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GET /api/1.0/patches/2197538/?format=api
{ "id": 2197538, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197538/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260218-wakeirq_support-v7-3-0d4689830207@oss.qualcomm.com>", "date": "2026-02-18T08:12:25", "name": "[v7,3/3] PCI: Add support for PCIe WAKE# interrupt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bb4b467cd3515255ffde686a20e11c06255ff95c", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.0/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260218-wakeirq_support-v7-3-0d4689830207@oss.qualcomm.com/mbox/", "series": [ { "id": 492518, "url": "http://patchwork.ozlabs.org/api/1.0/series/492518/?format=api", "date": "2026-02-18T08:12:23", "name": "PCI: Add support for PCIe WAKE# interrupt", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/492518/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197538/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-31778-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=bQcCVZVL;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZZJKswC7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260218-wakeirq_support-v7-3-0d4689830207@oss.qualcomm.com>", "References": "<20260218-wakeirq_support-v7-0-0d4689830207@oss.qualcomm.com>", "In-Reply-To": "<20260218-wakeirq_support-v7-0-0d4689830207@oss.qualcomm.com>", "To": "\"Rafael J. Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n Pavel Machek <pavel@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Bartosz Golaszewski <brgl@bgdev.pl>,\n Linus Walleij <linusw@kernel.org>,\n Bartosz Golaszewski <brgl@kernel.org>,\n Linus Walleij <linusw@kernel.org>", "Cc": "linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org,\n quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, sherry.sun@nxp.com,\n driver-core@lists.linux.dev,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1771402347; l=7967;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=YyvIpWrTFLi6XlA78epLgR4oDc+qO1nmiVhSzx9chWw=;\n b=T9yc43Z0e8+NjXJSIlHu3tdFO6HaY32cKsWHdKZZ2VqhHBCDBrlY90crKCb6DxcOXTnxOfSLF\n 9SUKBwO4bV5D1Zrj1R2rRIXSVgYARNPyuZm3lMN/9oxEZq/mzzo65Bk", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-GUID": "04YQoexdIKlA34TWv2_wrfx3n6AbGAmy", "X-Authority-Analysis": "v=2.4 cv=R7oO2NRX c=1 sm=1 tr=0 ts=69957484 cx=c_pps\n a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8\n a=ttF918e8ocTVMR-R1j4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22\n a=cvBusfyB2V15izCimMoJ:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjE4MDA3MSBTYWx0ZWRfXxZQXwlpE/6dX\n fMdE89bEhjIc9OhHJ0BuG29Tlw2rwAemTLfCCKS725QEsydYMGvZmOZnp4Fx+uVovm5GuPKMr2o\n fisIikQkrRQ52bplh5RD/Q5nKBl3Rt3ryzvQ9o2z6LzOv7xVzm40ClJxiqo/kNm0KqDLGGaDnNR\n /2xccINTjHWbYO77Eww7MvuNSewg3KuSvnnweWU30feHgzsU7MSGz5/ElE1TSRRd3MCGfVRwOmX\n L5EGuAF7o+W1cFasVA61CArsLkXCxoHadEF3SKtbNV20xD+9/rvmLitncImeknswvXJMgWQpVeL\n niipyl0TDBjaJ/4FOnOnLvVCOrjFJr3PAm7/xMR9V9kDa4u5F2D8Y9YqPMOQeaGL/2qwAERdhi6\n 2cJdGjUshf4G6mTXvNSJB95S+BJ1qBt+VhwYQxRLoclCp9TWv8iAhzZG9e3ti0uFw9OQ7K7Uqq4\n Aw9N2bj8W54otJes4Bg==", "X-Proofpoint-ORIG-GUID": "04YQoexdIKlA34TWv2_wrfx3n6AbGAmy", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-17_04,2026-02-16_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0\n lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602180071" }, "content": "According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2),\ntwo link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a\nhardware-only mechanism and is invisible to software (PCIe r7.0,\nSection 4.2.7.8.1). This change adds support for the WAKE# mechanism in\nthe PCI core.\n\nAccording to the PCIe specification, multiple WAKE# signals can exist in\na system or each component in the hierarchy could share a single WAKE#\nsignal. In configurations involving a PCIe switch, each downstream port\n(DSP) of the switch may be connected to a separate WAKE# line, allowing\neach endpoint to signal WAKE# independently. From figure 5.4 in sec\n5.3.3.2, WAKE# can also be terminated at the switch itself. To support\nthis, the WAKE# should be described in the device tree node of the\nendpoint/bridge. If all endpoints share a single WAKE# line, then each\nendpoint node should describe the same WAKE# signal or a single WAKE# in\nthe Root Port node.\n\nIn pci_device_add(), PCI framework will search for the WAKE# in device\nnode, If not found, it searches in its upstream port only if upstream port\nis Root Port. Once found, register for the wake IRQ in shared mode, as the\nWAKE# may be shared among multiple endpoints.\n\nWhen a device asserts WAKE#, PM core will wakeup the system, resume the\ndevice and its parent(s) in the hierarchy, which will cause the restoration\nof power and refclk to the device.\n\nWAKE# is added in dts schema and merged based on below links.\n\nLink: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/\nLink: https://github.com/devicetree-org/dt-schema/pull/170\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/of.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/pci/pci.c | 9 +++++++++\n drivers/pci/pci.h | 8 ++++++++\n drivers/pci/probe.c | 2 ++\n drivers/pci/remove.c | 1 +\n include/linux/pci.h | 2 ++\n 6 files changed, 77 insertions(+)", "diff": "diff --git a/drivers/pci/of.c b/drivers/pci/of.c\nindex 9bb5f258759be3f1e23496f083353600a4ef6743..23248900253faafaf9509d87c531b454fca41798 100644\n--- a/drivers/pci/of.c\n+++ b/drivers/pci/of.c\n@@ -7,6 +7,7 @@\n #define pr_fmt(fmt)\t\"PCI: OF: \" fmt\n \n #include <linux/cleanup.h>\n+#include <linux/gpio/consumer.h>\n #include <linux/irqdomain.h>\n #include <linux/kernel.h>\n #include <linux/pci.h>\n@@ -15,6 +16,7 @@\n #include <linux/of_address.h>\n #include <linux/of_pci.h>\n #include <linux/platform_device.h>\n+#include <linux/pm_wakeirq.h>\n #include \"pci.h\"\n \n #ifdef CONFIG_PCI\n@@ -586,6 +588,59 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)\n \treturn irq_create_of_mapping(&oirq);\n }\n EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);\n+\n+static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake)\n+{\n+\tint ret, wake_irq;\n+\n+\twake_irq = gpiod_to_irq(wake);\n+\tif (wake_irq < 0) {\n+\t\tpci_err(pdev, \"Failed to get wake irq: %d\\n\", wake_irq);\n+\t\treturn;\n+\t}\n+\n+\tdevice_init_wakeup(&pdev->dev, true);\n+\n+\tret = dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq,\n+\t\t\t\t\t\t IRQ_TYPE_EDGE_FALLING);\n+\tif (ret < 0) {\n+\t\tpci_err(pdev, \"Failed to set wake IRQ: %d\\n\", ret);\n+\t\tdevice_init_wakeup(&pdev->dev, false);\n+\t}\n+}\n+\n+void pci_configure_of_wake_gpio(struct pci_dev *dev)\n+{\n+\tstruct device_node *dn = pci_device_to_OF_node(dev);\n+\tstruct pci_dev *upstream;\n+\tstruct gpio_desc *gpio;\n+\n+\tif (!dn)\n+\t\treturn;\n+\n+\tgpio = fwnode_gpiod_get(of_fwnode_handle(dn), \"wake\",\n+\t\t\t\tGPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE, NULL);\n+\tif (IS_ERR(gpio)) {\n+\t\t/*\n+\t\t * In case the entire topology shares a single WAKE# signal, look for it\n+\t\t * in the upstream bridge node. But if it is not Root Port, then skip it.\n+\t\t */\n+\t\tupstream = pci_upstream_bridge(dev);\n+\t\tif (upstream && pci_is_root_bus(upstream->bus) && upstream->wake)\n+\t\t\tpci_configure_wake_irq(dev, upstream->wake);\n+\t} else {\n+\t\tdev->wake = gpio;\n+\t\tpci_configure_wake_irq(dev, gpio);\n+\t}\n+}\n+\n+void pci_remove_of_wake_gpio(struct pci_dev *dev)\n+{\n+\tdev_pm_clear_wake_irq(&dev->dev);\n+\tdevice_init_wakeup(&dev->dev, false);\n+\tgpiod_put(dev->wake);\n+\tdev->wake = NULL;\n+}\n #endif\t/* CONFIG_OF_IRQ */\n \n static int pci_parse_request_of_pci_ranges(struct device *dev,\ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex f3244630bfd05b15d52f866d80a015ed21f98f49..225cb861b3425700fc0d9d4805f5d9efcaab6f56 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -1123,6 +1123,15 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev)\n \treturn acpi_pci_bridge_d3(dev);\n }\n \n+void platform_pci_configure_wake(struct pci_dev *dev)\n+{\n+\treturn pci_configure_of_wake_gpio(dev);\n+}\n+\n+void platform_pci_remove_wake(struct pci_dev *dev)\n+{\n+\treturn pci_remove_of_wake_gpio(dev);\n+}\n /**\n * pci_update_current_state - Read power state of given device and cache it\n * @dev: PCI device to handle.\ndiff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 13d998fbacce6698514d92500dfea03cc562cdc2..22709573e41caf0ed45b20ee7ded5963f55aa9fe 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -282,6 +282,8 @@ void pci_msix_init(struct pci_dev *dev);\n bool pci_bridge_d3_possible(struct pci_dev *dev);\n void pci_bridge_d3_update(struct pci_dev *dev);\n int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);\n+void platform_pci_configure_wake(struct pci_dev *dev);\n+void platform_pci_remove_wake(struct pci_dev *dev);\n \n static inline bool pci_bus_rrs_vendor_id(u32 l)\n {\n@@ -1195,6 +1197,9 @@ void pci_release_of_node(struct pci_dev *dev);\n void pci_set_bus_of_node(struct pci_bus *bus);\n void pci_release_bus_of_node(struct pci_bus *bus);\n \n+void pci_configure_of_wake_gpio(struct pci_dev *dev);\n+void pci_remove_of_wake_gpio(struct pci_dev *dev);\n+\n int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);\n bool of_pci_supply_present(struct device_node *np);\n int of_pci_get_equalization_presets(struct device *dev,\n@@ -1240,6 +1245,9 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br\n \treturn 0;\n }\n \n+static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { }\n+static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { }\n+\n static inline bool of_pci_supply_present(struct device_node *np)\n {\n \treturn false;\ndiff --git a/drivers/pci/probe.c b/drivers/pci/probe.c\nindex 2975974f35e88b5025701d2b721df8386419de8d..7f5132c0c8de36a6ec2775468a3d4e5156a046d0 100644\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -2771,6 +2771,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)\n \t/* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */\n \tpci_tsm_init(dev);\n \n+\tplatform_pci_configure_wake(dev);\n+\n \tpci_npem_create(dev);\n \n \tpci_doe_sysfs_init(dev);\ndiff --git a/drivers/pci/remove.c b/drivers/pci/remove.c\nindex e9d519993853f92f1810d3eff9f44ca7e3e1abd9..d781b41e57c4444077075690cec926a9fe15334f 100644\n--- a/drivers/pci/remove.c\n+++ b/drivers/pci/remove.c\n@@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev)\n \tif (pci_dev_test_and_set_removed(dev))\n \t\treturn;\n \n+\tplatform_pci_remove_wake(dev);\n \tpci_doe_sysfs_teardown(dev);\n \tpci_npem_remove(dev);\n \ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 1c270f1d512301de4d462fe7e5097c32af5c6f8d..d1e08df8a8deaa87780589f23242767fdcdba541 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -586,6 +586,8 @@ struct pci_dev {\n \t/* These methods index pci_reset_fn_methods[] */\n \tu8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */\n \n+\tstruct gpio_desc *wake; /* Holds WAKE# gpio */\n+\n #ifdef CONFIG_PCIE_TPH\n \tu16\t\ttph_cap;\t/* TPH capability offset */\n \tu8\t\ttph_mode;\t/* TPH mode */\n", "prefixes": [ "v7", "3/3" ] }