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{
    "id": 2197494,
    "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197494/?format=api",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260217-mtk-mt8189-clocks-v2-7-cd381cd05251@baylibre.com>",
    "date": "2026-02-17T23:30:14",
    "name": "[v2,7/7] clk: mediatek: add clock driver for MT8189",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "f27d0484aee878d6bf0c5a25064e899b149d7e40",
    "submitter": {
        "id": 87228,
        "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api",
        "name": "David Lechner",
        "email": "dlechner@baylibre.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260217-mtk-mt8189-clocks-v2-7-cd381cd05251@baylibre.com/mbox/",
    "series": [
        {
            "id": 492497,
            "url": "http://patchwork.ozlabs.org/api/1.0/series/492497/?format=api",
            "date": "2026-02-17T23:30:08",
            "name": "clk: mediatek: new mt8189 driver",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/492497/mbox/"
        }
    ],
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2197494/checks/",
    "tags": {},
    "headers": {
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        "From": "David Lechner <dlechner@baylibre.com>",
        "Date": "Tue, 17 Feb 2026 17:30:14 -0600",
        "Subject": "[PATCH v2 7/7] clk: mediatek: add clock driver for MT8189",
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        "Message-Id": "<20260217-mtk-mt8189-clocks-v2-7-cd381cd05251@baylibre.com>",
        "References": "<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>",
        "In-Reply-To": "<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>",
        "To": "Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>",
        "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>,\n Chris Chen <chris-qj.chen@mediatek.com>",
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    "content": "From: Chris Chen <chris-qj.chen@mediatek.com>\n\nAdd new clock driver for MedaiTek MT8189 and compatible SoCs.\n\nSigned-off-by: Chris Chen <chris-qj.chen@mediatek.com>\nCo-developed-by: David Lechner <dlechner@baylibre.com>\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/Makefile     |    1 +\n drivers/clk/mediatek/clk-mt8189.c | 1738 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 1739 insertions(+)",
    "diff": "diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile\nindex 5bede819c0d..d4cac6aaf52 100644\n--- a/drivers/clk/mediatek/Makefile\n+++ b/drivers/clk/mediatek/Makefile\n@@ -12,6 +12,7 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o\n obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o\n obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o\n obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o\n+obj-$(CONFIG_TARGET_MT8189) += clk-mt8189.o\n obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o\n obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o\n obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o\ndiff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c\nnew file mode 100644\nindex 00000000000..093c4f2df86\n--- /dev/null\n+++ b/drivers/clk/mediatek/clk-mt8189.c\n@@ -0,0 +1,1738 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2026 MediaTek Inc.\n+ * Author: Chris Chen <chris-qj.chen@mediatek.com>\n+ * Author: David Lechner <dlechner@baylibre.com>\n+ */\n+\n+#include <dm.h>\n+#include <dt-bindings/clock/mediatek,mt8189-clk.h>\n+#include <linux/kernel.h>\n+\n+#include \"clk-mtk.h\"\n+\n+/* TOPCK MUX SEL REG */\n+#define CLK_CFG_UPDATE\t\t\t\t0x0004\n+#define CLK_CFG_UPDATE1\t\t\t\t0x0008\n+#define CLK_CFG_UPDATE2\t\t\t\t0x000c\n+#define VLP_CLK_CFG_UPDATE\t\t\t0x0004\n+#define CLK_CFG_0\t\t\t\t0x0010\n+#define CLK_CFG_0_SET\t\t\t\t0x0014\n+#define CLK_CFG_0_CLR\t\t\t\t0x0018\n+#define CLK_CFG_1\t\t\t\t0x0020\n+#define CLK_CFG_1_SET\t\t\t\t0x0024\n+#define CLK_CFG_1_CLR\t\t\t\t0x0028\n+#define CLK_CFG_2\t\t\t\t0x0030\n+#define CLK_CFG_2_SET\t\t\t\t0x0034\n+#define CLK_CFG_2_CLR\t\t\t\t0x0038\n+#define CLK_CFG_3\t\t\t\t0x0040\n+#define CLK_CFG_3_SET\t\t\t\t0x0044\n+#define CLK_CFG_3_CLR\t\t\t\t0x0048\n+#define CLK_CFG_4\t\t\t\t0x0050\n+#define CLK_CFG_4_SET\t\t\t\t0x0054\n+#define CLK_CFG_4_CLR\t\t\t\t0x0058\n+#define CLK_CFG_5\t\t\t\t0x0060\n+#define CLK_CFG_5_SET\t\t\t\t0x0064\n+#define CLK_CFG_5_CLR\t\t\t\t0x0068\n+#define CLK_CFG_6\t\t\t\t0x0070\n+#define CLK_CFG_6_SET\t\t\t\t0x0074\n+#define CLK_CFG_6_CLR\t\t\t\t0x0078\n+#define CLK_CFG_7\t\t\t\t0x0080\n+#define CLK_CFG_7_SET\t\t\t\t0x0084\n+#define CLK_CFG_7_CLR\t\t\t\t0x0088\n+#define CLK_CFG_8\t\t\t\t0x0090\n+#define CLK_CFG_8_SET\t\t\t\t0x0094\n+#define CLK_CFG_8_CLR\t\t\t\t0x0098\n+#define CLK_CFG_9\t\t\t\t0x00A0\n+#define CLK_CFG_9_SET\t\t\t\t0x00A4\n+#define CLK_CFG_9_CLR\t\t\t\t0x00A8\n+#define CLK_CFG_10\t\t\t\t0x00B0\n+#define CLK_CFG_10_SET\t\t\t\t0x00B4\n+#define CLK_CFG_10_CLR\t\t\t\t0x00B8\n+#define CLK_CFG_11\t\t\t\t0x00C0\n+#define CLK_CFG_11_SET\t\t\t\t0x00C4\n+#define CLK_CFG_11_CLR\t\t\t\t0x00C8\n+#define CLK_CFG_12\t\t\t\t0x00D0\n+#define CLK_CFG_12_SET\t\t\t\t0x00D4\n+#define CLK_CFG_12_CLR\t\t\t\t0x00D8\n+#define CLK_CFG_13\t\t\t\t0x00E0\n+#define CLK_CFG_13_SET\t\t\t\t0x00E4\n+#define CLK_CFG_13_CLR\t\t\t\t0x00E8\n+#define CLK_CFG_14\t\t\t\t0x00F0\n+#define CLK_CFG_14_SET\t\t\t\t0x00F4\n+#define CLK_CFG_14_CLR\t\t\t\t0x00F8\n+#define CLK_CFG_15\t\t\t\t0x0100\n+#define CLK_CFG_15_SET\t\t\t\t0x0104\n+#define CLK_CFG_15_CLR\t\t\t\t0x0108\n+#define CLK_CFG_16\t\t\t\t0x0110\n+#define CLK_CFG_16_SET\t\t\t\t0x0114\n+#define CLK_CFG_16_CLR\t\t\t\t0x0118\n+#define CLK_CFG_17\t\t\t\t0x0180\n+#define CLK_CFG_17_SET\t\t\t\t0x0184\n+#define CLK_CFG_17_CLR\t\t\t\t0x0188\n+#define CLK_CFG_18\t\t\t\t0x0190\n+#define CLK_CFG_18_SET\t\t\t\t0x0194\n+#define CLK_CFG_18_CLR\t\t\t\t0x0198\n+#define CLK_CFG_19\t\t\t\t0x0240\n+#define CLK_CFG_19_SET\t\t\t\t0x0244\n+#define CLK_CFG_19_CLR\t\t\t\t0x0248\n+#define CLK_AUDDIV_0\t\t\t\t0x0320\n+#define CLK_MISC_CFG_3\t\t\t\t0x0510\n+#define CLK_MISC_CFG_3_SET\t\t\t0x0514\n+#define CLK_MISC_CFG_3_CLR\t\t\t0x0518\n+#define VLP_CLK_CFG_0\t\t\t\t0x0008\n+#define VLP_CLK_CFG_0_SET\t\t\t0x000C\n+#define VLP_CLK_CFG_0_CLR\t\t\t0x0010\n+#define VLP_CLK_CFG_1\t\t\t\t0x0014\n+#define VLP_CLK_CFG_1_SET\t\t\t0x0018\n+#define VLP_CLK_CFG_1_CLR\t\t\t0x001C\n+#define VLP_CLK_CFG_2\t\t\t\t0x0020\n+#define VLP_CLK_CFG_2_SET\t\t\t0x0024\n+#define VLP_CLK_CFG_2_CLR\t\t\t0x0028\n+#define VLP_CLK_CFG_3\t\t\t\t0x002C\n+#define VLP_CLK_CFG_3_SET\t\t\t0x0030\n+#define VLP_CLK_CFG_3_CLR\t\t\t0x0034\n+#define VLP_CLK_CFG_4\t\t\t\t0x0038\n+#define VLP_CLK_CFG_4_SET\t\t\t0x003C\n+#define VLP_CLK_CFG_4_CLR\t\t\t0x0040\n+#define VLP_CLK_CFG_5\t\t\t\t0x0044\n+#define VLP_CLK_CFG_5_SET\t\t\t0x0048\n+#define VLP_CLK_CFG_5_CLR\t\t\t0x004C\n+\n+/* TOPCK MUX SHIFT */\n+#define TOP_MUX_AXI_SHIFT\t\t\t0\n+#define TOP_MUX_AXI_PERI_SHIFT\t\t\t1\n+#define TOP_MUX_AXI_UFS_SHIFT\t\t\t2\n+#define TOP_MUX_BUS_AXIMEM_SHIFT\t\t3\n+#define TOP_MUX_DISP0_SHIFT\t\t\t4\n+#define TOP_MUX_MMINFRA_SHIFT\t\t\t5\n+#define TOP_MUX_UART_SHIFT\t\t\t6\n+#define TOP_MUX_SPI0_SHIFT\t\t\t7\n+#define TOP_MUX_SPI1_SHIFT\t\t\t8\n+#define TOP_MUX_SPI2_SHIFT\t\t\t9\n+#define TOP_MUX_SPI3_SHIFT\t\t\t10\n+#define TOP_MUX_SPI4_SHIFT\t\t\t11\n+#define TOP_MUX_SPI5_SHIFT\t\t\t12\n+#define TOP_MUX_MSDC_MACRO_0P_SHIFT\t\t13\n+#define TOP_MUX_MSDC50_0_HCLK_SHIFT\t\t14\n+#define TOP_MUX_MSDC50_0_SHIFT\t\t\t15\n+#define TOP_MUX_AES_MSDCFDE_SHIFT\t\t16\n+#define TOP_MUX_MSDC_MACRO_1P_SHIFT\t\t17\n+#define TOP_MUX_MSDC30_1_SHIFT\t\t\t18\n+#define TOP_MUX_MSDC30_1_HCLK_SHIFT\t\t19\n+#define TOP_MUX_MSDC_MACRO_2P_SHIFT\t\t20\n+#define TOP_MUX_MSDC30_2_SHIFT\t\t\t21\n+#define TOP_MUX_MSDC30_2_HCLK_SHIFT\t\t22\n+#define TOP_MUX_AUD_INTBUS_SHIFT\t\t23\n+#define TOP_MUX_ATB_SHIFT\t\t\t24\n+#define TOP_MUX_DISP_PWM_SHIFT\t\t\t25\n+#define TOP_MUX_USB_TOP_P0_SHIFT\t\t26\n+#define TOP_MUX_SSUSB_XHCI_P0_SHIFT\t\t27\n+#define TOP_MUX_USB_TOP_P1_SHIFT\t\t28\n+#define TOP_MUX_SSUSB_XHCI_P1_SHIFT\t\t29\n+#define TOP_MUX_USB_TOP_P2_SHIFT\t\t30\n+#define TOP_MUX_SSUSB_XHCI_P2_SHIFT\t\t0\n+#define TOP_MUX_USB_TOP_P3_SHIFT\t\t1\n+#define TOP_MUX_SSUSB_XHCI_P3_SHIFT\t\t2\n+#define TOP_MUX_USB_TOP_P4_SHIFT\t\t3\n+#define TOP_MUX_SSUSB_XHCI_P4_SHIFT\t\t4\n+#define TOP_MUX_I2C_SHIFT\t\t\t5\n+#define TOP_MUX_SENINF_SHIFT\t\t\t6\n+#define TOP_MUX_SENINF1_SHIFT\t\t\t7\n+#define TOP_MUX_AUD_ENGEN1_SHIFT\t\t8\n+#define TOP_MUX_AUD_ENGEN2_SHIFT\t\t9\n+#define TOP_MUX_AES_UFSFDE_SHIFT\t\t10\n+#define TOP_MUX_UFS_SHIFT\t\t\t11\n+#define TOP_MUX_UFS_MBIST_SHIFT\t\t\t12\n+#define TOP_MUX_AUD_1_SHIFT\t\t\t13\n+#define TOP_MUX_AUD_2_SHIFT\t\t\t14\n+#define TOP_MUX_VENC_SHIFT\t\t\t15\n+#define TOP_MUX_VDEC_SHIFT\t\t\t16\n+#define TOP_MUX_PWM_SHIFT\t\t\t17\n+#define TOP_MUX_AUDIO_H_SHIFT\t\t\t18\n+#define TOP_MUX_MCUPM_SHIFT\t\t\t19\n+#define TOP_MUX_MEM_SUB_SHIFT\t\t\t20\n+#define TOP_MUX_MEM_SUB_PERI_SHIFT\t\t21\n+#define TOP_MUX_MEM_SUB_UFS_SHIFT\t\t22\n+#define TOP_MUX_EMI_N_SHIFT\t\t\t23\n+#define TOP_MUX_DSI_OCC_SHIFT\t\t\t24\n+#define TOP_MUX_AP2CONN_HOST_SHIFT\t\t25\n+#define TOP_MUX_IMG1_SHIFT\t\t\t26\n+#define TOP_MUX_IPE_SHIFT\t\t\t27\n+#define TOP_MUX_CAM_SHIFT\t\t\t28\n+#define TOP_MUX_CAMTM_SHIFT\t\t\t29\n+#define TOP_MUX_DSP_SHIFT\t\t\t30\n+#define TOP_MUX_SR_PKA_SHIFT\t\t\t0\n+#define TOP_MUX_DXCC_SHIFT\t\t\t1\n+#define TOP_MUX_MFG_REF_SHIFT\t\t\t2\n+#define TOP_MUX_MDP0_SHIFT\t\t\t3\n+#define TOP_MUX_DP_SHIFT\t\t\t4\n+#define TOP_MUX_EDP_SHIFT\t\t\t5\n+#define TOP_MUX_EDP_FAVT_SHIFT\t\t\t6\n+#define TOP_MUX_SNPS_ETH_250M_SHIFT\t\t7\n+#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT\t8\n+#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT\t\t9\n+#define TOP_MUX_SFLASH_SHIFT\t\t\t10\n+#define TOP_MUX_GCPU_SHIFT\t\t\t11\n+#define TOP_MUX_PCIE_MAC_TL_SHIFT\t\t12\n+#define TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT\t\t13\n+#define TOP_MUX_PLL_DPIX_SHIFT\t\t\t14\n+#define TOP_MUX_ECC_SHIFT\t\t\t15\n+#define TOP_MUX_SCP_SHIFT\t\t\t0\n+#define TOP_MUX_PWRAP_ULPOSC_SHIFT\t\t1\n+#define TOP_MUX_SPMI_P_MST_SHIFT\t\t2\n+#define TOP_MUX_DVFSRC_SHIFT\t\t\t3\n+#define TOP_MUX_PWM_VLP_SHIFT\t\t\t4\n+#define TOP_MUX_AXI_VLP_SHIFT\t\t\t5\n+#define TOP_MUX_SYSTIMER_26M_SHIFT\t\t6\n+#define TOP_MUX_SSPM_SHIFT\t\t\t7\n+#define TOP_MUX_SSPM_F26M_SHIFT\t\t\t8\n+#define TOP_MUX_SRCK_SHIFT\t\t\t9\n+#define TOP_MUX_SCP_SPI_SHIFT\t\t\t10\n+#define TOP_MUX_SCP_IIC_SHIFT\t\t\t11\n+#define TOP_MUX_SCP_SPI_HIGH_SPD_SHIFT\t\t12\n+#define TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT\t\t13\n+#define TOP_MUX_SSPM_ULPOSC_SHIFT\t\t14\n+#define TOP_MUX_APXGPT_26M_SHIFT\t\t15\n+#define TOP_MUX_VADSP_SHIFT\t\t\t16\n+#define TOP_MUX_VADSP_VOWPLL_SHIFT\t\t17\n+#define TOP_MUX_VADSP_UARTHUB_BCLK_SHIFT\t18\n+#define TOP_MUX_CAMTG0_SHIFT\t\t\t19\n+#define TOP_MUX_CAMTG1_SHIFT\t\t\t20\n+#define TOP_MUX_CAMTG2_SHIFT\t\t\t21\n+#define TOP_MUX_AUD_ADC_SHIFT\t\t\t22\n+#define TOP_MUX_KP_IRQ_GEN_SHIFT\t\t23\n+\n+/* TOPCK DIVIDER REG */\n+#define CLK_AUDDIV_2\t\t\t\t0x0328\n+#define CLK_AUDDIV_3\t\t\t\t0x0334\n+#define CLK_AUDDIV_5\t\t\t\t0x033C\n+\n+/* APMIXED PLL REG */\n+#define AP_PLL_CON3\t\t\t\t0x00C\n+#define APLL1_TUNER_CON0\t\t\t0x040\n+#define APLL2_TUNER_CON0\t\t\t0x044\n+#define ARMPLL_LL_CON0\t\t\t\t0x204\n+#define ARMPLL_LL_CON1\t\t\t\t0x208\n+#define ARMPLL_LL_CON2\t\t\t\t0x20C\n+#define ARMPLL_LL_CON3\t\t\t\t0x210\n+#define ARMPLL_BL_CON0\t\t\t\t0x214\n+#define ARMPLL_BL_CON1\t\t\t\t0x218\n+#define ARMPLL_BL_CON2\t\t\t\t0x21C\n+#define ARMPLL_BL_CON3\t\t\t\t0x220\n+#define CCIPLL_CON0\t\t\t\t0x224\n+#define CCIPLL_CON1\t\t\t\t0x228\n+#define CCIPLL_CON2\t\t\t\t0x22C\n+#define CCIPLL_CON3\t\t\t\t0x230\n+#define MAINPLL_CON0\t\t\t\t0x304\n+#define MAINPLL_CON1\t\t\t\t0x308\n+#define MAINPLL_CON2\t\t\t\t0x30C\n+#define MAINPLL_CON3\t\t\t\t0x310\n+#define UNIVPLL_CON0\t\t\t\t0x314\n+#define UNIVPLL_CON1\t\t\t\t0x318\n+#define UNIVPLL_CON2\t\t\t\t0x31C\n+#define UNIVPLL_CON3\t\t\t\t0x320\n+#define MMPLL_CON0\t\t\t\t0x324\n+#define MMPLL_CON1\t\t\t\t0x328\n+#define MMPLL_CON2\t\t\t\t0x32C\n+#define MMPLL_CON3\t\t\t\t0x330\n+#define MFGPLL_CON0\t\t\t\t0x504\n+#define MFGPLL_CON1\t\t\t\t0x508\n+#define MFGPLL_CON2\t\t\t\t0x50C\n+#define MFGPLL_CON3\t\t\t\t0x510\n+#define APLL1_CON0\t\t\t\t0x404\n+#define APLL1_CON1\t\t\t\t0x408\n+#define APLL1_CON2\t\t\t\t0x40C\n+#define APLL1_CON3\t\t\t\t0x410\n+#define APLL1_CON4\t\t\t\t0x414\n+#define APLL2_CON0\t\t\t\t0x418\n+#define APLL2_CON1\t\t\t\t0x41C\n+#define APLL2_CON2\t\t\t\t0x420\n+#define APLL2_CON3\t\t\t\t0x424\n+#define APLL2_CON4\t\t\t\t0x428\n+#define EMIPLL_CON0\t\t\t\t0x334\n+#define EMIPLL_CON1\t\t\t\t0x338\n+#define EMIPLL_CON2\t\t\t\t0x33C\n+#define EMIPLL_CON3\t\t\t\t0x340\n+#define APUPLL2_CON0\t\t\t\t0x614\n+#define APUPLL2_CON1\t\t\t\t0x618\n+#define APUPLL2_CON2\t\t\t\t0x61C\n+#define APUPLL2_CON3\t\t\t\t0x620\n+#define APUPLL_CON0\t\t\t\t0x604\n+#define APUPLL_CON1\t\t\t\t0x608\n+#define APUPLL_CON2\t\t\t\t0x60C\n+#define APUPLL_CON3\t\t\t\t0x610\n+#define TVDPLL1_CON0\t\t\t\t0x42C\n+#define TVDPLL1_CON1\t\t\t\t0x430\n+#define TVDPLL1_CON2\t\t\t\t0x434\n+#define TVDPLL1_CON3\t\t\t\t0x438\n+#define TVDPLL2_CON0\t\t\t\t0x43C\n+#define TVDPLL2_CON1\t\t\t\t0x440\n+#define TVDPLL2_CON2\t\t\t\t0x444\n+#define TVDPLL2_CON3\t\t\t\t0x448\n+#define ETHPLL_CON0\t\t\t\t0x514\n+#define ETHPLL_CON1\t\t\t\t0x518\n+#define ETHPLL_CON2\t\t\t\t0x51C\n+#define ETHPLL_CON3\t\t\t\t0x520\n+#define MSDCPLL_CON0\t\t\t\t0x524\n+#define MSDCPLL_CON1\t\t\t\t0x528\n+#define MSDCPLL_CON2\t\t\t\t0x52C\n+#define MSDCPLL_CON3\t\t\t\t0x530\n+#define UFSPLL_CON0\t\t\t\t0x534\n+#define UFSPLL_CON1\t\t\t\t0x538\n+#define UFSPLL_CON2\t\t\t\t0x53C\n+#define UFSPLL_CON3\t\t\t\t0x540\n+\n+#define CLK_PAD_CLK32K\t\t\t0\n+#define CLK_PAD_CLK26M\t\t\t1\n+#define CLK_PAD_ULPOSC\t\t\t2\n+\n+static ulong pad_clks[] = {\n+\t[CLK_PAD_CLK32K] = 32000,\n+\t[CLK_PAD_CLK26M] = 26000000,\n+\t[CLK_PAD_ULPOSC] = 260000000,\n+};\n+\n+#define MT8189_PLL_FMAX\t\t(3800UL * MHZ)\n+#define MT8189_PLL_FMIN\t\t(1500UL * MHZ)\n+\n+#define PLL(_id, _reg, _flags, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, _pcwbits) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.id = _id,\t\t\t\t\t\t\\\n+\t\t.reg = _reg,\t\t\t\t\t\t\\\n+\t\t.flags = (_flags),\t\t\t\t\t\\\n+\t\t.fmax = MT8189_PLL_FMAX,\t\t\t\t\\\n+\t\t.fmin = MT8189_PLL_FMIN,\t\t\t\t\\\n+\t\t.pd_reg = _pd_reg,\t\t\t\t\t\\\n+\t\t.pd_shift = _pd_shift,\t\t\t\t\t\\\n+\t\t.pcw_reg = _pcw_reg,\t\t\t\t\t\\\n+\t\t.pcw_shift = _pcw_shift,\t\t\t\t\\\n+\t\t.pcwbits = _pcwbits,\t\t\t\t\t\\\n+\t\t.pcwibits = 8,\t\t\t\t\t\t\\\n+\t}\n+\n+static const struct mtk_pll_data apmixed_plls[] = {\n+\tPLL(CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_CON0, 0, ARMPLL_LL_CON1, 24, ARMPLL_LL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_CON0, 0, ARMPLL_BL_CON1, 24, ARMPLL_BL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_CCIPLL, CCIPLL_CON0, 0, CCIPLL_CON1, 24, CCIPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_MAINPLL, MAINPLL_CON0, 0, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_UNIVPLL, UNIVPLL_CON0, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_MMPLL, MMPLL_CON0, 0, MMPLL_CON1, 24, MMPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_MFGPLL, MFGPLL_CON0, 0, MFGPLL_CON1, 24, MFGPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_APLL1, APLL1_CON0, 0, APLL1_CON1, 24, APLL1_CON2, 0, 32),\n+\tPLL(CLK_APMIXED_APLL2, APLL2_CON0, 0, APLL2_CON1, 24, APLL2_CON2, 0, 32),\n+\tPLL(CLK_APMIXED_EMIPLL, EMIPLL_CON0, 0, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_APUPLL2, APUPLL2_CON0, 0, APUPLL2_CON1, 24, APUPLL2_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_APUPLL, APUPLL_CON0, 0, APUPLL_CON1, 24, APUPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_TVDPLL1, TVDPLL1_CON0, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_TVDPLL2, TVDPLL2_CON0, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_ETHPLL, ETHPLL_CON0, 0, ETHPLL_CON1, 24, ETHPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_MSDCPLL, MSDCPLL_CON0, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22),\n+\tPLL(CLK_APMIXED_UFSPLL, UFSPLL_CON0, 0, UFSPLL_CON1, 24, UFSPLL_CON1, 0, 22),\n+};\n+\n+static const struct mtk_fixed_factor top_fixed_divs[] = {\n+\tFACTOR(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D4_D2, CLK_APMIXED_MAINPLL, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D4_D4, CLK_APMIXED_MAINPLL, 1, 16, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D4_D8, CLK_APMIXED_MAINPLL, 43, 1375, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D5_D2, CLK_APMIXED_MAINPLL, 1, 10, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D5_D4, CLK_APMIXED_MAINPLL, 1, 20, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D5_D8, CLK_APMIXED_MAINPLL, 1, 40, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D6_D2, CLK_APMIXED_MAINPLL, 1, 12, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D6_D4, CLK_APMIXED_MAINPLL, 1, 24, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D6_D8, CLK_APMIXED_MAINPLL, 1, 48, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D7_D2, CLK_APMIXED_MAINPLL, 1, 14, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D7_D4, CLK_APMIXED_MAINPLL, 1, 28, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D7_D8, CLK_APMIXED_MAINPLL, 1, 56, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D4_D2, CLK_APMIXED_UNIVPLL, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D4_D4, CLK_APMIXED_UNIVPLL, 1, 16, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D4_D8, CLK_APMIXED_UNIVPLL, 1, 32, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_APMIXED_UNIVPLL, 1, 10, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_APMIXED_UNIVPLL, 1, 20, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D6_D2, CLK_APMIXED_UNIVPLL, 1, 12, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D6_D4, CLK_APMIXED_UNIVPLL, 1, 24, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D6_D8, CLK_APMIXED_UNIVPLL, 1, 48, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D6_D16, CLK_APMIXED_UNIVPLL, 1, 96, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D7_D2, CLK_APMIXED_UNIVPLL, 1, 14, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_D7_D3, CLK_APMIXED_UNIVPLL, 1, 21, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_LVDSTX_DG_CTS, CLK_APMIXED_UNIVPLL, 1, 21, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D2, CLK_APMIXED_UNIVPLL, 1, 26, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D4, CLK_APMIXED_UNIVPLL, 1, 52, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D8, CLK_APMIXED_UNIVPLL, 1, 104, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D10, CLK_APMIXED_UNIVPLL, 1, 130, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D16, CLK_APMIXED_UNIVPLL, 1, 208, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_UNIVPLL_192M_D32, CLK_APMIXED_UNIVPLL, 1, 416, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D4_D2, CLK_APMIXED_MMPLL, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D4_D4, CLK_APMIXED_MMPLL, 1, 16, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_VPLL_DPIX, CLK_APMIXED_MMPLL, 1, 16, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D5_D2, CLK_APMIXED_MMPLL, 1, 10, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D5_D4, CLK_APMIXED_MMPLL, 1, 20, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D6_D2, CLK_APMIXED_MMPLL, 1, 12, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 92, 1473, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 92, 1473, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_VOWPLL, CLK_PAD_CLK26M, 1, 1, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_UFSPLL_D2, CLK_APMIXED_UFSPLL, 1, 2, CLK_PARENT_APMIXED),\n+\tFACTOR(CLK_TOP_F26M_CK_D2, CLK_PAD_CLK26M, 1, 2, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D2, CLK_PAD_ULPOSC, 1, 2, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D4, CLK_PAD_ULPOSC, 1, 4, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D8, CLK_PAD_ULPOSC, 1, 8, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D16, CLK_PAD_ULPOSC, 61, 973, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D3, CLK_PAD_ULPOSC, 1, 3, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D7, CLK_PAD_ULPOSC, 1, 7, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D10, CLK_PAD_ULPOSC, 1, 10, CLK_PARENT_EXT),\n+\tFACTOR(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20, CLK_PARENT_EXT),\n+};\n+\n+static const struct mtk_parent axi_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent axi_peri_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent axi_u_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D8, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent bus_aximem_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent disp0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_TVDPLL1, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_APMIXED_TVDPLL2, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mminfra_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_EMIPLL, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent uart_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D8, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi3_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi4_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent spi5_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_192M, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc_macro_0p_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_MSDCPLL, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_MMPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc5hclk_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc50_0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_MSDCPLL, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aes_msdcfde_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_MSDCPLL, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent msdc_macro_1p_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_MSDCPLL, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_MMPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc30_1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc30_1_h_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc_macro_2p_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_MSDCPLL, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_MMPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc30_2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent msdc30_2_h_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aud_intbus_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent atb_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent disp_pwm_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D16, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent usb_p0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ssusb_xhci_p0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent usb_p1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ssusb_xhci_p1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent usb_p2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ssusb_xhci_p2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent usb_p3_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ssusb_xhci_p3_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent usb_p4_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ssusb_xhci_p4_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent i2c_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent seninf_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent seninf1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aud_engen1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_APLL1_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL1_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL1_D8, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aud_engen2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_APLL2_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL2_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL2_D8, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aes_ufsfde_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ufs_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MSDCPLL_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ufs_mbist_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UFSPLL_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent aud_1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_APLL1, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent aud_2_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_APMIXED_APLL2, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent venc_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MMPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D9, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent vdec_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_192M_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent pwm_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D8, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent audio_h_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_APLL1, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_APMIXED_APLL2, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent mcupm_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mem_sub_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mem_sub_peri_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mem_sub_u_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent emi_n_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D9, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_EMIPLL, CLK_PARENT_APMIXED),\n+};\n+\n+static const struct mtk_parent dsi_occ_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ap2conn_host_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent img1_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ipe_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent cam_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D9, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent camtm_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent dsp_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_OSC_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D3, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_OSC_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D7_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent sr_pka_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent dxcc_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mfg_ref_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent mdp0_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_APMIXED_TVDPLL1, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_APMIXED_TVDPLL2, CLK_PARENT_APMIXED),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent dp_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_TVDPLL1_D16, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL1_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL1_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL1_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent edp_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_TVDPLL2_D16, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL1_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL2_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent edp_favt_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_TVDPLL2_D16, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_TVDPLL2_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL1_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL2_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent snps_eth_250m_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_ETHPLL_D2, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_ETHPLL_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL1_D3, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_APLL2_D3, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent snps_eth_50m_rmii_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_ETHPLL_D10, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent sflash_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D8, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D7_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D7_D3, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent gcpu_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent pcie_mac_tl_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_MAINPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D5_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent vdstx_dg_cts_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_LVDSTX_DG_CTS, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D7_D3, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent pll_dpix_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_VPLL_DPIX, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MMPLL_D4_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+static const struct mtk_parent ecc_parents[] = {\n+\tPARENT(CLK_PAD_CLK26M, CLK_PARENT_EXT),\n+\tPARENT(CLK_TOP_UNIVPLL_D6_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4_D2, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D6, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_MAINPLL_D4, CLK_PARENT_TOPCKGEN),\n+\tPARENT(CLK_TOP_UNIVPLL_D4, CLK_PARENT_TOPCKGEN),\n+};\n+\n+#define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,\t\\\n+\t\t\t_shift, _width,\t_upd_ofs, _upd)\t\t\t\t\\\n+\tMUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\t\\\n+\t\t\t\t    _mux_clr_ofs, _shift, _width, -1, _upd_ofs,\t\\\n+\t\t\t\t    _upd, CLK_MUX_SETCLR_UPD)\n+\n+#define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs,\t\t\\\n+\t\t\t      _mux_clr_ofs, _shift, _width, _gate, _upd_ofs,\t\\\n+\t\t\t      _upd)\t\t\t\t\t\t\\\n+\tMUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\t\\\n+\t\t\t\t   _mux_clr_ofs, _shift, _width, _gate,\t\t\\\n+\t\t\t\t   _upd_ofs, _upd, CLK_MUX_SETCLR_UPD)\n+\n+const struct mtk_composite top_muxes[] = {\n+\t/* CLK_CFG_0 */\n+\tMUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents, CLK_CFG_0, CLK_CFG_0_SET,\n+\t\t\tCLK_CFG_0_CLR, 0, 3, CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, axi_peri_parents, CLK_CFG_0,\n+\t\t\tCLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 2, CLK_CFG_UPDATE,\n+\t\t\tTOP_MUX_AXI_PERI_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, axi_u_parents, CLK_CFG_0,\n+\t\t\tCLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 2, CLK_CFG_UPDATE,\n+\t\t\tTOP_MUX_AXI_UFS_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, bus_aximem_parents, CLK_CFG_0,\n+\t\t\tCLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, CLK_CFG_UPDATE,\n+\t\t\tTOP_MUX_BUS_AXIMEM_SHIFT),\n+\t/* CLK_CFG_1 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, disp0_parents, CLK_CFG_1,\n+\t\t\t     CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 4, 7,\n+\t\t\t\t\tCLK_CFG_UPDATE, TOP_MUX_DISP0_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, mminfra_parents, CLK_CFG_1,\n+\t\t\t     CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 4, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, uart_parents, CLK_CFG_1,\n+\t\t\t     CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 1, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, spi0_parents, CLK_CFG_1,\n+\t\t\t     CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI0_SHIFT),\n+\t/* CLK_CFG_2 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, spi1_parents, CLK_CFG_2,\n+\t\t\t     CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 3, 7,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, spi2_parents, CLK_CFG_2,\n+\t\t\t     CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI2_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, spi3_parents, CLK_CFG_2,\n+\t\t\t     CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI3_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, spi4_parents, CLK_CFG_2,\n+\t\t\t     CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI4_SHIFT),\n+\t/* CLK_CFG_3 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, spi5_parents, CLK_CFG_3,\n+\t\t\t     CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 3, 7,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SPI5_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, msdc_macro_0p_parents,\n+\t\t\t     CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 2, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_0P_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, msdc5hclk_parents,\n+\t\t\t     CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_HCLK_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, CLK_CFG_3,\n+\t\t\t     CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 3, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_SHIFT),\n+\t/* CLK_CFG_4 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, aes_msdcfde_parents,\n+\t\t\t     CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 3, 7,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_AES_MSDCFDE_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, msdc_macro_1p_parents,\n+\t\t\t     CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_1P_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, CLK_CFG_4,\n+\t\t\t     CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, msdc30_1_h_parents,\n+\t\t\t     CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_HCLK_SHIFT),\n+\t/* CLK_CFG_5 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, msdc_macro_2p_parents,\n+\t\t\t     CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_2P_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, msdc30_2_parents, CLK_CFG_5,\n+\t\t\t     CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, msdc30_2_h_parents,\n+\t\t\t     CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_HCLK_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,\n+\t\t\t     CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_AUD_INTBUS_SHIFT),\n+\t/* CLK_CFG_6 */\n+\tMUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, atb_parents, CLK_CFG_6, CLK_CFG_6_SET,\n+\t\t\tCLK_CFG_6_CLR, 0, 2, CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, CLK_CFG_6,\n+\t\t\t     CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_DISP_PWM_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, usb_p0_parents, CLK_CFG_6,\n+\t\t\t     CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P0_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, ssusb_xhci_p0_parents,\n+\t\t\t     CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P0_SHIFT),\n+\t/* CLK_CFG_7 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, usb_p1_parents, CLK_CFG_7,\n+\t\t\t     CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, ssusb_xhci_p1_parents,\n+\t\t\t     CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, usb_p2_parents, CLK_CFG_7,\n+\t\t\t     CLK_CFG_7_SET, CLK_CFG_7_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P2_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, ssusb_xhci_p2_parents,\n+\t\t\t     CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P2_SHIFT),\n+\t/* CLK_CFG_8 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, usb_p3_parents, CLK_CFG_8,\n+\t\t\t     CLK_CFG_8_SET, CLK_CFG_8_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P3_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, ssusb_xhci_p3_parents,\n+\t\t\t     CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 8, 2, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P3_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, usb_p4_parents, CLK_CFG_8,\n+\t\t\t     CLK_CFG_8_SET, CLK_CFG_8_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P4_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, ssusb_xhci_p4_parents,\n+\t\t\t     CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P4_SHIFT),\n+\t/* CLK_CFG_9 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, i2c_parents, CLK_CFG_9,\n+\t\t\t     CLK_CFG_9_SET, CLK_CFG_9_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_I2C_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, seninf_parents,\n+\t\t\t     CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_SENINF_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, seninf1_parents, CLK_CFG_9,\n+\t\t\t     CLK_CFG_9_SET, CLK_CFG_9_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_SENINF1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents,\n+\t\t\t     CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT),\n+\t/* CLK_CFG_10 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents,\n+\t\t\t     CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, aes_ufsfde_parents,\n+\t\t\t     CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_U_SEL, ufs_parents, CLK_CFG_10,\n+\t\t\t     CLK_CFG_10_SET, CLK_CFG_10_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, ufs_mbist_parents, CLK_CFG_10,\n+\t\t\t     CLK_CFG_10_SET, CLK_CFG_10_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_UFS_MBIST_SHIFT),\n+\t/* CLK_CFG_11 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, aud_1_parents, CLK_CFG_11,\n+\t\t\t     CLK_CFG_11_SET, CLK_CFG_11_CLR, 0, 1, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, aud_2_parents, CLK_CFG_11,\n+\t\t\t     CLK_CFG_11_SET, CLK_CFG_11_CLR, 8, 1, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, venc_parents, CLK_CFG_11,\n+\t\t\t     CLK_CFG_11_SET, CLK_CFG_11_CLR, 16, 4, 23,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_VENC_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, vdec_parents, CLK_CFG_11,\n+\t\t\t     CLK_CFG_11_SET, CLK_CFG_11_CLR, 24, 4, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_VDEC_SHIFT),\n+\t/* CLK_CFG_12 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, pwm_parents, CLK_CFG_12,\n+\t\t\t     CLK_CFG_12_SET, CLK_CFG_12_CLR, 0, 1, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, audio_h_parents, CLK_CFG_12,\n+\t\t\t     CLK_CFG_12_SET, CLK_CFG_12_CLR, 8, 2, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, mcupm_parents, CLK_CFG_12,\n+\t\t\tCLK_CFG_12_SET, CLK_CFG_12_CLR, 16, 2, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_MCUPM_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, mem_sub_parents, CLK_CFG_12,\n+\t\t\tCLK_CFG_12_SET, CLK_CFG_12_CLR, 24, 4, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_MEM_SUB_SHIFT),\n+\t/* CLK_CFG_13 */\n+\tMUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, mem_sub_peri_parents, CLK_CFG_13,\n+\t\t\tCLK_CFG_13_SET, CLK_CFG_13_CLR, 0, 3, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_MEM_SUB_PERI_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, mem_sub_u_parents, CLK_CFG_13,\n+\t\t\tCLK_CFG_13_SET, CLK_CFG_13_CLR, 8, 3, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_MEM_SUB_UFS_SHIFT),\n+\tMUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, emi_n_parents, CLK_CFG_13,\n+\t\t\tCLK_CFG_13_SET, CLK_CFG_13_CLR, 16, 3, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_EMI_N_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, dsi_occ_parents, CLK_CFG_13,\n+\t\t\t     CLK_CFG_13_SET, CLK_CFG_13_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_DSI_OCC_SHIFT),\n+\t/* CLK_CFG_14 */\n+\tMUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, ap2conn_host_parents, CLK_CFG_14,\n+\t\t\tCLK_CFG_14_SET, CLK_CFG_14_CLR, 0, 1, CLK_CFG_UPDATE1,\n+\t\t\tTOP_MUX_AP2CONN_HOST_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, img1_parents, CLK_CFG_14,\n+\t\t\t     CLK_CFG_14_SET, CLK_CFG_14_CLR, 8, 4, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_IMG1_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, ipe_parents, CLK_CFG_14,\n+\t\t\t     CLK_CFG_14_SET, CLK_CFG_14_CLR, 16, 4, 23,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_IPE_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, cam_parents, CLK_CFG_14,\n+\t\t\t     CLK_CFG_14_SET, CLK_CFG_14_CLR, 24, 4, 31,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_CAM_SHIFT),\n+\t/* CLK_CFG_15 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, camtm_parents, CLK_CFG_15,\n+\t\t\t     CLK_CFG_15_SET, CLK_CFG_15_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_CAMTM_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, dsp_parents, CLK_CFG_15,\n+\t\t\t     CLK_CFG_15_SET, CLK_CFG_15_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE1, TOP_MUX_DSP_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, sr_pka_parents, CLK_CFG_15,\n+\t\t\t     CLK_CFG_15_SET, CLK_CFG_15_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_SR_PKA_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, dxcc_parents, CLK_CFG_15,\n+\t\t\t     CLK_CFG_15_SET, CLK_CFG_15_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),\n+\t/* CLK_CFG_16 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, mfg_ref_parents, CLK_CFG_16,\n+\t\t\t     CLK_CFG_16_SET, CLK_CFG_16_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_MFG_REF_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, mdp0_parents, CLK_CFG_16,\n+\t\t\t     CLK_CFG_16_SET, CLK_CFG_16_CLR, 8, 4, 15,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_MDP0_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, dp_parents, CLK_CFG_16,\n+\t\t\t     CLK_CFG_16_SET, CLK_CFG_16_CLR, 16, 3, 23,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_DP_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, edp_parents, CLK_CFG_16,\n+\t\t\t     CLK_CFG_16_SET, CLK_CFG_16_CLR, 24, 3, 31,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_EDP_SHIFT),\n+\t/* CLK_CFG_17 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, edp_favt_parents, CLK_CFG_17,\n+\t\t\t     CLK_CFG_17_SET, CLK_CFG_17_CLR, 0, 3, 7,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_EDP_FAVT_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, snps_eth_250m_parents, CLK_CFG_17,\n+\t\t\t     CLK_CFG_17_SET, CLK_CFG_17_CLR, 8, 1, 15,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_250M_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL,\n+\t\t\t     snps_eth_62p4m_ptp_parents, CLK_CFG_17,\n+\t\t\t     CLK_CFG_17_SET, CLK_CFG_17_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL,\n+\t\t\t     snps_eth_50m_rmii_parents, CLK_CFG_17,\n+\t\t\t     CLK_CFG_17_SET, CLK_CFG_17_CLR, 24, 1, 31,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_50M_RMII_SHIFT),\n+\t/* CLK_CFG_18 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, sflash_parents, CLK_CFG_18,\n+\t\t\t     CLK_CFG_18_SET, CLK_CFG_18_CLR, 0, 3, 7,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_SFLASH_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, gcpu_parents, CLK_CFG_18,\n+\t\t\t     CLK_CFG_18_SET, CLK_CFG_18_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_GCPU_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, pcie_mac_tl_parents, CLK_CFG_18,\n+\t\t\t     CLK_CFG_18_SET, CLK_CFG_18_CLR, 16, 2, 23,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_PCIE_MAC_TL_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, vdstx_dg_cts_parents, CLK_CFG_18,\n+\t\t\t     CLK_CFG_18_SET, CLK_CFG_18_CLR, 24, 2, 31,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT),\n+\t/* CLK_CFG_19 */\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, pll_dpix_parents, CLK_CFG_19,\n+\t\t\t     CLK_CFG_19_SET, CLK_CFG_19_CLR, 0, 2, 7,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_PLL_DPIX_SHIFT),\n+\tMUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, ecc_parents, CLK_CFG_19,\n+\t\t\t     CLK_CFG_19_SET, CLK_CFG_19_CLR, 8, 3, 15,\n+\t\t\t     CLK_CFG_UPDATE2, TOP_MUX_ECC_SHIFT),\n+};\n+\n+static const struct mtk_gate_regs top_cg_regs = {\n+\t.set_ofs = 0x514,\n+\t.clr_ofs = 0x518,\n+\t.sta_ofs = 0x510,\n+};\n+\n+#define GATE_TOP(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &top_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_EXT | CLK_GATE_NO_SETCLR_INV)\n+\n+static const struct mtk_gate top_gates[] = {\n+\tGATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, CLK_PAD_CLK26M, 7),\n+\tGATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, CLK_PAD_CLK26M, 10),\n+\tGATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, CLK_PAD_CLK26M, 11),\n+\tGATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, CLK_PAD_CLK26M, 12),\n+\tGATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, CLK_PAD_CLK26M, 13),\n+};\n+\n+static const struct mtk_gate_regs perao0_cg_regs = {\n+\t.set_ofs = 0x24,\n+\t.clr_ofs = 0x28,\n+\t.sta_ofs = 0x10,\n+};\n+\n+static const struct mtk_gate_regs perao1_cg_regs = {\n+\t.set_ofs = 0x2C,\n+\t.clr_ofs = 0x30,\n+\t.sta_ofs = 0x14,\n+};\n+\n+static const struct mtk_gate_regs perao2_cg_regs = {\n+\t.set_ofs = 0x34,\n+\t.clr_ofs = 0x38,\n+\t.sta_ofs = 0x18,\n+};\n+\n+#define GATE_PERAO0(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+#define GATE_PERAO0P(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_EXT | CLK_GATE_SETCLR)\n+\n+#define GATE_PERAO1(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+#define GATE_PERAO1P(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_EXT | CLK_GATE_SETCLR)\n+\n+#define GATE_PERAO2(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+#define GATE_PERAO2P(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_EXT | CLK_GATE_SETCLR)\n+\n+static const struct mtk_gate perao_clks[] = {\n+\t/* PERAO0 */\n+\tGATE_PERAO0(CLK_PERAO_UART0, CLK_TOP_UART_SEL, 0),\n+\tGATE_PERAO0(CLK_PERAO_UART1, CLK_TOP_UART_SEL, 1),\n+\tGATE_PERAO0(CLK_PERAO_UART2, CLK_TOP_UART_SEL, 2),\n+\tGATE_PERAO0(CLK_PERAO_UART3, CLK_TOP_UART_SEL, 3),\n+\tGATE_PERAO0(CLK_PERAO_PWM_H, CLK_TOP_AXI_PERI_SEL, 4),\n+\tGATE_PERAO0(CLK_PERAO_PWM_B, CLK_TOP_PWM_SEL, 5),\n+\tGATE_PERAO0(CLK_PERAO_PWM_FB1, CLK_TOP_PWM_SEL, 6),\n+\tGATE_PERAO0(CLK_PERAO_PWM_FB2, CLK_TOP_PWM_SEL, 7),\n+\tGATE_PERAO0(CLK_PERAO_PWM_FB3, CLK_TOP_PWM_SEL, 8),\n+\tGATE_PERAO0(CLK_PERAO_PWM_FB4, CLK_TOP_PWM_SEL, 9),\n+\tGATE_PERAO0(CLK_PERAO_DISP_PWM0, CLK_TOP_DISP_PWM_SEL, 10),\n+\tGATE_PERAO0(CLK_PERAO_DISP_PWM1, CLK_TOP_DISP_PWM_SEL, 11),\n+\tGATE_PERAO0(CLK_PERAO_SPI0_B, CLK_TOP_SPI0_SEL, 12),\n+\tGATE_PERAO0(CLK_PERAO_SPI1_B, CLK_TOP_SPI1_SEL, 13),\n+\tGATE_PERAO0(CLK_PERAO_SPI2_B, CLK_TOP_SPI2_SEL, 14),\n+\tGATE_PERAO0(CLK_PERAO_SPI3_B, CLK_TOP_SPI3_SEL, 15),\n+\tGATE_PERAO0(CLK_PERAO_SPI4_B, CLK_TOP_SPI4_SEL, 16),\n+\tGATE_PERAO0(CLK_PERAO_SPI5_B, CLK_TOP_SPI5_SEL, 17),\n+\tGATE_PERAO0(CLK_PERAO_SPI0_H, CLK_TOP_AXI_PERI_SEL, 18),\n+\tGATE_PERAO0(CLK_PERAO_SPI1_H, CLK_TOP_AXI_PERI_SEL, 19),\n+\tGATE_PERAO0(CLK_PERAO_SPI2_H, CLK_TOP_AXI_PERI_SEL, 20),\n+\tGATE_PERAO0(CLK_PERAO_SPI3_H, CLK_TOP_AXI_PERI_SEL, 21),\n+\tGATE_PERAO0(CLK_PERAO_SPI4_H, CLK_TOP_AXI_PERI_SEL, 22),\n+\tGATE_PERAO0(CLK_PERAO_SPI5_H, CLK_TOP_AXI_PERI_SEL, 23),\n+\tGATE_PERAO0(CLK_PERAO_AXI, CLK_TOP_MEM_SUB_PERI_SEL, 24),\n+\tGATE_PERAO0(CLK_PERAO_AHB_APB, CLK_TOP_AXI_PERI_SEL, 25),\n+\tGATE_PERAO0(CLK_PERAO_TL, CLK_TOP_MAC_TL_SEL, 26),\n+\tGATE_PERAO0P(CLK_PERAO_REF, CLK_PAD_CLK26M, 27),\n+\tGATE_PERAO0(CLK_PERAO_I2C, CLK_TOP_AXI_PERI_SEL, 28),\n+\tGATE_PERAO0(CLK_PERAO_DMA_B, CLK_TOP_AXI_PERI_SEL, 29),\n+\t/* PERAO1 */\n+\tGATE_PERAO1P(CLK_PERAO_SSUSB0_REF, CLK_PAD_CLK26M, 1),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 2),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB0_SYS, CLK_TOP_USB_TOP_P0_SEL, 4),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, CLK_TOP_USB_XHCI_P0_SEL, 5),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB0_F, CLK_TOP_AXI_PERI_SEL, 6),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB0_H, CLK_TOP_AXI_PERI_SEL, 7),\n+\tGATE_PERAO1P(CLK_PERAO_SSUSB1_REF, CLK_PAD_CLK26M, 8),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 9),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB1_SYS, CLK_TOP_USB_TOP_P1_SEL, 11),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, CLK_TOP_USB_XHCI_P1_SEL, 12),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB1_F, CLK_TOP_AXI_PERI_SEL, 13),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB1_H, CLK_TOP_AXI_PERI_SEL, 14),\n+\tGATE_PERAO1P(CLK_PERAO_SSUSB2_REF, CLK_PAD_CLK26M, 15),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 16),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB2_SYS, CLK_TOP_USB_TOP_P2_SEL, 18),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, CLK_TOP_USB_XHCI_P2_SEL, 19),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB2_F, CLK_TOP_AXI_PERI_SEL, 20),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB2_H, CLK_TOP_AXI_PERI_SEL, 21),\n+\tGATE_PERAO1P(CLK_PERAO_SSUSB3_REF, CLK_PAD_CLK26M, 23),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 24),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB3_SYS, CLK_TOP_USB_TOP_P3_SEL, 26),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, CLK_TOP_USB_XHCI_P3_SEL, 27),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB3_F, CLK_TOP_AXI_PERI_SEL, 28),\n+\tGATE_PERAO1(CLK_PERAO_SSUSB3_H, CLK_TOP_AXI_PERI_SEL, 29),\n+\t/* PERAO2 */\n+\tGATE_PERAO2P(CLK_PERAO_SSUSB4_REF, CLK_PAD_CLK26M, 0),\n+\tGATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 1),\n+\tGATE_PERAO2(CLK_PERAO_SSUSB4_SYS, CLK_TOP_USB_TOP_P4_SEL, 3),\n+\tGATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, CLK_TOP_USB_XHCI_P4_SEL, 4),\n+\tGATE_PERAO2(CLK_PERAO_SSUSB4_F, CLK_TOP_AXI_PERI_SEL, 5),\n+\tGATE_PERAO2(CLK_PERAO_SSUSB4_H, CLK_TOP_AXI_PERI_SEL, 6),\n+\tGATE_PERAO2(CLK_PERAO_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),\n+\tGATE_PERAO2(CLK_PERAO_MSDC0_H, CLK_TOP_MSDC50_0_HCLK_SEL, 8),\n+\tGATE_PERAO2(CLK_PERAO_MSDC0_FAES, CLK_TOP_AES_MSDCFDE_SEL, 9),\n+\tGATE_PERAO2(CLK_PERAO_MSDC0_MST_F, CLK_TOP_AXI_PERI_SEL, 10),\n+\tGATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, CLK_TOP_AXI_PERI_SEL, 11),\n+\tGATE_PERAO2(CLK_PERAO_MSDC1, CLK_TOP_MSDC30_1_SEL, 12),\n+\tGATE_PERAO2(CLK_PERAO_MSDC1_H, CLK_TOP_MSDC30_1_HCLK_SEL, 13),\n+\tGATE_PERAO2(CLK_PERAO_MSDC1_MST_F, CLK_TOP_AXI_PERI_SEL, 14),\n+\tGATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, CLK_TOP_AXI_PERI_SEL, 15),\n+\tGATE_PERAO2(CLK_PERAO_MSDC2, CLK_TOP_MSDC30_2_SEL, 16),\n+\tGATE_PERAO2(CLK_PERAO_MSDC2_H, CLK_TOP_MSDC30_2_HCLK_SEL, 17),\n+\tGATE_PERAO2(CLK_PERAO_MSDC2_MST_F, CLK_TOP_AXI_PERI_SEL, 18),\n+\tGATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, CLK_TOP_AXI_PERI_SEL, 19),\n+\tGATE_PERAO2(CLK_PERAO_SFLASH, CLK_TOP_SFLASH_SEL, 20),\n+\tGATE_PERAO2(CLK_PERAO_SFLASH_F, CLK_TOP_AXI_PERI_SEL, 21),\n+\tGATE_PERAO2(CLK_PERAO_SFLASH_H, CLK_TOP_AXI_PERI_SEL, 22),\n+\tGATE_PERAO2(CLK_PERAO_SFLASH_P, CLK_TOP_AXI_PERI_SEL, 23),\n+\tGATE_PERAO2(CLK_PERAO_AUDIO0, CLK_TOP_AXI_PERI_SEL, 24),\n+\tGATE_PERAO2(CLK_PERAO_AUDIO1, CLK_TOP_AXI_PERI_SEL, 25),\n+\tGATE_PERAO2(CLK_PERAO_AUDIO2, CLK_TOP_AUD_INTBUS_SEL, 26),\n+\tGATE_PERAO2P(CLK_PERAO_AUXADC_26M, CLK_PAD_CLK26M, 27),\n+};\n+\n+static const struct mtk_gate_regs imp_cg_regs = {\n+\t.set_ofs = 0xE08,\n+\t.clr_ofs = 0xE04,\n+\t.sta_ofs = 0xE00,\n+};\n+\n+#define GATE_IMP(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &imp_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+static const struct mtk_gate imp_clks[] = {\n+\tGATE_IMP(CLK_IMPE_I2C0, CLK_TOP_I2C_SEL, 0),\n+\tGATE_IMP(CLK_IMPE_I2C1, CLK_TOP_I2C_SEL, 1),\n+\tGATE_IMP(CLK_IMPWS_I2C2, CLK_TOP_I2C_SEL, 0),\n+\tGATE_IMP(CLK_IMPS_I2C3, CLK_TOP_I2C_SEL, 0),\n+\tGATE_IMP(CLK_IMPS_I2C4, CLK_TOP_I2C_SEL, 1),\n+\tGATE_IMP(CLK_IMPS_I2C5, CLK_TOP_I2C_SEL, 2),\n+\tGATE_IMP(CLK_IMPS_I2C6, CLK_TOP_I2C_SEL, 3),\n+\tGATE_IMP(CLK_IMPEN_I2C7, CLK_TOP_I2C_SEL, 0),\n+\tGATE_IMP(CLK_IMPEN_I2C8, CLK_TOP_I2C_SEL, 1),\n+};\n+\n+static const struct mtk_gate_regs mm0_cg_regs = {\n+\t.set_ofs = 0x104,\n+\t.clr_ofs = 0x108,\n+\t.sta_ofs = 0x100,\n+};\n+\n+static const struct mtk_gate_regs mm1_cg_regs = {\n+\t.set_ofs = 0x114,\n+\t.clr_ofs = 0x118,\n+\t.sta_ofs = 0x110,\n+};\n+\n+#define GATE_MM0(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &mm0_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+#define GATE_MM1(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+static const struct mtk_gate mm_clks[] = {\n+\t/* MM0 */\n+\tGATE_MM0(CLK_MM_DISP_OVL0_4L, CLK_TOP_DISP0_SEL, 0),\n+\tGATE_MM0(CLK_MM_DISP_OVL1_4L, CLK_TOP_DISP0_SEL, 1),\n+\tGATE_MM0(CLK_MM_VPP_RSZ0, CLK_TOP_DISP0_SEL, 2),\n+\tGATE_MM0(CLK_MM_VPP_RSZ1, CLK_TOP_DISP0_SEL, 3),\n+\tGATE_MM0(CLK_MM_DISP_RDMA0, CLK_TOP_DISP0_SEL, 4),\n+\tGATE_MM0(CLK_MM_DISP_RDMA1, CLK_TOP_DISP0_SEL, 5),\n+\tGATE_MM0(CLK_MM_DISP_COLOR0, CLK_TOP_DISP0_SEL, 6),\n+\tGATE_MM0(CLK_MM_DISP_COLOR1, CLK_TOP_DISP0_SEL, 7),\n+\tGATE_MM0(CLK_MM_DISP_CCORR0, CLK_TOP_DISP0_SEL, 8),\n+\tGATE_MM0(CLK_MM_DISP_CCORR1, CLK_TOP_DISP0_SEL, 9),\n+\tGATE_MM0(CLK_MM_DISP_CCORR2, CLK_TOP_DISP0_SEL, 10),\n+\tGATE_MM0(CLK_MM_DISP_CCORR3, CLK_TOP_DISP0_SEL, 11),\n+\tGATE_MM0(CLK_MM_DISP_AAL0, CLK_TOP_DISP0_SEL, 12),\n+\tGATE_MM0(CLK_MM_DISP_AAL1, CLK_TOP_DISP0_SEL, 13),\n+\tGATE_MM0(CLK_MM_DISP_GAMMA0, CLK_TOP_DISP0_SEL, 14),\n+\tGATE_MM0(CLK_MM_DISP_GAMMA1, CLK_TOP_DISP0_SEL, 15),\n+\tGATE_MM0(CLK_MM_DISP_DITHER0, CLK_TOP_DISP0_SEL, 16),\n+\tGATE_MM0(CLK_MM_DISP_DITHER1, CLK_TOP_DISP0_SEL, 17),\n+\tGATE_MM0(CLK_MM_DISP_DSC_WRAP0, CLK_TOP_DISP0_SEL, 18),\n+\tGATE_MM0(CLK_MM_VPP_MERGE0, CLK_TOP_DISP0_SEL, 19),\n+\tGATE_MM0(CLK_MMSYS_0_DISP_DVO, CLK_TOP_DISP0_SEL, 20),\n+\tGATE_MM0(CLK_MMSYS_0_DISP_DSI0, CLK_TOP_DISP0_SEL, 21),\n+\tGATE_MM0(CLK_MM_DP_INTF0, CLK_TOP_DISP0_SEL, 22),\n+\tGATE_MM0(CLK_MM_DPI0, CLK_TOP_DISP0_SEL, 23),\n+\tGATE_MM0(CLK_MM_DISP_WDMA0, CLK_TOP_DISP0_SEL, 24),\n+\tGATE_MM0(CLK_MM_DISP_WDMA1, CLK_TOP_DISP0_SEL, 25),\n+\tGATE_MM0(CLK_MM_DISP_FAKE_ENG0, CLK_TOP_DISP0_SEL, 26),\n+\tGATE_MM0(CLK_MM_DISP_FAKE_ENG1, CLK_TOP_DISP0_SEL, 27),\n+\tGATE_MM0(CLK_MM_SMI_LARB, CLK_TOP_DISP0_SEL, 28),\n+\tGATE_MM0(CLK_MM_DISP_MUTEX0, CLK_TOP_DISP0_SEL, 29),\n+\tGATE_MM0(CLK_MM_DIPSYS_CONFIG, CLK_TOP_DISP0_SEL, 30),\n+\tGATE_MM0(CLK_MM_DUMMY, CLK_TOP_DISP0_SEL, 31),\n+\t/* MM1 */\n+\tGATE_MM1(CLK_MMSYS_1_DISP_DSI0, CLK_TOP_DSI_OCC_SEL, 0),\n+\tGATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, CLK_TOP_PLL_DPIX_SEL, 1),\n+\tGATE_MM1(CLK_MMSYS_1_DPI0, CLK_TOP_PLL_DPIX_SEL, 2),\n+\tGATE_MM1(CLK_MMSYS_1_DISP_DVO, CLK_TOP_EDP_SEL, 3),\n+\tGATE_MM1(CLK_MM_DP_INTF, CLK_TOP_DP_SEL, 4),\n+\tGATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, CLK_TOP_VDSTX_DG_CTS_SEL, 5),\n+\tGATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, CLK_TOP_EDP_FAVT_SEL, 6),\n+};\n+\n+static const struct mtk_gate_regs mminfra_config0_cg_regs = {\n+\t.set_ofs = 0x104,\n+\t.clr_ofs = 0x108,\n+\t.sta_ofs = 0x100,\n+};\n+\n+static const struct mtk_gate_regs mminfra_config1_cg_regs = {\n+\t.set_ofs = 0x114,\n+\t.clr_ofs = 0x118,\n+\t.sta_ofs = 0x110,\n+};\n+\n+#define GATE_MMINFRA_CONFIG0(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &mminfra_config0_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+#define GATE_MMINFRA_CONFIG1(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &mminfra_config1_cg_regs, _shift, \\\n+\t\t   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)\n+\n+static const struct mtk_gate mminfra_config_clks[] = {\n+\tGATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, CLK_TOP_MMINFRA_SEL, 0),\n+\tGATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, CLK_TOP_MMINFRA_SEL, 1),\n+\tGATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, CLK_TOP_MMINFRA_SEL, 2),\n+\tGATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17),\n+};\n+\n+static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {\n+\t.xtal_rate = 26 * MHZ,\n+\t.xtal2_rate = 26 * MHZ,\n+\t.ext_clk_rates = pad_clks,\n+\t.num_ext_clks = ARRAY_SIZE(pad_clks),\n+\t.plls = apmixed_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+};\n+\n+static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {\n+\t.xtal_rate = 26 * MHZ,\n+\t.ext_clk_rates = pad_clks,\n+\t.num_ext_clks = ARRAY_SIZE(pad_clks),\n+\t.fdivs_offs = CLK_TOP_MAINPLL_D3,\n+\t.muxes_offs = CLK_TOP_AXI_SEL,\n+\t.gates_offs = CLK_TOP_USB2_PHY_RF_P0_EN,\n+\t.fdivs = top_fixed_divs,\n+\t.muxes = top_muxes,\n+\t.gates = top_gates,\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n+\t.num_gates = ARRAY_SIZE(top_gates),\n+};\n+\n+static const struct udevice_id mt8189_apmixed[] = {\n+\t{ .compatible = \"mediatek,mt8189-apmixedsys\", },\n+\t{ }\n+};\n+\n+static const struct udevice_id mt8189_topckgen_compat[] = {\n+\t{ .compatible = \"mediatek,mt8189-topckgen\", },\n+\t{ }\n+};\n+\n+struct mt8189_gate_clk_data {\n+\tconst struct mtk_gate *gates;\n+\tint num_gates;\n+};\n+\n+#define GATE_CLK_DATA(name) \\\n+static const struct mt8189_gate_clk_data name##_data = { \\\n+\t.gates = name, .num_gates = ARRAY_SIZE(name) \\\n+}\n+\n+GATE_CLK_DATA(perao_clks);\n+GATE_CLK_DATA(imp_clks);\n+GATE_CLK_DATA(mm_clks);\n+GATE_CLK_DATA(mminfra_config_clks);\n+\n+static const struct udevice_id of_match_mt8189_clk_gate[] = {\n+\t{ .compatible = \"mediatek,mt8189-peri-ao\", .data = (ulong)&perao_clks_data },\n+\t{ .compatible = \"mediatek,mt8189-iic-wrap\", .data = (ulong)&imp_clks_data },\n+\t{ .compatible = \"mediatek,mt8189-dispsys\", .data = (ulong)&mm_clks_data },\n+\t{ .compatible = \"mediatek,mt8189-mm-infra\", .data = (ulong)&mminfra_config_clks_data },\n+\t{ }\n+};\n+\n+static int mt8189_apmixedsys_probe(struct udevice *dev)\n+{\n+\treturn mtk_common_clk_init(dev, &mt8189_apmixedsys_clk_tree);\n+}\n+\n+static int mt8189_topckgen_probe(struct udevice *dev)\n+{\n+\treturn mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree);\n+}\n+\n+static int mt8189_clk_gate_probe(struct udevice *dev)\n+{\n+\tstruct mt8189_gate_clk_data *data;\n+\n+\tdata = (void *)dev_get_driver_data(dev);\n+\n+\treturn mtk_common_clk_gate_init(dev, &mt8189_topckgen_clk_tree,\n+\t\t\t\t\tdata->gates, data->num_gates,\n+\t\t\t\t\tdata->gates[0].id);\n+}\n+\n+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {\n+\t.name = \"mt8189-apmixedsys\",\n+\t.id = UCLASS_CLK,\n+\t.of_match = mt8189_apmixed,\n+\t.probe = mt8189_apmixedsys_probe,\n+\t.priv_auto = sizeof(struct mtk_clk_priv),\n+\t.ops = &mtk_clk_apmixedsys_ops,\n+\t.flags = DM_FLAG_PRE_RELOC,\n+};\n+\n+U_BOOT_DRIVER(mtk_clk_topckgen) = {\n+\t.name = \"mt8189-topckgen\",\n+\t.id = UCLASS_CLK,\n+\t.of_match = mt8189_topckgen_compat,\n+\t.probe = mt8189_topckgen_probe,\n+\t.priv_auto = sizeof(struct mtk_clk_priv),\n+\t.ops = &mtk_clk_topckgen_ops,\n+\t.flags = DM_FLAG_PRE_RELOC,\n+};\n+\n+U_BOOT_DRIVER(mtk_clk_gate) = {\n+\t.name = \"mt8189-gate-clk\",\n+\t.id = UCLASS_CLK,\n+\t.of_match = of_match_mt8189_clk_gate,\n+\t.probe = mt8189_clk_gate_probe,\n+\t.priv_auto = sizeof(struct mtk_cg_priv),\n+\t.ops = &mtk_clk_gate_ops,\n+\t.flags = DM_FLAG_PRE_RELOC,\n+};\n",
    "prefixes": [
        "v2",
        "7/7"
    ]
}