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{
    "id": 2197493,
    "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197493/?format=api",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260217-mtk-mt8189-clocks-v2-6-cd381cd05251@baylibre.com>",
    "date": "2026-02-17T23:30:13",
    "name": "[v2,6/7] dt-bindings: clock: Add MediaTek MT8189 clock",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "38b6af386abef7bdfa609d0fbdc622800610968e",
    "submitter": {
        "id": 87228,
        "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api",
        "name": "David Lechner",
        "email": "dlechner@baylibre.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260217-mtk-mt8189-clocks-v2-6-cd381cd05251@baylibre.com/mbox/",
    "series": [
        {
            "id": 492497,
            "url": "http://patchwork.ozlabs.org/api/1.0/series/492497/?format=api",
            "date": "2026-02-17T23:30:08",
            "name": "clk: mediatek: new mt8189 driver",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/492497/mbox/"
        }
    ],
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2197493/checks/",
    "tags": {},
    "headers": {
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        "From": "David Lechner <dlechner@baylibre.com>",
        "Date": "Tue, 17 Feb 2026 17:30:13 -0600",
        "Subject": "[PATCH v2 6/7] dt-bindings: clock: Add MediaTek MT8189 clock",
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        "Message-Id": "<20260217-mtk-mt8189-clocks-v2-6-cd381cd05251@baylibre.com>",
        "References": "<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>",
        "In-Reply-To": "<20260217-mtk-mt8189-clocks-v2-0-cd381cd05251@baylibre.com>",
        "To": "Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>",
        "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>,\n Irving-CH Lin <irving-ch.lin@mediatek.com>",
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    "content": "From: Irving-CH Lin <irving-ch.lin@mediatek.com>\n\nAdd IDs for the clocks of MediaTek MT8189 SoC.\n\nSigned-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n\nThis is just the header file portion of [1] which has been submitted\nupstream to the Linux project but is still under review. The intention\nis to eventually to switch to CONFIG_OF_UPSTREAM and remove this file\nfrom U-Boot once it is accepted in Linux and gets merged into U-Boot.\nThis can take a long time and we would like to have it in U-Boot sooner\neven if there will be some churn.\n\n[1] https://lore.kernel.org/linux-mediatek/20260202062840.342707-2-irving-ch.lin@mediatek.com/\n---\n include/dt-bindings/clock/mediatek,mt8189-clk.h | 580 ++++++++++++++++++++++++\n 1 file changed, 580 insertions(+)",
    "diff": "diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h\nnew file mode 100644\nindex 00000000000..ffbc1814f28\n--- /dev/null\n+++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h\n@@ -0,0 +1,580 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)  */\n+/*\n+ * Copyright (c) 2025 MediaTek Inc.\n+ * Author: Qiqi Wang <qiqi.wang@mediatek.com>\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_MT8189_H\n+#define _DT_BINDINGS_CLK_MT8189_H\n+\n+/* TOPCKGEN */\n+#define CLK_TOP_AXI_SEL\t\t\t\t\t0\n+#define CLK_TOP_AXI_PERI_SEL\t\t\t\t1\n+#define CLK_TOP_AXI_U_SEL\t\t\t\t2\n+#define CLK_TOP_BUS_AXIMEM_SEL\t\t\t\t3\n+#define CLK_TOP_DISP0_SEL\t\t\t\t4\n+#define CLK_TOP_MMINFRA_SEL\t\t\t\t5\n+#define CLK_TOP_UART_SEL\t\t\t\t6\n+#define CLK_TOP_SPI0_SEL\t\t\t\t7\n+#define CLK_TOP_SPI1_SEL\t\t\t\t8\n+#define CLK_TOP_SPI2_SEL\t\t\t\t9\n+#define CLK_TOP_SPI3_SEL\t\t\t\t10\n+#define CLK_TOP_SPI4_SEL\t\t\t\t11\n+#define CLK_TOP_SPI5_SEL\t\t\t\t12\n+#define CLK_TOP_MSDC_MACRO_0P_SEL\t\t\t13\n+#define CLK_TOP_MSDC50_0_HCLK_SEL\t\t\t14\n+#define CLK_TOP_MSDC50_0_SEL\t\t\t\t15\n+#define CLK_TOP_AES_MSDCFDE_SEL\t\t\t\t16\n+#define CLK_TOP_MSDC_MACRO_1P_SEL\t\t\t17\n+#define CLK_TOP_MSDC30_1_SEL\t\t\t\t18\n+#define CLK_TOP_MSDC30_1_HCLK_SEL\t\t\t19\n+#define CLK_TOP_MSDC_MACRO_2P_SEL\t\t\t20\n+#define CLK_TOP_MSDC30_2_SEL\t\t\t\t21\n+#define CLK_TOP_MSDC30_2_HCLK_SEL\t\t\t22\n+#define CLK_TOP_AUD_INTBUS_SEL\t\t\t\t23\n+#define CLK_TOP_ATB_SEL\t\t\t\t\t24\n+#define CLK_TOP_DISP_PWM_SEL\t\t\t\t25\n+#define CLK_TOP_USB_TOP_P0_SEL\t\t\t\t26\n+#define CLK_TOP_USB_XHCI_P0_SEL\t\t\t\t27\n+#define CLK_TOP_USB_TOP_P1_SEL\t\t\t\t28\n+#define CLK_TOP_USB_XHCI_P1_SEL\t\t\t\t29\n+#define CLK_TOP_USB_TOP_P2_SEL\t\t\t\t30\n+#define CLK_TOP_USB_XHCI_P2_SEL\t\t\t\t31\n+#define CLK_TOP_USB_TOP_P3_SEL\t\t\t\t32\n+#define CLK_TOP_USB_XHCI_P3_SEL\t\t\t\t33\n+#define CLK_TOP_USB_TOP_P4_SEL\t\t\t\t34\n+#define CLK_TOP_USB_XHCI_P4_SEL\t\t\t\t35\n+#define CLK_TOP_I2C_SEL\t\t\t\t\t36\n+#define CLK_TOP_SENINF_SEL\t\t\t\t37\n+#define CLK_TOP_SENINF1_SEL\t\t\t\t38\n+#define CLK_TOP_AUD_ENGEN1_SEL\t\t\t\t39\n+#define CLK_TOP_AUD_ENGEN2_SEL\t\t\t\t40\n+#define CLK_TOP_AES_UFSFDE_SEL\t\t\t\t41\n+#define CLK_TOP_U_SEL\t\t\t\t\t42\n+#define CLK_TOP_U_MBIST_SEL\t\t\t\t43\n+#define CLK_TOP_AUD_1_SEL\t\t\t\t44\n+#define CLK_TOP_AUD_2_SEL\t\t\t\t45\n+#define CLK_TOP_VENC_SEL\t\t\t\t46\n+#define CLK_TOP_VDEC_SEL\t\t\t\t47\n+#define CLK_TOP_PWM_SEL\t\t\t\t\t48\n+#define CLK_TOP_AUDIO_H_SEL\t\t\t\t49\n+#define CLK_TOP_MCUPM_SEL\t\t\t\t50\n+#define CLK_TOP_MEM_SUB_SEL\t\t\t\t51\n+#define CLK_TOP_MEM_SUB_PERI_SEL\t\t\t52\n+#define CLK_TOP_MEM_SUB_U_SEL\t\t\t\t53\n+#define CLK_TOP_EMI_N_SEL\t\t\t\t54\n+#define CLK_TOP_DSI_OCC_SEL\t\t\t\t55\n+#define CLK_TOP_AP2CONN_HOST_SEL\t\t\t56\n+#define CLK_TOP_IMG1_SEL\t\t\t\t57\n+#define CLK_TOP_IPE_SEL\t\t\t\t\t58\n+#define CLK_TOP_CAM_SEL\t\t\t\t\t59\n+#define CLK_TOP_CAMTM_SEL\t\t\t\t60\n+#define CLK_TOP_DSP_SEL\t\t\t\t\t61\n+#define CLK_TOP_SR_PKA_SEL\t\t\t\t62\n+#define CLK_TOP_DXCC_SEL\t\t\t\t63\n+#define CLK_TOP_MFG_REF_SEL\t\t\t\t64\n+#define CLK_TOP_MDP0_SEL\t\t\t\t65\n+#define CLK_TOP_DP_SEL\t\t\t\t\t66\n+#define CLK_TOP_EDP_SEL\t\t\t\t\t67\n+#define CLK_TOP_EDP_FAVT_SEL\t\t\t\t68\n+#define CLK_TOP_ETH_250M_SEL\t\t\t\t69\n+#define CLK_TOP_ETH_62P4M_PTP_SEL\t\t\t70\n+#define CLK_TOP_ETH_50M_RMII_SEL\t\t\t71\n+#define CLK_TOP_SFLASH_SEL\t\t\t\t72\n+#define CLK_TOP_GCPU_SEL\t\t\t\t73\n+#define CLK_TOP_MAC_TL_SEL\t\t\t\t74\n+#define CLK_TOP_VDSTX_DG_CTS_SEL\t\t\t75\n+#define CLK_TOP_PLL_DPIX_SEL\t\t\t\t76\n+#define CLK_TOP_ECC_SEL\t\t\t\t\t77\n+#define CLK_TOP_APLL_I2SIN0_MCK_SEL\t\t\t78\n+#define CLK_TOP_APLL_I2SIN1_MCK_SEL\t\t\t79\n+#define CLK_TOP_APLL_I2SIN2_MCK_SEL\t\t\t80\n+#define CLK_TOP_APLL_I2SIN3_MCK_SEL\t\t\t81\n+#define CLK_TOP_APLL_I2SIN4_MCK_SEL\t\t\t82\n+#define CLK_TOP_APLL_I2SIN6_MCK_SEL\t\t\t83\n+#define CLK_TOP_APLL_I2SOUT0_MCK_SEL\t\t\t84\n+#define CLK_TOP_APLL_I2SOUT1_MCK_SEL\t\t\t85\n+#define CLK_TOP_APLL_I2SOUT2_MCK_SEL\t\t\t86\n+#define CLK_TOP_APLL_I2SOUT3_MCK_SEL\t\t\t87\n+#define CLK_TOP_APLL_I2SOUT4_MCK_SEL\t\t\t88\n+#define CLK_TOP_APLL_I2SOUT6_MCK_SEL\t\t\t89\n+#define CLK_TOP_APLL_FMI2S_MCK_SEL\t\t\t90\n+#define CLK_TOP_APLL_TDMOUT_MCK_SEL\t\t\t91\n+#define CLK_TOP_MFG_SEL_MFGPLL\t\t\t\t92\n+#define CLK_TOP_APLL12_CK_DIV_I2SIN0\t\t\t93\n+#define CLK_TOP_APLL12_CK_DIV_I2SIN1\t\t\t94\n+#define CLK_TOP_APLL12_CK_DIV_I2SOUT0\t\t\t95\n+#define CLK_TOP_APLL12_CK_DIV_I2SOUT1\t\t\t96\n+#define CLK_TOP_APLL12_CK_DIV_FMI2S\t\t\t97\n+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M\t\t\t98\n+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B\t\t\t99\n+#define CLK_TOP_MAINPLL_D3\t\t\t\t100\n+#define CLK_TOP_MAINPLL_D4\t\t\t\t101\n+#define CLK_TOP_MAINPLL_D4_D2\t\t\t\t102\n+#define CLK_TOP_MAINPLL_D4_D4\t\t\t\t103\n+#define CLK_TOP_MAINPLL_D4_D8\t\t\t\t104\n+#define CLK_TOP_MAINPLL_D5\t\t\t\t105\n+#define CLK_TOP_MAINPLL_D5_D2\t\t\t\t106\n+#define CLK_TOP_MAINPLL_D5_D4\t\t\t\t107\n+#define CLK_TOP_MAINPLL_D5_D8\t\t\t\t108\n+#define CLK_TOP_MAINPLL_D6\t\t\t\t109\n+#define CLK_TOP_MAINPLL_D6_D2\t\t\t\t110\n+#define CLK_TOP_MAINPLL_D6_D4\t\t\t\t111\n+#define CLK_TOP_MAINPLL_D6_D8\t\t\t\t112\n+#define CLK_TOP_MAINPLL_D7\t\t\t\t113\n+#define CLK_TOP_MAINPLL_D7_D2\t\t\t\t114\n+#define CLK_TOP_MAINPLL_D7_D4\t\t\t\t115\n+#define CLK_TOP_MAINPLL_D7_D8\t\t\t\t116\n+#define CLK_TOP_MAINPLL_D9\t\t\t\t117\n+#define CLK_TOP_UNIVPLL_D2\t\t\t\t118\n+#define CLK_TOP_UNIVPLL_D3\t\t\t\t119\n+#define CLK_TOP_UNIVPLL_D4\t\t\t\t120\n+#define CLK_TOP_UNIVPLL_D4_D2\t\t\t\t121\n+#define CLK_TOP_UNIVPLL_D4_D4\t\t\t\t122\n+#define CLK_TOP_UNIVPLL_D4_D8\t\t\t\t123\n+#define CLK_TOP_UNIVPLL_D5\t\t\t\t124\n+#define CLK_TOP_UNIVPLL_D5_D2\t\t\t\t125\n+#define CLK_TOP_UNIVPLL_D5_D4\t\t\t\t126\n+#define CLK_TOP_UNIVPLL_D6\t\t\t\t127\n+#define CLK_TOP_UNIVPLL_D6_D2\t\t\t\t128\n+#define CLK_TOP_UNIVPLL_D6_D4\t\t\t\t129\n+#define CLK_TOP_UNIVPLL_D6_D8\t\t\t\t130\n+#define CLK_TOP_UNIVPLL_D6_D16\t\t\t\t131\n+#define CLK_TOP_UNIVPLL_D7\t\t\t\t132\n+#define CLK_TOP_UNIVPLL_D7_D2\t\t\t\t133\n+#define CLK_TOP_UNIVPLL_D7_D3\t\t\t\t134\n+#define CLK_TOP_LVDSTX_DG_CTS\t\t\t\t135\n+#define CLK_TOP_UNIVPLL_192M\t\t\t\t136\n+#define CLK_TOP_UNIVPLL_192M_D2\t\t\t\t137\n+#define CLK_TOP_UNIVPLL_192M_D4\t\t\t\t138\n+#define CLK_TOP_UNIVPLL_192M_D8\t\t\t\t139\n+#define CLK_TOP_UNIVPLL_192M_D10\t\t\t140\n+#define CLK_TOP_UNIVPLL_192M_D16\t\t\t141\n+#define CLK_TOP_UNIVPLL_192M_D32\t\t\t142\n+#define CLK_TOP_APLL1_D2\t\t\t\t143\n+#define CLK_TOP_APLL1_D4\t\t\t\t144\n+#define CLK_TOP_APLL1_D8\t\t\t\t145\n+#define CLK_TOP_APLL1_D3\t\t\t\t146\n+#define CLK_TOP_APLL2_D2\t\t\t\t147\n+#define CLK_TOP_APLL2_D4\t\t\t\t148\n+#define CLK_TOP_APLL2_D8\t\t\t\t149\n+#define CLK_TOP_APLL2_D3\t\t\t\t150\n+#define CLK_TOP_MMPLL_D4\t\t\t\t151\n+#define CLK_TOP_MMPLL_D4_D2\t\t\t\t152\n+#define CLK_TOP_MMPLL_D4_D4\t\t\t\t153\n+#define CLK_TOP_VPLL_DPIX\t\t\t\t154\n+#define CLK_TOP_MMPLL_D5\t\t\t\t155\n+#define CLK_TOP_MMPLL_D5_D2\t\t\t\t156\n+#define CLK_TOP_MMPLL_D5_D4\t\t\t\t157\n+#define CLK_TOP_MMPLL_D6\t\t\t\t158\n+#define CLK_TOP_MMPLL_D6_D2\t\t\t\t159\n+#define CLK_TOP_MMPLL_D7\t\t\t\t160\n+#define CLK_TOP_MMPLL_D9\t\t\t\t161\n+#define CLK_TOP_TVDPLL1_D2\t\t\t\t162\n+#define CLK_TOP_TVDPLL1_D4\t\t\t\t163\n+#define CLK_TOP_TVDPLL1_D8\t\t\t\t164\n+#define CLK_TOP_TVDPLL1_D16\t\t\t\t165\n+#define CLK_TOP_TVDPLL2_D2\t\t\t\t166\n+#define CLK_TOP_TVDPLL2_D4\t\t\t\t167\n+#define CLK_TOP_TVDPLL2_D8\t\t\t\t168\n+#define CLK_TOP_TVDPLL2_D16\t\t\t\t169\n+#define CLK_TOP_ETHPLL_D2\t\t\t\t170\n+#define CLK_TOP_ETHPLL_D8\t\t\t\t171\n+#define CLK_TOP_ETHPLL_D10\t\t\t\t172\n+#define CLK_TOP_MSDCPLL_D2\t\t\t\t173\n+#define CLK_TOP_VOWPLL\t\t\t\t\t174\n+#define CLK_TOP_UFSPLL_D2\t\t\t\t175\n+#define CLK_TOP_F26M_CK_D2\t\t\t\t176\n+#define CLK_TOP_OSC_D2\t\t\t\t\t177\n+#define CLK_TOP_OSC_D4\t\t\t\t\t178\n+#define CLK_TOP_OSC_D8\t\t\t\t\t179\n+#define CLK_TOP_OSC_D16\t\t\t\t\t180\n+#define CLK_TOP_OSC_D3\t\t\t\t\t181\n+#define CLK_TOP_OSC_D7\t\t\t\t\t182\n+#define CLK_TOP_OSC_D10\t\t\t\t\t183\n+#define CLK_TOP_OSC_D20\t\t\t\t\t184\n+#define CLK_TOP_FMCNT_P0_EN\t\t\t\t185\n+#define CLK_TOP_FMCNT_P1_EN\t\t\t\t186\n+#define CLK_TOP_FMCNT_P2_EN\t\t\t\t187\n+#define CLK_TOP_FMCNT_P3_EN\t\t\t\t188\n+#define CLK_TOP_FMCNT_P4_EN\t\t\t\t189\n+#define CLK_TOP_USB_F26M_CK_EN\t\t\t\t190\n+#define CLK_TOP_SSPXTP_F26M_CK_EN\t\t\t191\n+#define CLK_TOP_USB2_PHY_RF_P0_EN\t\t\t192\n+#define CLK_TOP_USB2_PHY_RF_P1_EN\t\t\t193\n+#define CLK_TOP_USB2_PHY_RF_P2_EN\t\t\t194\n+#define CLK_TOP_USB2_PHY_RF_P3_EN\t\t\t195\n+#define CLK_TOP_USB2_PHY_RF_P4_EN\t\t\t196\n+#define CLK_TOP_USB2_26M_CK_P0_EN\t\t\t197\n+#define CLK_TOP_USB2_26M_CK_P1_EN\t\t\t198\n+#define CLK_TOP_USB2_26M_CK_P2_EN\t\t\t199\n+#define CLK_TOP_USB2_26M_CK_P3_EN\t\t\t200\n+#define CLK_TOP_USB2_26M_CK_P4_EN\t\t\t201\n+#define CLK_TOP_F26M_CK_EN\t\t\t\t202\n+#define CLK_TOP_AP2CON_EN\t\t\t\t203\n+#define CLK_TOP_EINT_N_EN\t\t\t\t204\n+#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN\t\t205\n+#define CLK_TOP_DRAMULP_CK_EN\t\t\t\t206\n+#define CLK_TOP_EINT_E_EN\t\t\t\t207\n+#define CLK_TOP_EINT_W_EN\t\t\t\t208\n+#define CLK_TOP_EINT_S_EN\t\t\t\t209\n+\n+/* INFRACFG_AO */\n+#define CLK_IFRAO_CQ_DMA_FPC\t\t\t\t0\n+#define CLK_IFRAO_DEBUGSYS\t\t\t\t1\n+#define CLK_IFRAO_DBG_TRACE\t\t\t\t2\n+#define CLK_IFRAO_CQ_DMA\t\t\t\t3\n+\n+/* APMIXEDSYS */\n+#define CLK_APMIXED_ARMPLL_LL\t\t\t\t0\n+#define CLK_APMIXED_ARMPLL_BL\t\t\t\t1\n+#define CLK_APMIXED_CCIPLL\t\t\t\t2\n+#define CLK_APMIXED_MAINPLL\t\t\t\t3\n+#define CLK_APMIXED_UNIVPLL\t\t\t\t4\n+#define CLK_APMIXED_MMPLL\t\t\t\t5\n+#define CLK_APMIXED_MFGPLL\t\t\t\t6\n+#define CLK_APMIXED_APLL1\t\t\t\t7\n+#define CLK_APMIXED_APLL2\t\t\t\t8\n+#define CLK_APMIXED_EMIPLL\t\t\t\t9\n+#define CLK_APMIXED_APUPLL2\t\t\t\t10\n+#define CLK_APMIXED_APUPLL\t\t\t\t11\n+#define CLK_APMIXED_TVDPLL1\t\t\t\t12\n+#define CLK_APMIXED_TVDPLL2\t\t\t\t13\n+#define CLK_APMIXED_ETHPLL\t\t\t\t14\n+#define CLK_APMIXED_MSDCPLL\t\t\t\t15\n+#define CLK_APMIXED_UFSPLL\t\t\t\t16\n+\n+/* PERICFG_AO */\n+#define CLK_PERAO_UART0\t\t\t\t\t0\n+#define CLK_PERAO_UART1\t\t\t\t\t1\n+#define CLK_PERAO_UART2\t\t\t\t\t2\n+#define CLK_PERAO_UART3\t\t\t\t\t3\n+#define CLK_PERAO_PWM_H\t\t\t\t\t4\n+#define CLK_PERAO_PWM_B\t\t\t\t\t5\n+#define CLK_PERAO_PWM_FB1\t\t\t\t6\n+#define CLK_PERAO_PWM_FB2\t\t\t\t7\n+#define CLK_PERAO_PWM_FB3\t\t\t\t8\n+#define CLK_PERAO_PWM_FB4\t\t\t\t9\n+#define CLK_PERAO_DISP_PWM0\t\t\t\t10\n+#define CLK_PERAO_DISP_PWM1\t\t\t\t11\n+#define CLK_PERAO_SPI0_B\t\t\t\t12\n+#define CLK_PERAO_SPI1_B\t\t\t\t13\n+#define CLK_PERAO_SPI2_B\t\t\t\t14\n+#define CLK_PERAO_SPI3_B\t\t\t\t15\n+#define CLK_PERAO_SPI4_B\t\t\t\t16\n+#define CLK_PERAO_SPI5_B\t\t\t\t17\n+#define CLK_PERAO_SPI0_H\t\t\t\t18\n+#define CLK_PERAO_SPI1_H\t\t\t\t19\n+#define CLK_PERAO_SPI2_H\t\t\t\t20\n+#define CLK_PERAO_SPI3_H\t\t\t\t21\n+#define CLK_PERAO_SPI4_H\t\t\t\t22\n+#define CLK_PERAO_SPI5_H\t\t\t\t23\n+#define CLK_PERAO_AXI\t\t\t\t\t24\n+#define CLK_PERAO_AHB_APB\t\t\t\t25\n+#define CLK_PERAO_TL\t\t\t\t\t26\n+#define CLK_PERAO_REF\t\t\t\t\t27\n+#define CLK_PERAO_I2C\t\t\t\t\t28\n+#define CLK_PERAO_DMA_B\t\t\t\t\t29\n+#define CLK_PERAO_SSUSB0_REF\t\t\t\t30\n+#define CLK_PERAO_SSUSB0_FRMCNT\t\t\t\t31\n+#define CLK_PERAO_SSUSB0_SYS\t\t\t\t32\n+#define CLK_PERAO_SSUSB0_XHCI\t\t\t\t33\n+#define CLK_PERAO_SSUSB0_F\t\t\t\t34\n+#define CLK_PERAO_SSUSB0_H\t\t\t\t35\n+#define CLK_PERAO_SSUSB1_REF\t\t\t\t36\n+#define CLK_PERAO_SSUSB1_FRMCNT\t\t\t\t37\n+#define CLK_PERAO_SSUSB1_SYS\t\t\t\t38\n+#define CLK_PERAO_SSUSB1_XHCI\t\t\t\t39\n+#define CLK_PERAO_SSUSB1_F\t\t\t\t40\n+#define CLK_PERAO_SSUSB1_H\t\t\t\t41\n+#define CLK_PERAO_SSUSB2_REF\t\t\t\t42\n+#define CLK_PERAO_SSUSB2_FRMCNT\t\t\t\t43\n+#define CLK_PERAO_SSUSB2_SYS\t\t\t\t44\n+#define CLK_PERAO_SSUSB2_XHCI\t\t\t\t45\n+#define CLK_PERAO_SSUSB2_F\t\t\t\t46\n+#define CLK_PERAO_SSUSB2_H\t\t\t\t47\n+#define CLK_PERAO_SSUSB3_REF\t\t\t\t48\n+#define CLK_PERAO_SSUSB3_FRMCNT\t\t\t\t49\n+#define CLK_PERAO_SSUSB3_SYS\t\t\t\t50\n+#define CLK_PERAO_SSUSB3_XHCI\t\t\t\t51\n+#define CLK_PERAO_SSUSB3_F\t\t\t\t52\n+#define CLK_PERAO_SSUSB3_H\t\t\t\t53\n+#define CLK_PERAO_SSUSB4_REF\t\t\t\t54\n+#define CLK_PERAO_SSUSB4_FRMCNT\t\t\t\t55\n+#define CLK_PERAO_SSUSB4_SYS\t\t\t\t56\n+#define CLK_PERAO_SSUSB4_XHCI\t\t\t\t57\n+#define CLK_PERAO_SSUSB4_F\t\t\t\t58\n+#define CLK_PERAO_SSUSB4_H\t\t\t\t59\n+#define CLK_PERAO_MSDC0\t\t\t\t\t60\n+#define CLK_PERAO_MSDC0_H\t\t\t\t61\n+#define CLK_PERAO_MSDC0_FAES\t\t\t\t62\n+#define CLK_PERAO_MSDC0_MST_F\t\t\t\t63\n+#define CLK_PERAO_MSDC0_SLV_H\t\t\t\t64\n+#define CLK_PERAO_MSDC1\t\t\t\t\t65\n+#define CLK_PERAO_MSDC1_H\t\t\t\t66\n+#define CLK_PERAO_MSDC1_MST_F\t\t\t\t67\n+#define CLK_PERAO_MSDC1_SLV_H\t\t\t\t68\n+#define CLK_PERAO_MSDC2\t\t\t\t\t69\n+#define CLK_PERAO_MSDC2_H\t\t\t\t70\n+#define CLK_PERAO_MSDC2_MST_F\t\t\t\t71\n+#define CLK_PERAO_MSDC2_SLV_H\t\t\t\t72\n+#define CLK_PERAO_SFLASH\t\t\t\t73\n+#define CLK_PERAO_SFLASH_F\t\t\t\t74\n+#define CLK_PERAO_SFLASH_H\t\t\t\t75\n+#define CLK_PERAO_SFLASH_P\t\t\t\t76\n+#define CLK_PERAO_AUDIO0\t\t\t\t77\n+#define CLK_PERAO_AUDIO1\t\t\t\t78\n+#define CLK_PERAO_AUDIO2\t\t\t\t79\n+#define CLK_PERAO_AUXADC_26M\t\t\t\t80\n+\n+/* UFSCFG_AO_REG */\n+#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM\t\t\t0\n+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0\t\t1\n+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1\t\t2\n+#define CLK_UFSCFG_AO_REG_UNIPRO_SYS\t\t\t3\n+#define CLK_UFSCFG_AO_REG_U_SAP_CFG\t\t\t4\n+#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS\t\t5\n+\n+/* UFSCFG_PDN_REG */\n+#define CLK_UFSCFG_REG_UFSHCI_UFS\t\t\t0\n+#define CLK_UFSCFG_REG_UFSHCI_AES\t\t\t1\n+#define CLK_UFSCFG_REG_UFSHCI_U_AHB\t\t\t2\n+#define CLK_UFSCFG_REG_UFSHCI_U_AXI\t\t\t3\n+\n+/* IMP_IIC_WRAP_WS */\n+#define CLK_IMPWS_I2C2\t\t\t\t\t0\n+\n+/* IMP_IIC_WRAP_E */\n+#define CLK_IMPE_I2C0\t\t\t\t\t0\n+#define CLK_IMPE_I2C1\t\t\t\t\t1\n+\n+/* IMP_IIC_WRAP_S */\n+#define CLK_IMPS_I2C3\t\t\t\t\t0\n+#define CLK_IMPS_I2C4\t\t\t\t\t1\n+#define CLK_IMPS_I2C5\t\t\t\t\t2\n+#define CLK_IMPS_I2C6\t\t\t\t\t3\n+\n+/* IMP_IIC_WRAP_EN */\n+#define CLK_IMPEN_I2C7\t\t\t\t\t0\n+#define CLK_IMPEN_I2C8\t\t\t\t\t1\n+\n+/* MFG */\n+#define CLK_MFG_BG3D\t\t\t\t\t0\n+\n+/* DISPSYS_CONFIG */\n+#define CLK_MM_DISP_OVL0_4L\t\t\t\t0\n+#define CLK_MM_DISP_OVL1_4L\t\t\t\t1\n+#define CLK_MM_VPP_RSZ0\t\t\t\t\t2\n+#define CLK_MM_VPP_RSZ1\t\t\t\t\t3\n+#define CLK_MM_DISP_RDMA0\t\t\t\t4\n+#define CLK_MM_DISP_RDMA1\t\t\t\t5\n+#define CLK_MM_DISP_COLOR0\t\t\t\t6\n+#define CLK_MM_DISP_COLOR1\t\t\t\t7\n+#define CLK_MM_DISP_CCORR0\t\t\t\t8\n+#define CLK_MM_DISP_CCORR1\t\t\t\t9\n+#define CLK_MM_DISP_CCORR2\t\t\t\t10\n+#define CLK_MM_DISP_CCORR3\t\t\t\t11\n+#define CLK_MM_DISP_AAL0\t\t\t\t12\n+#define CLK_MM_DISP_AAL1\t\t\t\t13\n+#define CLK_MM_DISP_GAMMA0\t\t\t\t14\n+#define CLK_MM_DISP_GAMMA1\t\t\t\t15\n+#define CLK_MM_DISP_DITHER0\t\t\t\t16\n+#define CLK_MM_DISP_DITHER1\t\t\t\t17\n+#define CLK_MM_DISP_DSC_WRAP0\t\t\t\t18\n+#define CLK_MM_VPP_MERGE0\t\t\t\t19\n+#define CLK_MMSYS_0_DISP_DVO\t\t\t\t20\n+#define CLK_MMSYS_0_DISP_DSI0\t\t\t\t21\n+#define CLK_MM_DP_INTF0\t\t\t\t\t22\n+#define CLK_MM_DPI0\t\t\t\t\t23\n+#define CLK_MM_DISP_WDMA0\t\t\t\t24\n+#define CLK_MM_DISP_WDMA1\t\t\t\t25\n+#define CLK_MM_DISP_FAKE_ENG0\t\t\t\t26\n+#define CLK_MM_DISP_FAKE_ENG1\t\t\t\t27\n+#define CLK_MM_SMI_LARB\t\t\t\t\t28\n+#define CLK_MM_DISP_MUTEX0\t\t\t\t29\n+#define CLK_MM_DIPSYS_CONFIG\t\t\t\t30\n+#define CLK_MM_DUMMY\t\t\t\t\t31\n+#define CLK_MMSYS_1_DISP_DSI0\t\t\t\t32\n+#define CLK_MMSYS_1_LVDS_ENCODER\t\t\t33\n+#define CLK_MMSYS_1_DPI0\t\t\t\t34\n+#define CLK_MMSYS_1_DISP_DVO\t\t\t\t35\n+#define CLK_MM_DP_INTF\t\t\t\t\t36\n+#define CLK_MMSYS_1_LVDS_ENCODER_CTS\t\t\t37\n+#define CLK_MMSYS_1_DISP_DVO_AVT\t\t\t38\n+\n+/* IMGSYS1 */\n+#define CLK_IMGSYS1_LARB9\t\t\t\t0\n+#define CLK_IMGSYS1_LARB11\t\t\t\t1\n+#define CLK_IMGSYS1_DIP\t\t\t\t\t2\n+#define CLK_IMGSYS1_GALS\t\t\t\t3\n+\n+/* IMGSYS2 */\n+#define CLK_IMGSYS2_LARB9\t\t\t\t0\n+#define CLK_IMGSYS2_LARB11\t\t\t\t1\n+#define CLK_IMGSYS2_MFB\t\t\t\t\t2\n+#define CLK_IMGSYS2_WPE\t\t\t\t\t3\n+#define CLK_IMGSYS2_MSS\t\t\t\t\t4\n+#define CLK_IMGSYS2_GALS\t\t\t\t5\n+\n+/* VDEC_CORE */\n+#define CLK_VDEC_CORE_LARB_CKEN\t\t\t\t0\n+#define CLK_VDEC_CORE_VDEC_CKEN\t\t\t\t1\n+#define CLK_VDEC_CORE_VDEC_ACTIVE\t\t\t2\n+\n+/* VENC_GCON */\n+#define CLK_VEN1_CKE0_LARB\t\t\t\t0\n+#define CLK_VEN1_CKE1_VENC\t\t\t\t1\n+#define CLK_VEN1_CKE2_JPGENC\t\t\t\t2\n+#define CLK_VEN1_CKE3_JPGDEC\t\t\t\t3\n+#define CLK_VEN1_CKE4_JPGDEC_C1\t\t\t\t4\n+#define CLK_VEN1_CKE5_GALS\t\t\t\t5\n+#define CLK_VEN1_CKE6_GALS_SRAM\t\t\t\t6\n+\n+/* VLPCFG_REG */\n+#define CLK_VLPCFG_REG_SCP\t\t\t\t0\n+#define CLK_VLPCFG_REG_RG_R_APXGPT_26M\t\t\t1\n+#define CLK_VLPCFG_REG_DPMSRCK_TEST\t\t\t2\n+#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST\t\t\t3\n+#define CLK_VLPCFG_REG_DPMSRULP_TEST\t\t\t4\n+#define CLK_VLPCFG_REG_SPMI_P_MST\t\t\t5\n+#define CLK_VLPCFG_REG_SPMI_P_MST_32K\t\t\t6\n+#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS\t\t\t7\n+#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR\t\t\t8\n+#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS\t\t\t9\n+#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR\t\t\t10\n+#define CLK_VLPCFG_REG_DVFSRC\t\t\t\t11\n+#define CLK_VLPCFG_REG_PWM_VLP\t\t\t\t12\n+#define CLK_VLPCFG_REG_SRCK\t\t\t\t13\n+#define CLK_VLPCFG_REG_SSPM_F26M\t\t\t14\n+#define CLK_VLPCFG_REG_SSPM_F32K\t\t\t15\n+#define CLK_VLPCFG_REG_SSPM_ULPOSC\t\t\t16\n+#define CLK_VLPCFG_REG_VLP_32K_COM\t\t\t17\n+#define CLK_VLPCFG_REG_VLP_26M_COM\t\t\t18\n+\n+/* VLP_CKSYS */\n+#define CLK_VLP_CK_SCP_SEL\t\t\t\t0\n+#define CLK_VLP_CK_PWRAP_ULPOSC_SEL\t\t\t1\n+#define CLK_VLP_CK_SPMI_P_MST_SEL\t\t\t2\n+#define CLK_VLP_CK_DVFSRC_SEL\t\t\t\t3\n+#define CLK_VLP_CK_PWM_VLP_SEL\t\t\t\t4\n+#define CLK_VLP_CK_AXI_VLP_SEL\t\t\t\t5\n+#define CLK_VLP_CK_SYSTIMER_26M_SEL\t\t\t6\n+#define CLK_VLP_CK_SSPM_SEL\t\t\t\t7\n+#define CLK_VLP_CK_SSPM_F26M_SEL\t\t\t8\n+#define CLK_VLP_CK_SRCK_SEL\t\t\t\t9\n+#define CLK_VLP_CK_SCP_SPI_SEL\t\t\t\t10\n+#define CLK_VLP_CK_SCP_IIC_SEL\t\t\t\t11\n+#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL\t\t\t12\n+#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL\t\t\t13\n+#define CLK_VLP_CK_SSPM_ULPOSC_SEL\t\t\t14\n+#define CLK_VLP_CK_APXGPT_26M_SEL\t\t\t15\n+#define CLK_VLP_CK_VADSP_SEL\t\t\t\t16\n+#define CLK_VLP_CK_VADSP_VOWPLL_SEL\t\t\t17\n+#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL\t\t18\n+#define CLK_VLP_CK_CAMTG0_SEL\t\t\t\t19\n+#define CLK_VLP_CK_CAMTG1_SEL\t\t\t\t20\n+#define CLK_VLP_CK_CAMTG2_SEL\t\t\t\t21\n+#define CLK_VLP_CK_AUD_ADC_SEL\t\t\t\t22\n+#define CLK_VLP_CK_KP_IRQ_GEN_SEL\t\t\t23\n+#define CLK_VLP_CK_VADSYS_VLP_26M_EN\t\t\t24\n+#define CLK_VLP_CK_SEJ_13M_EN\t\t\t\t25\n+#define CLK_VLP_CK_SEJ_26M_EN\t\t\t\t26\n+#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN\t\t27\n+\n+/* SCP_IIC */\n+#define CLK_SCP_IIC_I2C0_W1S\t\t\t\t0\n+#define CLK_SCP_IIC_I2C1_W1S\t\t\t\t1\n+\n+/* SCP */\n+#define CLK_SCP_SET_SPI0\t\t\t\t0\n+#define CLK_SCP_SET_SPI1\t\t\t\t1\n+\n+/* CAMSYS_MAIN */\n+#define CLK_CAM_M_LARB13\t\t\t\t0\n+#define CLK_CAM_M_LARB14\t\t\t\t1\n+#define CLK_CAM_M_CAMSYS_MAIN_CAM\t\t\t2\n+#define CLK_CAM_M_CAMSYS_MAIN_CAMTG\t\t\t3\n+#define CLK_CAM_M_SENINF\t\t\t\t4\n+#define CLK_CAM_M_CAMSV1\t\t\t\t5\n+#define CLK_CAM_M_CAMSV2\t\t\t\t6\n+#define CLK_CAM_M_CAMSV3\t\t\t\t7\n+#define CLK_CAM_M_FAKE_ENG\t\t\t\t8\n+#define CLK_CAM_M_CAM2MM_GALS\t\t\t\t9\n+#define CLK_CAM_M_CAMSV4\t\t\t\t10\n+#define CLK_CAM_M_PDA\t\t\t\t\t11\n+\n+/* CAMSYS_RAWA */\n+#define CLK_CAM_RA_CAMSYS_RAWA_LARBX\t\t\t0\n+#define CLK_CAM_RA_CAMSYS_RAWA_CAM\t\t\t1\n+#define CLK_CAM_RA_CAMSYS_RAWA_CAMTG\t\t\t2\n+\n+/* CAMSYS_RAWB */\n+#define CLK_CAM_RB_CAMSYS_RAWB_LARBX\t\t\t0\n+#define CLK_CAM_RB_CAMSYS_RAWB_CAM\t\t\t1\n+#define CLK_CAM_RB_CAMSYS_RAWB_CAMTG\t\t\t2\n+\n+/* IPESYS */\n+#define CLK_IPE_LARB19\t\t\t\t\t0\n+#define CLK_IPE_LARB20\t\t\t\t\t1\n+#define CLK_IPE_SMI_SUBCOM\t\t\t\t2\n+#define CLK_IPE_FD\t\t\t\t\t3\n+#define CLK_IPE_FE\t\t\t\t\t4\n+#define CLK_IPE_RSC\t\t\t\t\t5\n+#define CLK_IPESYS_GALS\t\t\t\t\t6\n+\n+/* VLPCFG_AO_REG */\n+#define CLK_VLPCFG_AO_APEINT_RX\t\t\t\t0\n+\n+/* DVFSRC_TOP */\n+#define CLK_DVFSRC_TOP_DVFSRC_EN\t\t\t0\n+\n+/* MMINFRA_CONFIG */\n+#define CLK_MMINFRA_GCE_D\t\t\t\t0\n+#define CLK_MMINFRA_GCE_M\t\t\t\t1\n+#define CLK_MMINFRA_SMI\t\t\t\t\t2\n+#define CLK_MMINFRA_GCE_26M\t\t\t\t3\n+\n+/* GCE_D */\n+#define CLK_GCE_D_TOP\t\t\t\t\t0\n+\n+/* GCE_M */\n+#define CLK_GCE_M_TOP\t\t\t\t\t0\n+\n+/* MDPSYS_CONFIG */\n+#define CLK_MDP_MUTEX0\t\t\t\t\t0\n+#define CLK_MDP_APB_BUS\t\t\t\t\t1\n+#define CLK_MDP_SMI0\t\t\t\t\t2\n+#define CLK_MDP_RDMA0\t\t\t\t\t3\n+#define CLK_MDP_RDMA2\t\t\t\t\t4\n+#define CLK_MDP_HDR0\t\t\t\t\t5\n+#define CLK_MDP_AAL0\t\t\t\t\t6\n+#define CLK_MDP_RSZ0\t\t\t\t\t7\n+#define CLK_MDP_TDSHP0\t\t\t\t\t8\n+#define CLK_MDP_COLOR0\t\t\t\t\t9\n+#define CLK_MDP_WROT0\t\t\t\t\t10\n+#define CLK_MDP_FAKE_ENG0\t\t\t\t11\n+#define CLK_MDPSYS_CONFIG\t\t\t\t12\n+#define CLK_MDP_RDMA1\t\t\t\t\t13\n+#define CLK_MDP_RDMA3\t\t\t\t\t14\n+#define CLK_MDP_HDR1\t\t\t\t\t15\n+#define CLK_MDP_AAL1\t\t\t\t\t16\n+#define CLK_MDP_RSZ1\t\t\t\t\t17\n+#define CLK_MDP_TDSHP1\t\t\t\t\t18\n+#define CLK_MDP_COLOR1\t\t\t\t\t19\n+#define CLK_MDP_WROT1\t\t\t\t\t20\n+#define CLK_MDP_RSZ2\t\t\t\t\t21\n+#define CLK_MDP_WROT2\t\t\t\t\t22\n+#define CLK_MDP_RSZ3\t\t\t\t\t23\n+#define CLK_MDP_WROT3\t\t\t\t\t24\n+#define CLK_MDP_BIRSZ0\t\t\t\t\t25\n+#define CLK_MDP_BIRSZ1\t\t\t\t\t26\n+\n+/* DBGAO */\n+#define CLK_DBGAO_ATB_EN\t\t\t\t0\n+\n+/* DEM */\n+#define CLK_DEM_ATB_EN\t\t\t\t\t0\n+#define CLK_DEM_BUSCLK_EN\t\t\t\t1\n+#define CLK_DEM_SYSCLK_EN\t\t\t\t2\n+\n+#endif /* _DT_BINDINGS_CLK_MT8189_H */\n",
    "prefixes": [
        "v2",
        "6/7"
    ]
}