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GET /api/1.0/patches/2197351/?format=api
{ "id": 2197351, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197351/?format=api", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.0/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260217173457.18628-6-akhilrajeev@nvidia.com>", "date": "2026-02-17T17:34:54", "name": "[5/8] dmaengine: tegra: Support address width > 40 bits", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "11f6650ade686475c72b5a6a0b076a1d2d6fe2a9", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/1.0/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217173457.18628-6-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 492464, "url": "http://patchwork.ozlabs.org/api/1.0/series/492464/?format=api", "date": "2026-02-17T17:34:49", "name": "Add GPCDMA support in Tegra264", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492464/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197351/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-12016-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=a2qr8Wbr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "<dmaengine@vger.kernel.org>, <linux-tegra@vger.kernel.org>", "CC": "<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<vkoul@kernel.org>, <Frank.Li@kernel.org>, <robh@kernel.org>,\n\t<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <thierry.reding@gmail.com>,\n\t<jonathanh@nvidia.com>, <p.zabel@pengutronix.de>, Akhil R\n\t<akhilrajeev@nvidia.com>", "Subject": "[PATCH 5/8] dmaengine: tegra: Support address width > 40 bits", "Date": "Tue, 17 Feb 2026 23:04:54 +0530", "Message-ID": "<20260217173457.18628-6-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260217173457.18628-1-akhilrajeev@nvidia.com>", "References": "<20260217173457.18628-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FB:EE_|LV2PR12MB5845:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c0008f1f-2f72-480c-88ef-08de6e4b1fa1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014;", "X-Microsoft-Antispam-Message-Info": "\n douy/2z2iT2xqmcgfeLfhixEActiNihk++jaA09pU70T6Yo+3iS2QQfehJPb1l2bxZXI1myK65WJHoMnFIsxEjdsyLTdjB3Xc1+DTN+oZ0+6dCQ++VHAiIyc1Fh5pJFy2gC33oWf/cbV2ZQfPf9NBPFVzNWtMFOaHh0shbJhlncbDwjcqe19NlRpxEbcAj60r+QHGWjo4KmG0bqfnyavwHQ74ICeyuZtYdwGqGEbd3HVVw+TPLJc+BJ47mK3KUzjIloqUts5rOscxz2etZsmEo7nwaKz39vsYG6MfD8cc2Ywecso/tUv8nNr6D3eRD2OgTs7H8S43Vlo7g2Ak068tj/5QsSi3dRIuUVROHXtMmj7f7IPbdttevhLG+J/atSXMof3BzsKZnFxInogrjEtHjbpCYWD6fNLc2UmVVW545g16QIIf8GVARO4R3UkHch++iYwqNxkFtvFy0mV/u2tDkSAan5/oK+IysxnLwnLElx6wEOv98wAt9f/beUdWVgdD1dhBWcFxmbXn9CvpfYsN8fg3W8Aw6og5XGv12X3NIeVTRoklJIMU/vil8IlEuNSKXQDeO5JkSwLpxGPwkZ4xUY4+mafQM0YEWUjVZHY5YkhxE0LjNh7NFUw94+ujvlufqgdVx7bfMyaS0Cbl5kaoMLGguwg3VYFOTBDXGQ9ObZT2o7AqdK9j8EveCXt5GIbXosYvvKzbPc9DqwEZEXqMBWi8z2AwloDcJkGo254+sifeDYidcn3iR8R0f8FIDVHqpr4XnBTxqWrz9C/Lj61hW/8bqlejAI8K9Ic0N6pnQRJVsZjrkj2QKkHxox522BxsK2CaqkRchxcMwHLJkLBD225fONflQ5QBHnnWMQVGaXOTQWNRP7/KOhHPhQMaXJidDcX4ZwPRJyXdzD7KFaDJcRMAGGIxCRocuIETBWjGXnWFBoFXlUBgdlr+vFJQDTdeN4zLxHkl2KXcbiDSzIfh+j9L9TQWYLnuSzaWHc/Sf9XjmB8UOg6u4OxVg/KzDMmakGrF+Wer/qf5MTJhMCPKGqrsJ8aGKfAT/NSWh93Zw+7KMjHp8X15xfwXaquMh8rBXkklS3sh2Ip5XurhlHnxJe/4GXJylGPLfJID1nZgtBNkuYbKFLh1xNuFiP6mbGXfuJIgLlzGzp+Cd2MJacKNWvTQwlm2hjaJPyY9NnoHI8YXVgTS2XziJBM/fBllfePOobBZ8223TxmEeLz52SanrgB5M0uZGV0XeeOd2CiRap8nSVsf1rtneCpvKjLEn8ULwzJeQRogzjB31zqjfBhsfy5U7wDvWQOTWZwdIosk/wGlTfR/oROwIod8opIXjC6VuQEWgSDWU5y+hOx+aro0O9aDmjvYt1LIcRHTIphxpcpBh8IJ9TYiiC0yZAMcLbEte8jj8gcMvDCDdIGD2xPauwzG2gGtgJccqFX8vpM93TWuFZJReMi6zcwtQsm554rZtqWdfgsB1IURSmo/Ruu3VS9FJZtAxTG3L/QL104IEBn1Mjrc03oU5gl+YHT724tuMKtQB7DALofc2tDB/pN1JyYXuAjGtOweqqglToyc9QI7X2rIvprIwzXSgRtm1JDnPd4mdZ5a/GmG6ynQGRvft3GwW0vVYPjiglIZZe7kdxhc0smnICDAp/76GJ3JgOvgjQAqXjb7XCdLhNKorgdCA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t0dVxRW7lbQh2WYNl8JwVWV8snVkXze8o4OVLxYk6OXZDU4YZGJ7Q/WvAeApeOZP5UPD3iebUlNs6E6bwCG6T4ALnsnCZEGuhfUk5R5oGalKVdcnDmY93sNsRZLZrL/Oqu7zRqRe+RI12yxg+rsD3+eH1iUZ2+n5CqcQJ0Vvi8ifPPdSTjLRstbvQ6hkMMJbKcNb+rRppVdsqjY8twQjfFxMxeKAbtWq8kdBm7QKtfsKY9kvaESTkLtrkEoMN+iU4SyhDbWiZucX3RXCEbiB7Qc7LCpUMAnNUuBzdlOgu2ahVhH9ZkXRU02OVVI2HfB0/28/c8ZukEUBixtsuZNB2eGju0FkXYOWeljY8gieoq36QVufBb8ZNI7u0o8o889EvZkggdgKl36GQwT344yiNzQaiworl6RsXb6DKDNiDp6sP1/ztb9jADZbYFYQwVe1n", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Feb 2026 17:36:46.3644\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c0008f1f-2f72-480c-88ef-08de6e4b1fa1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF0001A0FB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5845" }, "content": "Tegra264 supports address width of 41 bits and has a separate register\nto accommodate the high address. Add a device data property to specify\nthe number of address bits supported on a device and use that to\nprogram the required registers.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 129 +++++++++++++++++++++------------\n 1 file changed, 82 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 72701b543ceb..ce3b1dd52bb3 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -151,6 +151,7 @@ struct tegra_dma_channel;\n */\n struct tegra_dma_chip_data {\n \tbool hw_support_pause;\n+\tunsigned int addr_bits;\n \tunsigned int nr_channels;\n \tunsigned int channel_reg_size;\n \tunsigned int max_dma_count;\n@@ -166,6 +167,8 @@ struct tegra_dma_channel_regs {\n \tu32 src;\n \tu32 dst;\n \tu32 high_addr;\n+\tu32 src_high;\n+\tu32 dst_high;\n \tu32 mc_seq;\n \tu32 mmio_seq;\n \tu32 wcount;\n@@ -189,7 +192,8 @@ struct tegra_dma_sg_req {\n \tu32 csr;\n \tu32 src;\n \tu32 dst;\n-\tu32 high_addr;\n+\tu32 src_high;\n+\tu32 dst_high;\n \tu32 mc_seq;\n \tu32 mmio_seq;\n \tu32 wcount;\n@@ -273,6 +277,41 @@ static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)\n \treturn tdc->vc.chan.device->dev;\n }\n \n+static void tegra_dma_program_addr(struct tegra_dma_channel *tdc,\n+\t\t\t\t struct tegra_dma_sg_req *sg_req)\n+{\n+\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n+\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n+\n+\tif (tdc->tdma->chip_data->addr_bits > 40) {\n+\t\ttdc_write(tdc, tdc->regs->src_high,\n+\t\t\t sg_req->src_high);\n+\t\ttdc_write(tdc, tdc->regs->dst_high,\n+\t\t\t sg_req->dst_high);\n+\t} else {\n+\t\ttdc_write(tdc, tdc->regs->high_addr,\n+\t\t\t sg_req->src_high | sg_req->dst_high);\n+\t}\n+}\n+\n+static void tegra_dma_configure_addr(struct tegra_dma_channel *tdc,\n+\t\t\t\t struct tegra_dma_sg_req *sg_req,\n+\t\t\t\tphys_addr_t src, phys_addr_t dst)\n+{\n+\tsg_req->src = lower_32_bits(src);\n+\tsg_req->dst = lower_32_bits(dst);\n+\n+\tif (tdc->tdma->chip_data->addr_bits > 40) {\n+\t\tsg_req->src_high = upper_32_bits(src);\n+\t\tsg_req->dst_high = upper_32_bits(dst);\n+\t} else {\n+\t\tsg_req->src_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR,\n+\t\t\t\t\t upper_32_bits(src));\n+\t\tsg_req->dst_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR,\n+\t\t\t\t\t upper_32_bits(dst));\n+\t}\n+}\n+\n static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)\n {\n \tdev_dbg(tdc2dev(tdc), \"DMA Channel %d name %s register dump:\\n\",\n@@ -282,11 +321,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)\n \t\ttdc_read(tdc, tdc->regs->status),\n \t\ttdc_read(tdc, tdc->regs->csre)\n \t);\n-\tdev_dbg(tdc2dev(tdc), \"SRC %x DST %x HI ADDR %x\\n\",\n-\t\ttdc_read(tdc, tdc->regs->src),\n-\t\ttdc_read(tdc, tdc->regs->dst),\n-\t\ttdc_read(tdc, tdc->regs->high_addr)\n-\t);\n+\n+\tif (tdc->tdma->chip_data->addr_bits > 40) {\n+\t\tdev_dbg(tdc2dev(tdc), \"SRC %x SRC HI %x DST %x DST HI %x\\n\",\n+\t\t\ttdc_read(tdc, tdc->regs->src),\n+\t\t\ttdc_read(tdc, tdc->regs->src_high),\n+\t\t\ttdc_read(tdc, tdc->regs->dst),\n+\t\t\ttdc_read(tdc, tdc->regs->dst_high)\n+\t\t);\n+\t} else {\n+\t\tdev_dbg(tdc2dev(tdc), \"SRC %x DST %x HI ADDR %x\\n\",\n+\t\t\ttdc_read(tdc, tdc->regs->src),\n+\t\t\ttdc_read(tdc, tdc->regs->dst),\n+\t\t\ttdc_read(tdc, tdc->regs->high_addr)\n+\t\t);\n+\t}\n+\n \tdev_dbg(tdc2dev(tdc), \"MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\\n\",\n \t\ttdc_read(tdc, tdc->regs->mc_seq),\n \t\ttdc_read(tdc, tdc->regs->mmio_seq),\n@@ -490,9 +540,7 @@ static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)\n \tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n \ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n-\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n-\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n-\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n+\ttegra_dma_program_addr(tdc, sg_req);\n \n \t/* Start DMA */\n \ttdc_write(tdc, tdc->regs->csr,\n@@ -520,11 +568,9 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc)\n \n \tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n+\ttegra_dma_program_addr(tdc, sg_req);\n \ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n \ttdc_write(tdc, tdc->regs->csr, 0);\n-\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n-\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n-\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n \ttdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern);\n \ttdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq);\n \ttdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq);\n@@ -829,7 +875,7 @@ static unsigned int get_burst_size(struct tegra_dma_channel *tdc,\n \n static int get_transfer_param(struct tegra_dma_channel *tdc,\n \t\t\t enum dma_transfer_direction direction,\n-\t\t\t u32 *apb_addr,\n+\t\t\t dma_addr_t *apb_addr,\n \t\t\t u32 *mmio_seq,\n \t\t\t u32 *csr,\n \t\t\t unsigned int *burst_size,\n@@ -908,10 +954,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,\n \tdma_desc->sg_count = 1;\n \tsg_req = dma_desc->sg_req;\n \n-\tsg_req[0].src = 0;\n-\tsg_req[0].dst = dest;\n-\tsg_req[0].high_addr =\n-\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n+\ttegra_dma_configure_addr(tdc, &sg_req[0], 0, dest);\n \tsg_req[0].fixed_pattern = value;\n \t/* Word count reg takes value as (N +1) words */\n \tsg_req[0].wcount = ((len - 4) >> 2);\n@@ -977,12 +1020,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,\n \tdma_desc->sg_count = 1;\n \tsg_req = dma_desc->sg_req;\n \n-\tsg_req[0].src = src;\n-\tsg_req[0].dst = dest;\n-\tsg_req[0].high_addr =\n-\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));\n-\tsg_req[0].high_addr |=\n-\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n+\ttegra_dma_configure_addr(tdc, &sg_req[0], src, dest);\n \t/* Word count reg takes value as (N +1) words */\n \tsg_req[0].wcount = ((len - 4) >> 2);\n \tsg_req[0].csr = csr;\n@@ -1002,7 +1040,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \tstruct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);\n \tunsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;\n \tenum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;\n-\tu32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0;\n+\tu32 csr, mc_seq, mmio_seq = 0;\n+\tdma_addr_t apb_ptr = 0;\n \tstruct tegra_dma_sg_req *sg_req;\n \tstruct tegra_dma_desc *dma_desc;\n \tstruct scatterlist *sg;\n@@ -1087,17 +1126,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \t\tmmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);\n \t\tdma_desc->bytes_req += len;\n \n-\t\tif (direction == DMA_MEM_TO_DEV) {\n-\t\t\tsg_req[i].src = mem;\n-\t\t\tsg_req[i].dst = apb_ptr;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n-\t\t} else if (direction == DMA_DEV_TO_MEM) {\n-\t\t\tsg_req[i].src = apb_ptr;\n-\t\t\tsg_req[i].dst = mem;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n-\t\t}\n+\t\tif (direction == DMA_MEM_TO_DEV)\n+\t\t\ttegra_dma_configure_addr(tdc, &sg_req[i], mem, apb_ptr);\n+\t\telse if (direction == DMA_DEV_TO_MEM)\n+\t\t\ttegra_dma_configure_addr(tdc, &sg_req[i], apb_ptr, mem);\n \n \t\t/*\n \t\t * Word count register takes input in words. Writing a value\n@@ -1120,7 +1152,8 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \t\t\t unsigned long flags)\n {\n \tenum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;\n-\tu32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size;\n+\tu32 csr, mc_seq, mmio_seq = 0, burst_size;\n+\tdma_addr_t apb_ptr = 0;\n \tunsigned int max_dma_count, len, period_count, i;\n \tstruct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);\n \tstruct tegra_dma_desc *dma_desc;\n@@ -1209,17 +1242,10 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \t/* Split transfer equal to period size */\n \tfor (i = 0; i < period_count; i++) {\n \t\tmmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);\n-\t\tif (direction == DMA_MEM_TO_DEV) {\n-\t\t\tsg_req[i].src = mem;\n-\t\t\tsg_req[i].dst = apb_ptr;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n-\t\t} else if (direction == DMA_DEV_TO_MEM) {\n-\t\t\tsg_req[i].src = apb_ptr;\n-\t\t\tsg_req[i].dst = mem;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n-\t\t}\n+\t\tif (direction == DMA_MEM_TO_DEV)\n+\t\t\ttegra_dma_configure_addr(tdc, &sg_req[i], mem, apb_ptr);\n+\t\telse if (direction == DMA_DEV_TO_MEM)\n+\t\t\ttegra_dma_configure_addr(tdc, &sg_req[i], apb_ptr, mem);\n \t\t/*\n \t\t * Word count register takes input in words. Writing a value\n \t\t * of N into word count register means a req of (N+1) words.\n@@ -1317,6 +1343,7 @@ static const struct tegra_dma_channel_regs tegra186_reg_offsets = {\n \n static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 40,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = false,\n@@ -1326,6 +1353,7 @@ static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \n static const struct tegra_dma_chip_data tegra194_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 40,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n@@ -1335,6 +1363,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {\n \n static const struct tegra_dma_chip_data tegra234_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 41,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n@@ -1446,6 +1475,12 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\ttdc->stream_id = stream_id;\n \t}\n \n+\tret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to set DMA mask: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n \tdma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);\n \tdma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);\n \tdma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);\n", "prefixes": [ "5/8" ] }