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GET /api/1.0/patches/2197194/?format=api
{ "id": 2197194, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197194/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260217-d3cold-v2-5-89b322864043@oss.qualcomm.com>", "date": "2026-02-17T11:19:10", "name": "[v2,5/5] PCI: qcom: Add D3cold support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b3500e61423a12b967fb072726b88fcd3a0f2ff7", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.0/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-d3cold-v2-5-89b322864043@oss.qualcomm.com/mbox/", "series": [ { "id": 492410, "url": "http://patchwork.ozlabs.org/api/1.0/series/492410/?format=api", "date": "2026-02-17T11:19:05", "name": "PCI: qcom: Add D3cold support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492410/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197194/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-47452-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UsNyqI0P;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=boqNUyMY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260217-d3cold-v2-5-89b322864043@oss.qualcomm.com>", "References": "<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>", "In-Reply-To": "<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Will Deacon <will@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1771327148; l=6515;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=IAVEMPt0tOVYVQCFgBm15tr3uSMRBtLlDbxbCnOFZrQ=;\n b=wjF9Ok40l0LOgqKQkkPhl/h8dRDieyHrE+JHl4vXu3qG6H5Qh11tQtZ8Q5SfvNRzzzehxTmMs\n jJvG1KZaYAcBoHrk9mJo/xorBCcy23VvTGS4SE/tE4tf96AU3a1QeZ7", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Authority-Analysis": "v=2.4 cv=XKo9iAhE c=1 sm=1 tr=0 ts=69944ec8 cx=c_pps\n a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=EUspDBNiAAAA:8 a=RN3yzfvplrNe8VIVIhoA:9 a=QEXdDO2ut3YA:10\n a=zc0IvFSfCIW2DFIPzwfm:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfXwwiSs2qpridl\n WttgRar6I19x7NdDuZ/MlWeiUuNvhK0iCF+Ex/720piyj6NkNDbvPhds5y0PZH7d5VsWC15xQWb\n gAIvXgekBaTE2L9DC89wkdDU2fKugkbqPVoMFz9sBJTyi/VzgvOIUV+vd/SMjq6gRcsBvWMAOun\n T8I6NFhrFxjvDv5WRqLmUInCRhIsAmA15LSS8EQro2zqJiAXuqdICODpQ4Cj1rfWXgW+j8rj3CG\n WlRy25dm8LVH8Jse9pJVBulqfnWI/I3baHewpquMqK6SyKOxpX1yydVaKmGbSS28afjuioTcVUa\n EBpFk0tpE5haFZejuFpSvkaMLQ1YayfllZU4bc+31Kb+OUUEBj26YIdk3N0ui5v4ST54LbkGuA9\n IqRtRzE5oJY6Nf1hsIke0k8Y7XcINv+AS1P7tOLCfX2qExAzA5PSCM3oUh0Jpvc0HiF68bBcD24\n Yubef5XWZXWdgAva/bA==", "X-Proofpoint-ORIG-GUID": "r-xi2sJCbWKINQRJPL-L1Qy7a1HUgI-9", "X-Proofpoint-GUID": "r-xi2sJCbWKINQRJPL-L1Qy7a1HUgI-9", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0\n clxscore=1015 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094" }, "content": "Add support for transitioning Qcom PCIe controllers into D3cold by\nintegrating with the DWC core suspend/resume helpers.\n\nImplement PME_TurnOff message generation via ELBI_SYS_CTRL and hook it\ninto the DWC host operations so the controller follows the standard\nPME_TurnOff-based power-down sequence before entering D3cold.\n\nWhen the link is suspended into D3cold, fully tear down interconnect\nbandwidth, OPP votes. If D3cold is not entered, retain existing behavior\nby keeping the required interconnect and OPP votes.\n\nDrop the qcom_pcie::suspended flag and rely on the existing\ndw_pcie::suspended state, which now drives both the power-management\nflow and the interconnect/OPP handling.\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-qcom.c | 121 ++++++++++++++++++++-------------\n 1 file changed, 74 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex b02c19bbdf2ea5db252c2a0281a569bb3a0cc497..37442bbe588c36b0b0414cc4d0016da2d8424a87 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -145,6 +145,7 @@\n \n /* ELBI_SYS_CTRL register fields */\n #define ELBI_SYS_CTRL_LT_ENABLE\t\t\tBIT(0)\n+#define ELBI_SYS_CTRL_PME_TURNOFF_MSG\t\tBIT(4)\n \n /* AXI_MSTR_RESP_COMP_CTRL0 register fields */\n #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K\t0x4\n@@ -283,7 +284,6 @@ struct qcom_pcie {\n \tconst struct qcom_pcie_cfg *cfg;\n \tstruct dentry *debugfs;\n \tstruct list_head ports;\n-\tbool suspended;\n \tbool use_pm_opp;\n };\n \n@@ -1401,10 +1401,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)\n \t\tpcie->cfg->ops->host_post_init(pcie);\n }\n \n+static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp)\n+{\n+\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n+\n+\twritel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL);\n+}\n+\n static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {\n \t.init\t\t= qcom_pcie_host_init,\n \t.deinit\t\t= qcom_pcie_host_deinit,\n \t.post_init\t= qcom_pcie_host_post_init,\n+\t.pme_turn_off\t= qcom_pcie_host_pme_turn_off,\n };\n \n /* Qcom IP rev.: 2.1.0\tSynopsys IP rev.: 4.01a */\n@@ -2069,53 +2077,51 @@ static int qcom_pcie_suspend_noirq(struct device *dev)\n \tif (!pcie)\n \t\treturn 0;\n \n-\t/*\n-\t * Set minimum bandwidth required to keep data path functional during\n-\t * suspend.\n-\t */\n-\tif (pcie->icc_mem) {\n-\t\tret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));\n-\t\tif (ret) {\n-\t\t\tdev_err(dev,\n-\t\t\t\t\"Failed to set bandwidth for PCIe-MEM interconnect path: %d\\n\",\n-\t\t\t\tret);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n+\tret = dw_pcie_suspend_noirq(pcie->pci);\n+\tif (ret)\n+\t\treturn ret;\n \n-\t/*\n-\t * Turn OFF the resources only for controllers without active PCIe\n-\t * devices. For controllers with active devices, the resources are kept\n-\t * ON and the link is expected to be in L0/L1 (sub)states.\n-\t *\n-\t * Turning OFF the resources for controllers with active PCIe devices\n-\t * will trigger access violation during the end of the suspend cycle,\n-\t * as kernel tries to access the PCIe devices config space for masking\n-\t * MSIs.\n-\t *\n-\t * Also, it is not desirable to put the link into L2/L3 state as that\n-\t * implies VDD supply will be removed and the devices may go into\n-\t * powerdown state. This will affect the lifetime of the storage devices\n-\t * like NVMe.\n-\t */\n-\tif (!dw_pcie_link_up(pcie->pci)) {\n-\t\tqcom_pcie_host_deinit(&pcie->pci->pp);\n-\t\tpcie->suspended = true;\n-\t}\n+\tif (pcie->pci->suspended) {\n+\t\tret = icc_disable(pcie->icc_mem);\n+\t\tif (ret)\n+\t\t\tdev_err(dev, \"Failed to disable PCIe-MEM interconnect path: %d\\n\", ret);\n \n-\t/*\n-\t * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.\n-\t * Because on some platforms, DBI access can happen very late during the\n-\t * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC\n-\t * error.\n-\t */\n-\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n \t\tret = icc_disable(pcie->icc_cpu);\n \t\tif (ret)\n \t\t\tdev_err(dev, \"Failed to disable CPU-PCIe interconnect path: %d\\n\", ret);\n \n \t\tif (pcie->use_pm_opp)\n \t\t\tdev_pm_opp_set_opp(pcie->pci->dev, NULL);\n+\t} else {\n+\t\t/*\n+\t\t * Set minimum bandwidth required to keep data path functional during\n+\t\t * suspend.\n+\t\t */\n+\t\tif (pcie->icc_mem) {\n+\t\t\tret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev,\n+\t\t\t\t\t\"Failed to set bandwidth for PCIe-MEM interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.\n+\t\t * Because on some platforms, DBI access can happen very late during the\n+\t\t * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC\n+\t\t * error.\n+\t\t */\n+\t\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\t\t\tret = icc_disable(pcie->icc_cpu);\n+\t\t\tif (ret)\n+\t\t\t\tdev_err(dev, \"Failed to disable CPU-PCIe interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\n+\t\t\tif (pcie->use_pm_opp)\n+\t\t\t\tdev_pm_opp_set_opp(pcie->pci->dev, NULL);\n+\t\t}\n \t}\n \treturn ret;\n }\n@@ -2129,25 +2135,46 @@ static int qcom_pcie_resume_noirq(struct device *dev)\n \tif (!pcie)\n \t\treturn 0;\n \n-\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\tif (pcie->pci->suspended) {\n \t\tret = icc_enable(pcie->icc_cpu);\n \t\tif (ret) {\n \t\t\tdev_err(dev, \"Failed to enable CPU-PCIe interconnect path: %d\\n\", ret);\n \t\t\treturn ret;\n \t\t}\n-\t}\n \n-\tif (pcie->suspended) {\n-\t\tret = qcom_pcie_host_init(&pcie->pci->pp);\n-\t\tif (ret)\n-\t\t\treturn ret;\n+\t\tret = icc_enable(pcie->icc_mem);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to enable PCIe-MEM interconnect path: %d\\n\", ret);\n+\t\t\tgoto disable_icc_cpu;\n+\t\t}\n \n-\t\tpcie->suspended = false;\n+\t\t/*\n+\t\t * Ignore -ETIMEDOUT here since it is expected when no endpoint is\n+\t\t * connected to the PCIe link.\n+\t\t */\n+\t\tret = dw_pcie_resume_noirq(pcie->pci);\n+\t\tif (ret && (ret != -ETIMEDOUT))\n+\t\t\tgoto disable_icc_mem;\n+\t} else {\n+\t\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\t\t\tret = icc_enable(pcie->icc_cpu);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev, \"Failed to enable CPU-PCIe interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n \t}\n \n \tqcom_pcie_icc_opp_update(pcie);\n \n \treturn 0;\n+disable_icc_mem:\n+\ticc_disable(pcie->icc_mem);\n+disable_icc_cpu:\n+\ticc_disable(pcie->icc_cpu);\n+\n+\treturn ret;\n }\n \n static const struct of_device_id qcom_pcie_match[] = {\n", "prefixes": [ "v2", "5/5" ] }