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GET /api/1.0/patches/2197191/?format=api
{ "id": 2197191, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197191/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260217-d3cold-v2-2-89b322864043@oss.qualcomm.com>", "date": "2026-02-17T11:19:07", "name": "[v2,2/5] PCI: dwc: Use common D3cold eligibility helper in suspend path", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4be27b13c432b244490e502cc7ac94281f715ce9", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.0/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-d3cold-v2-2-89b322864043@oss.qualcomm.com/mbox/", "series": [ { "id": 492410, "url": "http://patchwork.ozlabs.org/api/1.0/series/492410/?format=api", "date": "2026-02-17T11:19:05", "name": "PCI: qcom: Add D3cold support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492410/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197191/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-47449-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=OYHGcIeH;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZmtPOfH0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260217-d3cold-v2-2-89b322864043@oss.qualcomm.com>", "References": "<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>", "In-Reply-To": "<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Will Deacon <will@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1771327148; l=2041;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=TtbJw2QxkiBmLJKp1okcAfp6LW1NcrShntWzlulImc8=;\n b=YWmGKKIDBl3wYoKkpN/uTl2ahJVwSeE+5nhAt6wtBrGX2sN86iG3g8H4fNwHYNFYCQvszbMOM\n qBFuDArb0YoDjIliFHrt0hfLTqnbaWrwXLZ4WkXsz6TBpW+1rxpcmoZ", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; 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However, such\ndevices typically remain in D0 and are already covered by the new helper's\nrequirement that all endpoints be in D3hot before the host bridge may\nenter D3cold.\n\nSo, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with\nthe shared pci_host_common_can_enter_d3cold() helper to decide whether the\nDesignWare host bridge can safely transition to D3cold.\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++------\n 1 file changed, 3 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex 6ae6189e9b8a9021c99ece17504834650debd86b..713aa64553bfc988717cab2936935bb43aabd72c 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -16,9 +16,11 @@\n #include <linux/msi.h>\n #include <linux/of_address.h>\n #include <linux/of_pci.h>\n+#include <linux/pci.h>\n #include <linux/pci_regs.h>\n #include <linux/platform_device.h>\n \n+#include \"../pci-host-common.h\"\n #include \"../../pci.h\"\n #include \"pcie-designware.h\"\n \n@@ -1218,18 +1220,13 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)\n \n int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n {\n-\tu8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tint ret = 0;\n \tu32 val;\n \n \tif (!dw_pcie_link_up(pci))\n \t\tgoto stop_link;\n \n-\t/*\n-\t * If L1SS is supported, then do not put the link into L2 as some\n-\t * devices such as NVMe expect low resume latency.\n-\t */\n-\tif (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)\n+\tif (!pci_host_common_can_enter_d3cold(pci->pp.bridge))\n \t\treturn 0;\n \n \tif (pci->pp.ops->pme_turn_off) {\n", "prefixes": [ "v2", "2/5" ] }