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GET /api/1.0/patches/2196695/?format=api
{ "id": 2196695, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2196695/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260216034432.23912-13-richard.henderson@linaro.org>", "date": "2026-02-16T03:44:31", "name": "[RFC,12/13] target/arm: Add SME state to kvm_arch_{get, put}_registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e6bbfc0a39078f2843ec455ead0aef87dee708b1", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.0/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-13-richard.henderson@linaro.org/mbox/", "series": [ { "id": 492243, "url": "http://patchwork.ozlabs.org/api/1.0/series/492243/?format=api", "date": "2026-02-16T03:44:19", "name": "target/arm: Support SME for KVM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492243/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196695/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QD8H0kCA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpbf2P8Xz1xxp\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 16 Feb 2026 14:46:22 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vrpXs-0002hm-SJ; Sun, 15 Feb 2026 22:45:12 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1vrpXn-0002de-Qt\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:07 -0500", "from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1vrpXl-0002T8-3Z\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:07 -0500", "by mail-pl1-x632.google.com with SMTP id\n d9443c01a7336-2a7a9b8ed69so27641535ad.2\n for <qemu-devel@nongnu.org>; Sun, 15 Feb 2026 19:45:03 -0800 (PST)", "from stoup.. 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This probably belongs in asm-arm64/kvm.h */\n+#define KVM_REG_ARM64_SME_ZT0 \\\n+ (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \\\n+ KVM_REG_ARM64_SME_ZT_BASE | KVM_REG_SIZE_U512)\n+\n const KVMCapabilityInfo kvm_arch_required_capabilities[] = {\n KVM_CAP_INFO(DEVICE_CTRL),\n KVM_CAP_LAST_INFO\n@@ -2157,10 +2162,39 @@ static int kvm_arch_put_sve(CPUState *cs, uint32_t vq, bool have_ffr)\n return 0;\n }\n \n+static int kvm_arch_put_sme(CPUState *cs, uint32_t svq)\n+{\n+ CPUARMState *env = cpu_env(cs);\n+ ARMCPU *cpu = env_archcpu(env);\n+ uint64_t tmp[ARM_MAX_VQ * 2];\n+ uint64_t *r;\n+ int ret;\n+\n+ for (int n = 0; n < svq * 16; ++n) {\n+ r = sve_bswap64(tmp, &env->za_state.za[n].d[0], svq * 2);\n+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n+ if (cpu_isar_feature(aa64_sme2, cpu)) {\n+ r = sve_bswap64(tmp, env->za_state.zt0, ARRAY_SIZE(env->za_state.zt0));\n+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+ return 0;\n+}\n+\n int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n {\n uint64_t val;\n uint32_t fpr;\n+ bool sme_sm = false;\n+ bool sme_za = false;\n+ uint32_t svq = 0;\n int i, ret;\n unsigned int el;\n \n@@ -2239,7 +2273,18 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n }\n }\n \n- if (cpu_isar_feature(aa64_sve, cpu)) {\n+ if (cpu_isar_feature(aa64_sme, cpu)) {\n+ /* Current SVL is required for either SM or ZA */\n+ sme_sm = FIELD_EX64(env->svcr, SVCR, SM);\n+ sme_za = FIELD_EX64(env->svcr, SVCR, ZA);\n+ if (sme_sm || sme_za) {\n+ svq = sve_vqm1_for_el_sm(env, el, true) + 1;\n+ }\n+ }\n+\n+ if (sme_sm) {\n+ ret = kvm_arch_put_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, cpu));\n+ } else if (cpu_isar_feature(aa64_sve, cpu)) {\n ret = kvm_arch_put_sve(cs, cpu->sve_max_vq, true);\n } else {\n ret = kvm_arch_put_fpsimd(cs);\n@@ -2248,6 +2293,13 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n return ret;\n }\n \n+ if (sme_za) {\n+ ret = kvm_arch_put_sme(cs, svq);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n fpr = vfp_get_fpsr(env);\n ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);\n if (ret) {\n@@ -2342,11 +2394,41 @@ static int kvm_arch_get_sve(CPUState *cs, uint32_t vq, bool have_ffr)\n return 0;\n }\n \n+static int kvm_arch_get_sme(CPUState *cs, uint32_t svq)\n+{\n+ CPUARMState *env = cpu_env(cs);\n+ ARMCPU *cpu = env_archcpu(env);\n+ uint64_t *r;\n+ int ret;\n+\n+ for (int n = 0; n < svq * 16; ++n) {\n+ r = &env->za_state.za[n].d[0];\n+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r);\n+ if (ret) {\n+ return ret;\n+ }\n+ sve_bswap64(r, r, svq * 2);\n+ }\n+\n+ if (cpu_isar_feature(aa64_sme2, cpu)) {\n+ r = env->za_state.zt0;\n+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r);\n+ if (ret) {\n+ return ret;\n+ }\n+ sve_bswap64(r, r, ARRAY_SIZE(env->za_state.zt0));\n+ }\n+ return 0;\n+}\n+\n int kvm_arch_get_registers(CPUState *cs, Error **errp)\n {\n uint64_t val;\n unsigned int el;\n uint32_t fpr;\n+ bool sme_sm = false;\n+ bool sme_za = false;\n+ uint32_t svq = 0;\n int i, ret;\n \n ARMCPU *cpu = ARM_CPU(cs);\n@@ -2424,7 +2506,18 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)\n env->spsr = env->banked_spsr[i];\n }\n \n- if (cpu_isar_feature(aa64_sve, cpu)) {\n+ if (cpu_isar_feature(aa64_sme, cpu)) {\n+ /* Current SVL is required for either SM or ZA */\n+ sme_sm = FIELD_EX64(env->svcr, SVCR, SM);\n+ sme_za = FIELD_EX64(env->svcr, SVCR, ZA);\n+ if (sme_sm || sme_za) {\n+ svq = sve_vqm1_for_el_sm(env, el, true) + 1;\n+ }\n+ }\n+\n+ if (sme_sm) {\n+ ret = kvm_arch_get_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, cpu));\n+ } else if (cpu_isar_feature(aa64_sve, cpu)) {\n ret = kvm_arch_get_sve(cs, cpu->sve_max_vq, true);\n } else {\n ret = kvm_arch_get_fpsimd(cs);\n@@ -2433,6 +2526,13 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)\n return ret;\n }\n \n+ if (sme_za) {\n+ ret = kvm_arch_get_sme(cs, svq);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);\n if (ret) {\n return ret;\n", "prefixes": [ "RFC", "12/13" ] }