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GET /api/1.0/patches/2175856/?format=api
{ "id": 2175856, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175856/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251219-aspeed-sgpio-v5-2-fd5593178144@google.com>", "date": "2025-12-19T07:04:15", "name": "[v5,2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4c109d48e69407694ffe1ed2dd797acb262e178c", "submitter": { "id": 91652, "url": "http://patchwork.ozlabs.org/api/1.0/people/91652/?format=api", "name": "Yubin Zou", "email": "yubinz@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-2-fd5593178144@google.com/mbox/", "series": [ { "id": 485958, "url": "http://patchwork.ozlabs.org/api/1.0/series/485958/?format=api", "date": "2025-12-19T07:04:13", "name": "hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485958/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175856/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=PwqX2xjm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 18\n Dec 2025 23:04:41 -0800 (PST)", "Date": "Fri, 19 Dec 2025 07:04:15 +0000", "In-Reply-To": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "Mime-Version": "1.0", "References": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "X-Mailer": "b4 0.14.2", "Message-ID": "<20251219-aspeed-sgpio-v5-2-fd5593178144@google.com>", "Subject": "[PATCH v5 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for\n SGPIO pins", "From": "Yubin Zou <yubinz@google.com>", "To": "qemu-devel@nongnu.org", "Cc": "\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Jamin Lin <jamin_lin@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Kane-Chen-AS <kane_chen@aspeedtech.com>,\n Nabih Estefan <nabihestefan@google.com>, qemu-arm@nongnu.org,\n Yubin Zou <yubinz@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::104a;\n envelope-from=3CflEaQYKCmAWS9GLXEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--yubinz.bounces.google.com;\n helo=mail-pj1-x104a.google.com", "X-Spam_score_int": "-95", "X-Spam_score": "-9.6", "X-Spam_bar": "---------", "X-Spam_report": "(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are\nimplemented to get and set the level of individual SGPIO pins. These\nare then exposed as boolean properties on the SGPIO device object.\n\nSigned-off-by: Yubin Zou <yubinz@google.com>\nReviewed-by: Kane Chen <kane_chen@aspeedtech.com>\n---\n hw/gpio/aspeed_sgpio.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 79 insertions(+)", "diff": "diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c\nindex 167a72c41e96c67bd1867a19e2b1706f5bd074e4..927c711cb3aef889c47c9a9156fe4241981c5efa 100644\n--- a/hw/gpio/aspeed_sgpio.c\n+++ b/hw/gpio/aspeed_sgpio.c\n@@ -51,6 +51,8 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset,\n reg = offset >> 2;\n \n switch (reg) {\n+ case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7:\n+ break;\n case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:\n value = aspeed_sgpio_2700_read_control_reg(s, reg);\n break;\n@@ -82,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data,\n }\n }\n \n+static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin)\n+{\n+ uint32_t value = s->ctrl_regs[pin >> 1];\n+ bool is_input = !(pin % 2);\n+ uint32_t bit_mask = 0;\n+\n+ if (is_input) {\n+ bit_mask = SGPIO_SERIAL_IN_VAL_MASK;\n+ } else {\n+ bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;\n+ }\n+\n+ return value & bit_mask;\n+}\n+\n+static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool level)\n+{\n+ uint32_t value = s->ctrl_regs[pin >> 1];\n+ bool is_input = !(pin % 2);\n+ uint32_t bit_mask = 0;\n+\n+ if (is_input) {\n+ bit_mask = SGPIO_SERIAL_IN_VAL_MASK;\n+ } else {\n+ bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;\n+ }\n+\n+ if (level) {\n+ value |= bit_mask;\n+ } else {\n+ value &= ~bit_mask;\n+ }\n+ s->ctrl_regs[pin >> 1] = value;\n+}\n+\n+static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool level = true;\n+ int pin = 0xfff;\n+ AspeedSGPIOState *s = ASPEED_SGPIO(obj);\n+\n+ if (sscanf(name, \"sgpio%03d\", &pin) != 1) {\n+ error_setg(errp, \"%s: error reading %s\", __func__, name);\n+ return;\n+ }\n+ level = aspeed_sgpio_get_pin_level(s, pin);\n+ visit_type_bool(v, name, &level, errp);\n+}\n+\n+static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool level;\n+ int pin = 0xfff;\n+ AspeedSGPIOState *s = ASPEED_SGPIO(obj);\n+\n+ if (!visit_type_bool(v, name, &level, errp)) {\n+ return;\n+ }\n+ if (sscanf(name, \"sgpio%03d\", &pin) != 1) {\n+ error_setg(errp, \"%s: error reading %s\", __func__, name);\n+ return;\n+ }\n+ aspeed_sgpio_set_pin_level(s, pin, level);\n+}\n+\n static const MemoryRegionOps aspeed_sgpio_2700_ops = {\n .read = aspeed_sgpio_2700_read,\n .write = aspeed_sgpio_2700_write,\n@@ -105,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, Error **errp)\n sysbus_init_mmio(sbd, &s->iomem);\n }\n \n+static void aspeed_sgpio_init(Object *obj)\n+{\n+ for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {\n+ g_autofree char *name = g_strdup_printf(\"sgpio%03d\", i);\n+ object_property_add(obj, name, \"bool\", aspeed_sgpio_get_pin,\n+ aspeed_sgpio_set_pin, NULL, NULL);\n+ }\n+}\n+\n static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n@@ -134,6 +212,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info = {\n .name = TYPE_ASPEED_SGPIO \"-ast2700\",\n .parent = TYPE_ASPEED_SGPIO,\n .class_init = aspeed_sgpio_2700_class_init,\n+ .instance_init = aspeed_sgpio_init,\n };\n \n static void aspeed_sgpio_register_types(void)\n", "prefixes": [ "v5", "2/6" ] }