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GET /api/1.0/patches/2175853/?format=api
{ "id": 2175853, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175853/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251219-aspeed-sgpio-v5-6-fd5593178144@google.com>", "date": "2025-12-19T07:04:19", "name": "[v5,6/6] test/qtest: Add Unit test for Aspeed SGPIO", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f6615d925756444fcd5ccbbf19b54285902f3368", "submitter": { "id": 91652, "url": "http://patchwork.ozlabs.org/api/1.0/people/91652/?format=api", "name": "Yubin Zou", "email": "yubinz@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-6-fd5593178144@google.com/mbox/", "series": [ { "id": 485958, "url": "http://patchwork.ozlabs.org/api/1.0/series/485958/?format=api", "date": "2025-12-19T07:04:13", "name": "hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485958/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175853/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=Bc4YhuDZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 18\n Dec 2025 23:04:47 -0800 (PST)", "Date": "Fri, 19 Dec 2025 07:04:19 +0000", "In-Reply-To": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "Mime-Version": "1.0", "References": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "X-Mailer": "b4 0.14.2", "Message-ID": "<20251219-aspeed-sgpio-v5-6-fd5593178144@google.com>", "Subject": "[PATCH v5 6/6] test/qtest: Add Unit test for Aspeed SGPIO", "From": "Yubin Zou <yubinz@google.com>", "To": "qemu-devel@nongnu.org", "Cc": "\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Jamin Lin <jamin_lin@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Kane-Chen-AS <kane_chen@aspeedtech.com>,\n Nabih Estefan <nabihestefan@google.com>, qemu-arm@nongnu.org,\n Yubin Zou <yubinz@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::54a;\n envelope-from=3D_lEaQYKCmYcYFMRdKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--yubinz.bounces.google.com;\n helo=mail-pg1-x54a.google.com", "X-Spam_score_int": "-95", "X-Spam_score": "-9.6", "X-Spam_bar": "---------", "X-Spam_report": "(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit introduces a new qtest for the Aspeed SGPIO controller\nThe test covers the following:\n - Setting and clearing SGPIO output pins and verifying the pin state.\n - Setting and clearing SGPIO input pins and verifying the pin state.\n - Verifying that level-high interrupts are correctly triggered and cleared.\n\nSigned-off-by: Yubin Zou <yubinz@google.com>\n---\n tests/qtest/ast2700-sgpio-test.c | 165 +++++++++++++++++++++++++++++++++++++++\n tests/qtest/meson.build | 1 +\n 2 files changed, 166 insertions(+)", "diff": "diff --git a/tests/qtest/ast2700-sgpio-test.c b/tests/qtest/ast2700-sgpio-test.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..14fa4084dad3daedcf78815b05b1282c284f0783\n--- /dev/null\n+++ b/tests/qtest/ast2700-sgpio-test.c\n@@ -0,0 +1,165 @@\n+/*\n+ * QTest testcase for the ASPEED AST2700 SGPIO Controller.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ * Copyright (C) 2025 Google LLC.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/bitops.h\"\n+#include \"qobject/qdict.h\"\n+#include \"libqtest-single.h\"\n+#include \"hw/registerfields.h\"\n+#include \"hw/gpio/aspeed_sgpio.h\"\n+\n+#define AST2700_SGPIO0_BASE 0x14C0C000\n+#define AST2700_SGPIO1_BASE 0x14C0D000\n+\n+static void test_output_pins(const char *machine, const uint32_t base, int idx)\n+{\n+ QTestState *s = qtest_init(machine);\n+ char name[16];\n+ char qom_path[64];\n+ uint32_t offset = 0;\n+ uint32_t value = 0;\n+ for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) {\n+ /* Odd index is output port */\n+ sprintf(name, \"sgpio%03d\", i * 2 + 1);\n+ sprintf(qom_path, \"/machine/soc/sgpio[%d]\", idx);\n+ offset = base + (R_SGPIO_0_CONTROL + i) * 4;\n+ /* set serial output */\n+ qtest_writel(s, offset, 0x00000001);\n+ value = qtest_readl(s, offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 1);\n+ g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true);\n+\n+ /* clear serial output */\n+ qtest_writel(s, offset, 0x00000000);\n+ value = qtest_readl(s, offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 0);\n+ g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false);\n+ }\n+ qtest_quit(s);\n+}\n+\n+static void test_input_pins(const char *machine, const uint32_t base, int idx)\n+{\n+ QTestState *s = qtest_init(machine);\n+ char name[16];\n+ char qom_path[64];\n+ uint32_t offset = 0;\n+ uint32_t value = 0;\n+ for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) {\n+ /* Even index is input port */\n+ sprintf(name, \"sgpio%03d\", i * 2);\n+ sprintf(qom_path, \"/machine/soc/sgpio[%d]\", idx);\n+ offset = base + (R_SGPIO_0_CONTROL + i) * 4;\n+ /* set serial input */\n+ qtest_qom_set_bool(s, qom_path, name, true);\n+ value = qtest_readl(s, offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1);\n+ g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true);\n+\n+ /* clear serial input */\n+ qtest_qom_set_bool(s, qom_path, name, false);\n+ value = qtest_readl(s, offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0);\n+ g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false);\n+ }\n+ qtest_quit(s);\n+}\n+\n+static void test_irq_level_high(const char *machine,\n+ const uint32_t base, int idx)\n+{\n+ QTestState *s = qtest_init(machine);\n+ char name[16];\n+ char qom_path[64];\n+ uint32_t ctrl_offset = 0;\n+ uint32_t int_offset = 0;\n+ uint32_t int_reg_idx = 0;\n+ uint32_t int_bit_idx = 0;\n+ uint32_t value = 0;\n+ for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) {\n+ /* Even index is input port */\n+ sprintf(name, \"sgpio%03d\", i * 2);\n+ sprintf(qom_path, \"/machine/soc/sgpio[%d]\", idx);\n+ int_reg_idx = i / 32;\n+ int_bit_idx = i % 32;\n+ int_offset = base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4;\n+ ctrl_offset = base + (R_SGPIO_0_CONTROL + i) * 4;\n+\n+ /* Enable the interrupt */\n+ value = SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1);\n+ qtest_writel(s, ctrl_offset, value);\n+\n+ /* Set the interrupt type to level-high trigger */\n+ value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset),\n+ SGPIO_INT_TYPE, 3);\n+ qtest_writel(s, ctrl_offset, value);\n+\n+ /* Set serial input high */\n+ qtest_qom_set_bool(s, qom_path, name, true);\n+ value = qtest_readl(s, ctrl_offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1);\n+\n+ /* Interrupt status is set */\n+ value = qtest_readl(s, int_offset);\n+ g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 1);\n+\n+ /* Clear Interrupt */\n+ value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset),\n+ SGPIO_INT_STATUS, 1);\n+ qtest_writel(s, ctrl_offset, value);\n+ value = qtest_readl(s, int_offset);\n+ g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 0);\n+\n+ /* Clear serial input */\n+ qtest_qom_set_bool(s, qom_path, name, false);\n+ value = qtest_readl(s, ctrl_offset);\n+ g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0);\n+ }\n+ qtest_quit(s);\n+}\n+\n+static void test_ast_2700_sgpio_input(void)\n+{\n+ test_input_pins(\"-machine ast2700-evb\",\n+ AST2700_SGPIO0_BASE, 0);\n+ test_input_pins(\"-machine ast2700-evb\",\n+ AST2700_SGPIO1_BASE, 1);\n+}\n+\n+static void test_ast_2700_sgpio_output(void)\n+{\n+ test_output_pins(\"-machine ast2700-evb\",\n+ AST2700_SGPIO0_BASE, 0);\n+ test_output_pins(\"-machine ast2700-evb\",\n+ AST2700_SGPIO1_BASE, 1);\n+ test_irq_level_high(\"-machine ast2700-evb\",\n+ AST2700_SGPIO0_BASE, 0);\n+ test_irq_level_high(\"-machine ast2700-evb\",\n+ AST2700_SGPIO1_BASE, 1);\n+}\n+\n+static void test_ast_2700_sgpio_irq(void)\n+{\n+ test_irq_level_high(\"-machine ast2700-evb\",\n+ AST2700_SGPIO0_BASE, 0);\n+ test_irq_level_high(\"-machine ast2700-evb\",\n+ AST2700_SGPIO1_BASE, 1);\n+}\n+\n+int main(int argc, char **argv)\n+{\n+ g_test_init(&argc, &argv, NULL);\n+\n+ qtest_add_func(\"/ast2700/sgpio/ast_2700_sgpio_input\",\n+ test_ast_2700_sgpio_input);\n+ qtest_add_func(\"/ast2700/sgpio/ast_2700_sgpio_output\",\n+ test_ast_2700_sgpio_output);\n+ qtest_add_func(\"/ast2700/sgpio/ast_2700_sgpio_irq\",\n+ test_ast_2700_sgpio_irq);\n+\n+ return g_test_run();\n+}\ndiff --git a/tests/qtest/meson.build b/tests/qtest/meson.build\nindex 669d07c06bdedc6be0c69acadeba989dc15ddf3f..5c80b2ed6de1f453d2483db482c1b0e7801ba980 100644\n--- a/tests/qtest/meson.build\n+++ b/tests/qtest/meson.build\n@@ -221,6 +221,7 @@ qtests_aspeed = \\\n qtests_aspeed64 = \\\n ['ast2700-gpio-test',\n 'ast2700-hace-test',\n+ 'ast2700-sgpio-test',\n 'ast2700-smc-test']\n \n qtests_stm32l4x5 = \\\n", "prefixes": [ "v5", "6/6" ] }