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GET /api/1.0/patches/2175852/?format=api
{ "id": 2175852, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175852/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251219-aspeed-sgpio-v5-1-fd5593178144@google.com>", "date": "2025-12-19T07:04:14", "name": "[v5,1/6] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb5e087085ff01a4239da126369a6b9347ac4f7e", "submitter": { "id": 91652, "url": "http://patchwork.ozlabs.org/api/1.0/people/91652/?format=api", "name": "Yubin Zou", "email": "yubinz@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com/mbox/", "series": [ { "id": 485958, "url": "http://patchwork.ozlabs.org/api/1.0/series/485958/?format=api", "date": "2025-12-19T07:04:13", "name": "hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485958/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175852/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=zPdgy7Ly;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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CffDzBNEDFoF6nH4sd725Gf1k11fxdD8niguw=", "X-Google-Smtp-Source": "\n AGHT+IF0xNoL+3yHdLaSkDB2AQcxYdNYa3wwLc+W6CHeQL0u7vSvn+ToCF1Z9dW1BsMKoYN5wrLjvRG8Gzs=", "X-Received": "from dlah7.prod.google.com ([2002:a05:701b:2607:b0:11d:cd2a:4c1b])\n (user=yubinz job=prod-delivery.src-stubby-dispatcher) by\n 2002:a05:7022:1a83:b0:11f:1500:4e9a\n with SMTP id a92af1059eb24-121722e03e0mr2604461c88.32.1766127879707; Thu, 18\n Dec 2025 23:04:39 -0800 (PST)", "Date": "Fri, 19 Dec 2025 07:04:14 +0000", "In-Reply-To": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "Mime-Version": "1.0", "References": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "X-Mailer": "b4 0.14.2", "Message-ID": "<20251219-aspeed-sgpio-v5-1-fd5593178144@google.com>", "Subject": "[PATCH v5 1/6] hw/gpio/aspeed_sgpio: Add basic device model for\n Aspeed SGPIO", "From": "Yubin Zou <yubinz@google.com>", "To": "qemu-devel@nongnu.org", "Cc": "\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Jamin Lin <jamin_lin@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Kane-Chen-AS <kane_chen@aspeedtech.com>,\n Nabih Estefan <nabihestefan@google.com>, qemu-arm@nongnu.org,\n Yubin Zou <yubinz@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::549;\n envelope-from=3B_lEaQYKCl4UQ7EJVCKKCHA.8KIMAIQ-9ARAHJKJCJQ.KNC@flex--yubinz.bounces.google.com;\n helo=mail-pg1-x549.google.com", "X-Spam_score_int": "-95", "X-Spam_score": "-9.6", "X-Spam_bar": "---------", "X-Spam_report": "(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This initial implementation includes the basic device structure,\nmemory-mapped register definitions, and read/write handlers for the\nSGPIO control registers.\n\nSigned-off-by: Yubin Zou <yubinz@google.com>\n---\n include/hw/gpio/aspeed_sgpio.h | 66 +++++++++++++++++++\n hw/gpio/aspeed_sgpio.c | 145 +++++++++++++++++++++++++++++++++++++++++\n hw/gpio/meson.build | 1 +\n 3 files changed, 212 insertions(+)", "diff": "diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..60279a597c722f94fba406d60cb30a52ef9544bc\n--- /dev/null\n+++ b/include/hw/gpio/aspeed_sgpio.h\n@@ -0,0 +1,66 @@\n+/*\n+ * ASPEED Serial GPIO Controller\n+ *\n+ * Copyright 2025 Google LLC.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+#ifndef ASPEED_SGPIO_H\n+#define ASPEED_SGPIO_H\n+\n+#include \"hw/sysbus.h\"\n+#include \"qom/object.h\"\n+#include \"hw/registerfields.h\"\n+\n+#define TYPE_ASPEED_SGPIO \"aspeed.sgpio\"\n+OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO)\n+\n+#define ASPEED_SGPIO_MAX_PIN_PAIR 256\n+#define ASPEED_SGPIO_MAX_INT 8\n+\n+/* AST2700 SGPIO Register Address Offsets */\n+REG32(SGPIO_INT_STATUS_0, 0x40)\n+REG32(SGPIO_INT_STATUS_1, 0x44)\n+REG32(SGPIO_INT_STATUS_2, 0x48)\n+REG32(SGPIO_INT_STATUS_3, 0x4C)\n+REG32(SGPIO_INT_STATUS_4, 0x50)\n+REG32(SGPIO_INT_STATUS_5, 0x54)\n+REG32(SGPIO_INT_STATUS_6, 0x58)\n+REG32(SGPIO_INT_STATUS_7, 0x5C)\n+/* AST2700 SGPIO_0 - SGPIO_255 Control Register */\n+REG32(SGPIO_0_CONTROL, 0x80)\n+ SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1)\n+ SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1)\n+ SHARED_FIELD(SGPIO_INT_EN, 2, 1)\n+ SHARED_FIELD(SGPIO_INT_TYPE, 3, 3)\n+ SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1)\n+ SHARED_FIELD(SGPIO_RESERVED_1, 7, 2)\n+ SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1)\n+ SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1)\n+ SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1)\n+ SHARED_FIELD(SGPIO_INT_STATUS, 12, 1)\n+ SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1)\n+ SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1)\n+ SHARED_FIELD(SGPIO_RESERVED_2, 15, 12)\n+ SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1)\n+REG32(SGPIO_255_CONTROL, 0x47C)\n+\n+struct AspeedSGPIOClass {\n+ SysBusDeviceClass parent_class;\n+ uint32_t nr_sgpio_pin_pairs;\n+ uint64_t mem_size;\n+ const MemoryRegionOps *reg_ops;\n+};\n+\n+struct AspeedSGPIOState {\n+ /* <private> */\n+ SysBusDevice parent;\n+\n+ /*< public >*/\n+ MemoryRegion iomem;\n+ qemu_irq irq;\n+ uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR];\n+ uint32_t int_regs[ASPEED_SGPIO_MAX_INT];\n+};\n+\n+#endif /* ASPEED_SGPIO_H */\ndiff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..167a72c41e96c67bd1867a19e2b1706f5bd074e4\n--- /dev/null\n+++ b/hw/gpio/aspeed_sgpio.c\n@@ -0,0 +1,145 @@\n+/*\n+ * ASPEED Serial GPIO Controller\n+ *\n+ * Copyright 2025 Google LLC.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/host-utils.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qapi/error.h\"\n+#include \"qapi/visitor.h\"\n+#include \"hw/qdev-properties.h\"\n+#include \"hw/gpio/aspeed_sgpio.h\"\n+\n+static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s,\n+ uint32_t reg)\n+{\n+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);\n+ uint32_t idx = reg - R_SGPIO_0_CONTROL;\n+ if (idx >= agc->nr_sgpio_pin_pairs) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: pin index: %d, out of bounds\\n\",\n+ __func__, idx);\n+ return 0;\n+ }\n+ return s->ctrl_regs[idx];\n+}\n+\n+static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s,\n+ uint32_t reg, uint64_t data)\n+{\n+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);\n+ uint32_t idx = reg - R_SGPIO_0_CONTROL;\n+ if (idx >= agc->nr_sgpio_pin_pairs) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: pin index: %d, out of bounds\\n\",\n+ __func__, idx);\n+ return;\n+ }\n+ s->ctrl_regs[idx] = data;\n+}\n+\n+static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset,\n+ uint32_t size)\n+{\n+ AspeedSGPIOState *s = ASPEED_SGPIO(opaque);\n+ uint64_t value = 0;\n+ uint64_t reg;\n+\n+ reg = offset >> 2;\n+\n+ switch (reg) {\n+ case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:\n+ value = aspeed_sgpio_2700_read_control_reg(s, reg);\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: no getter for offset 0x%\"\n+ HWADDR_PRIx\"\\n\", __func__, offset);\n+ return 0;\n+ }\n+\n+ return value;\n+}\n+\n+static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data,\n+ uint32_t size)\n+{\n+ AspeedSGPIOState *s = ASPEED_SGPIO(opaque);\n+ uint64_t reg;\n+\n+ reg = offset >> 2;\n+\n+ switch (reg) {\n+ case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:\n+ aspeed_sgpio_2700_write_control_reg(s, reg, data);\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: no setter for offset 0x%\"\n+ HWADDR_PRIx\"\\n\", __func__, offset);\n+ return;\n+ }\n+}\n+\n+static const MemoryRegionOps aspeed_sgpio_2700_ops = {\n+ .read = aspeed_sgpio_2700_read,\n+ .write = aspeed_sgpio_2700_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid.min_access_size = 4,\n+ .valid.max_access_size = 4,\n+};\n+\n+static void aspeed_sgpio_realize(DeviceState *dev, Error **errp)\n+{\n+ AspeedSGPIOState *s = ASPEED_SGPIO(dev);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);\n+\n+ /* Interrupt parent line */\n+ sysbus_init_irq(sbd, &s->irq);\n+\n+ memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s,\n+ TYPE_ASPEED_SGPIO, agc->mem_size);\n+\n+ sysbus_init_mmio(sbd, &s->iomem);\n+}\n+\n+static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = aspeed_sgpio_realize;\n+ dc->desc = \"Aspeed SGPIO Controller\";\n+}\n+\n+static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *data)\n+{\n+ AspeedSGPIOClass *agc = ASPEED_SGPIO_CLASS(klass);\n+ agc->nr_sgpio_pin_pairs = ASPEED_SGPIO_MAX_PIN_PAIR;\n+ agc->mem_size = 0x1000;\n+ agc->reg_ops = &aspeed_sgpio_2700_ops;\n+}\n+\n+static const TypeInfo aspeed_sgpio_info = {\n+ .name = TYPE_ASPEED_SGPIO,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(AspeedSGPIOState),\n+ .class_size = sizeof(AspeedSGPIOClass),\n+ .class_init = aspeed_sgpio_class_init,\n+ .abstract = true,\n+};\n+\n+static const TypeInfo aspeed_sgpio_ast2700_info = {\n+ .name = TYPE_ASPEED_SGPIO \"-ast2700\",\n+ .parent = TYPE_ASPEED_SGPIO,\n+ .class_init = aspeed_sgpio_2700_class_init,\n+};\n+\n+static void aspeed_sgpio_register_types(void)\n+{\n+ type_register_static(&aspeed_sgpio_info);\n+ type_register_static(&aspeed_sgpio_ast2700_info);\n+}\n+\n+type_init(aspeed_sgpio_register_types);\ndiff --git a/hw/gpio/meson.build b/hw/gpio/meson.build\nindex 74840619c01bf4d9a02c058c434c3ec9d2a55bee..6a67ee958faace69ffd3fe08e8ade31ced0faf7e 100644\n--- a/hw/gpio/meson.build\n+++ b/hw/gpio/meson.build\n@@ -16,5 +16,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(\n ))\n system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))\n system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))\n+system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c'))\n system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))\n system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c'))\n", "prefixes": [ "v5", "1/6" ] }