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GET /api/1.0/patches/2175851/?format=api
{ "id": 2175851, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175851/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251219-aspeed-sgpio-v5-4-fd5593178144@google.com>", "date": "2025-12-19T07:04:17", "name": "[v5,4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f361c19b93f8d6fd0155db92b3f3ce24b7d68483", "submitter": { "id": 91652, "url": "http://patchwork.ozlabs.org/api/1.0/people/91652/?format=api", "name": "Yubin Zou", "email": "yubinz@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-4-fd5593178144@google.com/mbox/", "series": [ { "id": 485958, "url": "http://patchwork.ozlabs.org/api/1.0/series/485958/?format=api", "date": "2025-12-19T07:04:13", "name": "hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485958/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175851/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=RfSB9zUa;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 18\n Dec 2025 23:04:44 -0800 (PST)", "Date": "Fri, 19 Dec 2025 07:04:17 +0000", "In-Reply-To": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "Mime-Version": "1.0", "References": "<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>", "X-Mailer": "b4 0.14.2", "Message-ID": "<20251219-aspeed-sgpio-v5-4-fd5593178144@google.com>", "Subject": "[PATCH v5 4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two\n SGPIO controllers", "From": "Yubin Zou <yubinz@google.com>", "To": "qemu-devel@nongnu.org", "Cc": "\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Jamin Lin <jamin_lin@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Kane-Chen-AS <kane_chen@aspeedtech.com>,\n Nabih Estefan <nabihestefan@google.com>, qemu-arm@nongnu.org,\n Yubin Zou <yubinz@google.com>,\n \" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" <clg@redhat.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "quoted-printable", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::124a;\n envelope-from=3DPlEaQYKCmMZVCJOaHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--yubinz.bounces.google.com;\n helo=mail-dl1-x124a.google.com", "X-Spam_score_int": "-95", "X-Spam_score": "-9.6", "X-Spam_bar": "---------", "X-Spam_report": "(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit updates the Aspeed SoC model to support two SGPIO\ncontrollers, reflecting the hardware capabilities of the AST2700\n\nThe memory map and interrupt map are updated to include entries for\ntwo SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a\nprerequisite for the full implementation of the SGPIO device model.\n\nSigned-off-by: Yubin Zou <yubinz@google.com>\nReviewed-by: Cédric Le Goater <clg@redhat.com>\n---\n include/hw/arm/aspeed_soc.h | 8 ++++++--\n hw/arm/aspeed_ast10x0.c | 6 +++---\n hw/arm/aspeed_ast27x0.c | 10 ++++++++++\n 3 files changed, 19 insertions(+), 5 deletions(-)", "diff": "diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\nindex 4b8e599f1a53bfb2e4d3196d5495cd316f799354..18ff961a38508c5df83b46e187f732d736443f20 100644\n--- a/include/hw/arm/aspeed_soc.h\n+++ b/include/hw/arm/aspeed_soc.h\n@@ -32,6 +32,7 @@\n #include \"hw/net/ftgmac100.h\"\n #include \"target/arm/cpu.h\"\n #include \"hw/gpio/aspeed_gpio.h\"\n+#include \"hw/gpio/aspeed_sgpio.h\"\n #include \"hw/sd/aspeed_sdhci.h\"\n #include \"hw/usb/hcd-ehci.h\"\n #include \"qom/object.h\"\n@@ -46,6 +47,7 @@\n #define VBOOTROM_FILE_NAME \"ast27x0_bootrom.bin\"\n \n #define ASPEED_SPIS_NUM 3\n+#define ASPEED_SGPIO_NUM 2\n #define ASPEED_EHCIS_NUM 4\n #define ASPEED_WDTS_NUM 8\n #define ASPEED_CPUS_NUM 4\n@@ -89,6 +91,7 @@ struct AspeedSoCState {\n AspeedMiiState mii[ASPEED_MACS_NUM];\n AspeedGPIOState gpio;\n AspeedGPIOState gpio_1_8v;\n+ AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM];\n AspeedSDHCIState sdhci;\n AspeedSDHCIState emmc;\n AspeedLPCState lpc;\n@@ -106,7 +109,6 @@ struct AspeedSoCState {\n UnimplementedDeviceState pwm;\n UnimplementedDeviceState espi;\n UnimplementedDeviceState udc;\n- UnimplementedDeviceState sgpiom;\n UnimplementedDeviceState ltpi;\n UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];\n AspeedAPB2OPBState fsi[2];\n@@ -166,6 +168,7 @@ struct AspeedSoCClass {\n uint64_t secsram_size;\n int pcie_num;\n int spis_num;\n+ int sgpio_num;\n int ehcis_num;\n int wdts_num;\n int macs_num;\n@@ -221,6 +224,8 @@ enum {\n ASPEED_DEV_SDHCI,\n ASPEED_DEV_GPIO,\n ASPEED_DEV_GPIO_1_8V,\n+ ASPEED_DEV_SGPIOM0,\n+ ASPEED_DEV_SGPIOM1,\n ASPEED_DEV_RTC,\n ASPEED_DEV_TIMER1,\n ASPEED_DEV_TIMER2,\n@@ -263,7 +268,6 @@ enum {\n ASPEED_DEV_I3C,\n ASPEED_DEV_ESPI,\n ASPEED_DEV_UDC,\n- ASPEED_DEV_SGPIOM,\n ASPEED_DEV_JTAG0,\n ASPEED_DEV_JTAG1,\n ASPEED_DEV_FSI1,\ndiff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c\nindex 7f49c13391be0b923e317409a0fccfa741f5e658..c141cc080422579ca6b6965369d84dfbe416247b 100644\n--- a/hw/arm/aspeed_ast10x0.c\n+++ b/hw/arm/aspeed_ast10x0.c\n@@ -36,7 +36,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {\n [ASPEED_DEV_ESPI] = 0x7E6EE000,\n [ASPEED_DEV_SBC] = 0x7E6F2000,\n [ASPEED_DEV_GPIO] = 0x7E780000,\n- [ASPEED_DEV_SGPIOM] = 0x7E780500,\n+ [ASPEED_DEV_SGPIOM0] = 0x7E780500,\n [ASPEED_DEV_TIMER1] = 0x7E782000,\n [ASPEED_DEV_UART1] = 0x7E783000,\n [ASPEED_DEV_UART2] = 0x7E78D000,\n@@ -94,7 +94,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {\n [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */\n [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */\n [ASPEED_DEV_UDC] = 9,\n- [ASPEED_DEV_SGPIOM] = 51,\n+ [ASPEED_DEV_SGPIOM0] = 51,\n [ASPEED_DEV_JTAG0] = 27,\n [ASPEED_DEV_JTAG1] = 53,\n };\n@@ -427,7 +427,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)\n sc->memmap[ASPEED_DEV_UDC], 0x1000);\n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom),\n \"aspeed.sgpiom\",\n- sc->memmap[ASPEED_DEV_SGPIOM], 0x100);\n+ sc->memmap[ASPEED_DEV_SGPIOM0], 0x100);\n \n aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),\n \"aspeed.jtag\",\ndiff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\nindex c484bcd4e22fb49faf9c16992ae2cdfd6cd82da4..e5f04bd16e80696e41005d9062a6df6d060b8088 100644\n--- a/hw/arm/aspeed_ast27x0.c\n+++ b/hw/arm/aspeed_ast27x0.c\n@@ -69,6 +69,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {\n [ASPEED_DEV_ADC] = 0x14C00000,\n [ASPEED_DEV_SCUIO] = 0x14C02000,\n [ASPEED_DEV_GPIO] = 0x14C0B000,\n+ [ASPEED_DEV_SGPIOM0] = 0x14C0C000,\n+ [ASPEED_DEV_SGPIOM1] = 0x14C0D000,\n [ASPEED_DEV_I2C] = 0x14C0F000,\n [ASPEED_DEV_INTCIO] = 0x14C18000,\n [ASPEED_DEV_PCIE_PHY2] = 0x14C1C000,\n@@ -122,6 +124,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {\n [ASPEED_DEV_KCS] = 128,\n [ASPEED_DEV_ADC] = 130,\n [ASPEED_DEV_GPIO] = 130,\n+ [ASPEED_DEV_SGPIOM0] = 130,\n+ [ASPEED_DEV_SGPIOM1] = 130,\n [ASPEED_DEV_I2C] = 130,\n [ASPEED_DEV_FMC] = 131,\n [ASPEED_DEV_WDT] = 131,\n@@ -173,6 +177,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {\n [ASPEED_DEV_I2C] = 194,\n [ASPEED_DEV_ADC] = 194,\n [ASPEED_DEV_GPIO] = 194,\n+ [ASPEED_DEV_SGPIOM0] = 194,\n+ [ASPEED_DEV_SGPIOM1] = 194,\n [ASPEED_DEV_FMC] = 195,\n [ASPEED_DEV_WDT] = 195,\n [ASPEED_DEV_PWM] = 195,\n@@ -214,6 +220,8 @@ static const int ast2700_gic130_gic194_intcmap[] = {\n [ASPEED_DEV_I2C] = 0,\n [ASPEED_DEV_ADC] = 16,\n [ASPEED_DEV_GPIO] = 18,\n+ [ASPEED_DEV_SGPIOM0] = 21,\n+ [ASPEED_DEV_SGPIOM1] = 24,\n };\n \n /* GICINT 131 */\n@@ -1061,6 +1069,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data)\n sc->sram_size = 0x20000;\n sc->pcie_num = 0;\n sc->spis_num = 3;\n+ sc->sgpio_num = 2;\n sc->ehcis_num = 2;\n sc->wdts_num = 8;\n sc->macs_num = 1;\n@@ -1089,6 +1098,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)\n sc->sram_size = 0x20000;\n sc->pcie_num = 3;\n sc->spis_num = 3;\n+ sc->sgpio_num = 2;\n sc->ehcis_num = 4;\n sc->wdts_num = 8;\n sc->macs_num = 3;\n", "prefixes": [ "v5", "4/6" ] }