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GET /api/1.0/patches/2175815/?format=api
{ "id": 2175815, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175815/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-9-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:29", "name": "[9/9] clk: mediatek: mt8365: fix missing topckgen IDs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3c09fc5ef6d3eb8941bd107f8913c0dced4e2077", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-9-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175815/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=GJK2DCXX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-9-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=7408; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=g3NUKP4hQnIsAL/5Bxbiv+YqlA2RgtEBuEugq6lUz/s=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0p4oLdHq72n0nCa53DF1HwS4rxT7ntzwtSn\n NIh1rZfzzqJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNKRYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A2YAIAJqEDQIwnBSNNydq2KEvR3+0odHvTFDEaG+FN6j\n YEjbwvscdyItEpN3PdrBVdJN+1Jg6ff6UQ+WZa67WAmlKIme+E15mpqW+UeYLciBIkqoafs506k\n oMqlas5idpagQdzk7N8vYPU8f5446PwrbBdF4U8V7aIq+NDNZ3UoaUqsCThxdgsuX1tcgHSEo/w\n cgjV6qSrUljoFI8dPSSkBMKrD0UZNlsh4X+eftquFs//UVWUoAUcQawShs8hBNRpju8vIoJosVi\n jNxnK/O8d7dhERX3n3NLroukckxQHNEf5QU1rV0LuhLOJBWMzqnPbeNaeE7jATJ88vQibouKld7\n wqf4=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Use a ID map to add clocks for the missing CLK_TOP_CLK32K and\nCLK_TOP_CLK26M that were not included in the devicetree definitions.\n\nThis fixes getting the rate of any clock that had one of these as a\nparent.\n\nCLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted\nnow since we can do that with the ID map as well.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8365.c | 151 +++++++++++++++++++++++++++++++++++++-\n 1 file changed, 147 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex a28547a0cf8..6ba464097ae 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -75,6 +75,146 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = {\n };\n \n /* topckgen */\n+\n+/*\n+ * The devicetree bindings missed a few clocks and can't be changed, so we need\n+ * to provide a mapping to fix the omissions.\n+ */\n+static const int mt8365_topckgen_id_map[] = {\n+\t[0 ... CLK_TOP_NR_CLK - 1]\t= -1,\n+\t/* FIXED */\n+\t/* Fixed 32K oscillator is not available in devicetree definitions */\n+\t[CLK_TOP_CLK32K]\t\t= 0,\n+\t[CLK_TOP_CLK_NULL]\t\t= 1,\n+\t[CLK_TOP_I2S0_BCK]\t\t= 2,\n+\t[CLK_TOP_DSI0_LNTC_DSICK]\t= 3,\n+\t[CLK_TOP_VPLL_DPIX]\t\t= 4,\n+\t[CLK_TOP_LVDSTX_CLKDIG_CTS]\t= 5,\n+\t/* FACTOR */\n+\t[CLK_TOP_MFGPLL]\t\t= 6,\n+\t[CLK_TOP_SYSPLL_D2]\t\t= 7,\n+\t[CLK_TOP_SYSPLL1_D2]\t\t= 8,\n+\t[CLK_TOP_SYSPLL1_D4]\t\t= 9,\n+\t[CLK_TOP_SYSPLL1_D8]\t\t= 10,\n+\t[CLK_TOP_SYSPLL1_D16]\t\t= 11,\n+\t[CLK_TOP_SYSPLL_D3]\t\t= 12,\n+\t[CLK_TOP_SYSPLL2_D2]\t\t= 13,\n+\t[CLK_TOP_SYSPLL2_D4]\t\t= 14,\n+\t[CLK_TOP_SYSPLL2_D8]\t\t= 15,\n+\t[CLK_TOP_SYSPLL_D5]\t\t= 16,\n+\t[CLK_TOP_SYSPLL3_D2]\t\t= 17,\n+\t[CLK_TOP_SYSPLL3_D4]\t\t= 18,\n+\t[CLK_TOP_SYSPLL_D7]\t\t= 19,\n+\t[CLK_TOP_SYSPLL4_D2]\t\t= 20,\n+\t[CLK_TOP_SYSPLL4_D4]\t\t= 21,\n+\t/* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */\n+\t[CLK_TOP_UNIVPLL_D2]\t\t= 22,\n+\t[CLK_TOP_UNIVPLL1_D2]\t\t= 23,\n+\t[CLK_TOP_UNIVPLL1_D4]\t\t= 24,\n+\t[CLK_TOP_UNIVPLL_D3]\t\t= 25,\n+\t[CLK_TOP_UNIVPLL2_D2]\t\t= 26,\n+\t[CLK_TOP_UNIVPLL2_D4]\t\t= 27,\n+\t[CLK_TOP_UNIVPLL2_D8]\t\t= 28,\n+\t[CLK_TOP_UNIVPLL2_D32]\t\t= 29,\n+\t[CLK_TOP_UNIVPLL_D5]\t\t= 30,\n+\t[CLK_TOP_UNIVPLL3_D2]\t\t= 31,\n+\t[CLK_TOP_UNIVPLL3_D4]\t\t= 32,\n+\t[CLK_TOP_MMPLL]\t\t\t= 33,\n+\t[CLK_TOP_MMPLL_D2]\t\t= 34,\n+\t[CLK_TOP_LVDSPLL_D2]\t\t= 35,\n+\t[CLK_TOP_LVDSPLL_D4]\t\t= 36,\n+\t[CLK_TOP_LVDSPLL_D8]\t\t= 37,\n+\t[CLK_TOP_LVDSPLL_D16]\t\t= 38,\n+\t[CLK_TOP_USB20_192M]\t\t= 39,\n+\t[CLK_TOP_USB20_192M_D4]\t\t= 40,\n+\t[CLK_TOP_USB20_192M_D8]\t\t= 41,\n+\t[CLK_TOP_USB20_192M_D16]\t= 42,\n+\t[CLK_TOP_USB20_192M_D32]\t= 43,\n+\t[CLK_TOP_APLL1]\t\t\t= 44,\n+\t[CLK_TOP_APLL1_D2]\t\t= 45,\n+\t[CLK_TOP_APLL1_D4]\t\t= 46,\n+\t[CLK_TOP_APLL1_D8]\t\t= 47,\n+\t[CLK_TOP_APLL2]\t\t\t= 48,\n+\t[CLK_TOP_APLL2_D2]\t\t= 49,\n+\t[CLK_TOP_APLL2_D4]\t\t= 50,\n+\t[CLK_TOP_APLL2_D8]\t\t= 51,\n+\t/* Fixed 26M oscillator is not available in devicetree definitions */\n+\t[CLK_TOP_CLK26M]\t\t= 52,\n+\t[CLK_TOP_SYS_26M_D2]\t\t= 53,\n+\t[CLK_TOP_MSDCPLL]\t\t= 54,\n+\t[CLK_TOP_MSDCPLL_D2]\t\t= 55,\n+\t[CLK_TOP_DSPPLL]\t\t= 56,\n+\t[CLK_TOP_DSPPLL_D2]\t\t= 57,\n+\t[CLK_TOP_DSPPLL_D4]\t\t= 58,\n+\t[CLK_TOP_DSPPLL_D8]\t\t= 59,\n+\t[CLK_TOP_APUPLL]\t\t= 60,\n+\t[CLK_TOP_CLK26M_D52]\t\t= 61,\n+\t/* MUX */\n+\t[CLK_TOP_AXI_SEL]\t\t= 62,\n+\t[CLK_TOP_MEM_SEL]\t\t= 63,\n+\t[CLK_TOP_MM_SEL]\t\t= 64,\n+\t[CLK_TOP_SCP_SEL]\t\t= 65,\n+\t[CLK_TOP_MFG_SEL]\t\t= 66,\n+\t[CLK_TOP_ATB_SEL]\t\t= 67,\n+\t[CLK_TOP_CAMTG_SEL]\t\t= 68,\n+\t[CLK_TOP_CAMTG1_SEL]\t\t= 69,\n+\t[CLK_TOP_UART_SEL]\t\t= 70,\n+\t[CLK_TOP_SPI_SEL]\t\t= 71,\n+\t[CLK_TOP_MSDC50_0_HC_SEL]\t= 72,\n+\t[CLK_TOP_MSDC2_2_HC_SEL]\t= 73,\n+\t[CLK_TOP_MSDC50_0_SEL]\t\t= 74,\n+\t[CLK_TOP_MSDC50_2_SEL]\t\t= 75,\n+\t[CLK_TOP_MSDC30_1_SEL]\t\t= 76,\n+\t[CLK_TOP_AUDIO_SEL]\t\t= 77,\n+\t[CLK_TOP_AUD_INTBUS_SEL]\t= 78,\n+\t[CLK_TOP_AUD_1_SEL]\t\t= 79,\n+\t[CLK_TOP_AUD_2_SEL]\t\t= 80,\n+\t[CLK_TOP_AUD_ENGEN1_SEL]\t= 81,\n+\t[CLK_TOP_AUD_ENGEN2_SEL]\t= 82,\n+\t[CLK_TOP_AUD_SPDIF_SEL]\t\t= 83,\n+\t[CLK_TOP_DISP_PWM_SEL]\t\t= 84,\n+\t[CLK_TOP_DXCC_SEL]\t\t= 85,\n+\t[CLK_TOP_SSUSB_SYS_SEL]\t\t= 86,\n+\t[CLK_TOP_SSUSB_XHCI_SEL]\t= 87,\n+\t[CLK_TOP_SPM_SEL]\t\t= 88,\n+\t[CLK_TOP_I2C_SEL]\t\t= 89,\n+\t[CLK_TOP_PWM_SEL]\t\t= 90,\n+\t[CLK_TOP_SENIF_SEL]\t\t= 91,\n+\t[CLK_TOP_AES_FDE_SEL]\t\t= 92,\n+\t[CLK_TOP_CAMTM_SEL]\t\t= 93,\n+\t[CLK_TOP_DPI0_SEL]\t\t= 94,\n+\t[CLK_TOP_DPI1_SEL]\t\t= 95,\n+\t[CLK_TOP_DSP_SEL]\t\t= 96,\n+\t[CLK_TOP_NFI2X_SEL]\t\t= 97,\n+\t[CLK_TOP_NFIECC_SEL]\t\t= 98,\n+\t[CLK_TOP_ECC_SEL]\t\t= 99,\n+\t[CLK_TOP_ETH_SEL]\t\t= 100,\n+\t[CLK_TOP_GCPU_SEL]\t\t= 101,\n+\t[CLK_TOP_GCPU_CPM_SEL]\t\t= 102,\n+\t[CLK_TOP_APU_SEL]\t\t= 103,\n+\t[CLK_TOP_APU_IF_SEL]\t\t= 104,\n+\t/* GATE */\n+\t[CLK_TOP_AUD_I2S0_M]\t\t= 105,\n+\t[CLK_TOP_AUD_I2S1_M]\t\t= 106,\n+\t[CLK_TOP_AUD_I2S2_M]\t\t= 107,\n+\t[CLK_TOP_AUD_I2S3_M]\t\t= 108,\n+\t[CLK_TOP_AUD_TDMOUT_M]\t\t= 109,\n+\t[CLK_TOP_AUD_TDMOUT_B]\t\t= 110,\n+\t[CLK_TOP_AUD_TDMIN_M]\t\t= 111,\n+\t[CLK_TOP_AUD_TDMIN_B]\t\t= 112,\n+\t[CLK_TOP_AUD_SPDIF_M]\t\t= 113,\n+\t[CLK_TOP_USB20_48M_EN]\t\t= 114,\n+\t[CLK_TOP_UNIVPLL_48M_EN]\t= 115,\n+\t[CLK_TOP_LVDSTX_CLKDIG_EN]\t= 116,\n+\t[CLK_TOP_VPLL_DPIX_EN]\t\t= 117,\n+\t[CLK_TOP_SSUSB_TOP_CK_EN]\t= 118,\n+\t[CLK_TOP_SSUSB_PHY_CK_EN]\t= 119,\n+\t[CLK_TOP_CONN_32K]\t\t= 120,\n+\t[CLK_TOP_CONN_26M]\t\t= 121,\n+\t[CLK_TOP_DSP_32K]\t\t= 122,\n+\t[CLK_TOP_DSP_26M]\t\t= 123,\n+};\n+\n #define FIXED_CLK0(_id, _rate)\t\t\t\t\t\t\\\n \tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n \n@@ -82,6 +222,7 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = {\n \tFIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n+\tFIXED_CLK0(CLK_TOP_CLK32K, 32000),\n \tFIXED_CLK0(CLK_TOP_CLK_NULL, 0),\n \tFIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000),\n \tFIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000),\n@@ -115,7 +256,6 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_SYSPLL_D7, \"syspll_d7\", CLK_APMIXED_MAINPLL, 1, 7),\n \tPLL_FACTOR(CLK_TOP_SYSPLL4_D2, \"syspll4_d2\", CLK_APMIXED_MAINPLL, 1, 14),\n \tPLL_FACTOR(CLK_TOP_SYSPLL4_D4, \"syspll4_d4\", CLK_APMIXED_MAINPLL, 1, 28),\n-\tPLL_FACTOR(CLK_TOP_UNIVPLL, \"univpll\", CLK_APMIXED_UNIV_EN, 1, 2),\n \tPLL_FACTOR(CLK_TOP_UNIVPLL_D2, \"univpll_d2\", CLK_APMIXED_UNIVPLL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_UNIVPLL1_D2, \"univpll1_d2\", CLK_APMIXED_UNIVPLL, 1, 4),\n \tPLL_FACTOR(CLK_TOP_UNIVPLL1_D4, \"univpll1_d4\", CLK_APMIXED_UNIVPLL, 1, 8),\n@@ -146,6 +286,7 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR1(CLK_TOP_APLL2_D2, \"apll2_d2\", CLK_TOP_APLL2, 1, 2),\n \tPLL_FACTOR1(CLK_TOP_APLL2_D4, \"apll2_d4\", CLK_TOP_APLL2, 1, 4),\n \tPLL_FACTOR1(CLK_TOP_APLL2_D8, \"apll2_d8\", CLK_TOP_APLL2, 1, 8),\n+\tPLL_FACTOR2(CLK_TOP_CLK26M, \"clk26m_ck\", CLK_XTAL, 1, 1),\n \tPLL_FACTOR2(CLK_TOP_SYS_26M_D2, \"sys_26m_d2\", CLK_XTAL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL, \"msdcpll_ck\", CLK_APMIXED_MSDCPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL_D2, \"msdcpll_d2\", CLK_APMIXED_MSDCPLL, 1, 2),\n@@ -567,9 +708,11 @@ static const struct mtk_gate top_clk_gates[] = {\n \n static const struct mtk_clk_tree mt8365_topckgen_tree = {\n \t.xtal_rate = 26 * MHZ,\n-\t.fdivs_offs = CLK_TOP_MFGPLL,\n-\t.muxes_offs = CLK_TOP_AXI_SEL,\n-\t.gates_offs = CLK_TOP_AUD_I2S0_M,\n+\t.id_offs_map = mt8365_topckgen_id_map,\n+\t.id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map),\n+\t.fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL],\n+\t.muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL],\n+\t.gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M],\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_divs,\n \t.muxes = top_muxes,\n", "prefixes": [ "9/9" ] }