Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175814/?format=api
{ "id": 2175814, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175814/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-8-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:28", "name": "[8/9] clk: mediatek: mt8365: remove separate topckgen-cg driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6611054ed5bd60262a16d30c264bfe4004c3d10e", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-8-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175814/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=GjJcHEaf;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=baylibre.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.b=\"GjJcHEaf\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=baylibre.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=dlechner@baylibre.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXRjC5975z1xty\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 10:30:07 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 17BE1839F1;\n\tFri, 19 Dec 2025 00:28:38 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 50A3883642; Fri, 19 Dec 2025 00:24:49 +0100 (CET)", "from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com\n [IPv6:2607:f8b0:4864:20::22b])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 81D1A83106\n for <u-boot@lists.denx.de>; Fri, 19 Dec 2025 00:24:46 +0100 (CET)", "by mail-oi1-x22b.google.com with SMTP id\n 5614622812f47-450b2715b6cso689690b6e.0\n for <u-boot@lists.denx.de>; Thu, 18 Dec 2025 15:24:46 -0800 (PST)", "from [127.0.1.1] ([2600:8803:e7e4:500:67e5:27b0:56a0:f05d])\n by smtp.gmail.com with ESMTPSA id\n 5614622812f47-457b3be228asm300334b6e.9.2025.12.18.15.24.44\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 18 Dec 2025 15:24:44 -0800 (PST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766100285;\n x=1766705085;\n darn=lists.denx.de;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to; bh=FYMNgVIOAr8aG7k6mxqnrjxI4rA2NYq6oiu648NtnMw=;\n b=GjJcHEafDMRcFrmgas5Mwx5NMnvkqL/r/TYfsMc44KrAz1JW/CoHpzjvOtGqg1rPfU\n Iqm2eZMrwgS7lzhZjU8tnoeYlYYZVLG4gVmo0muL5D96JOB6dzEi/BYpWijwz8CMow1k\n ckI6xj933MCTyi0rYF6caFTeGZd1ACCbkLKY9IL0sLYrRuw2i3W1HYI7PAmcqXGsa+sm\n ViJVDeK9ib2WDkhQRkKMGtIKjrazhbo7QEaE0L0OdLfnJ6vQYpzWFqd0UbKIPm60VFrZ\n nTQ5dEKal6AJvrReUc7I4IQyr8tDZOrmZith6ziBYe3dFNKQ9KZ7aOC6SjVfZWyNf80E\n SfCA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1766100285; x=1766705085;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=FYMNgVIOAr8aG7k6mxqnrjxI4rA2NYq6oiu648NtnMw=;\n b=KtLJ46fKjKOzsrFtgj/BjZqmkwh6iChQrCb3q3dHqzttyv9ktGk804EDHX5RmUud6q\n 7mciqosQEIrKT60qRZBJidpLA88lG99j2D44/3XCqECOo7XHHlanGlLSXurfz5bVt0fX\n wgNmpj8Jk3BQgEFGoCKFeY3skVfEUApDQI9ikscdzTHDGUgsyPjncEIqLwMUhgQWxF9M\n mG+XEssFc8pfvvYVz8dqf0zyGFHVr4oJfYhywv+g3aZOScSBwYC0cWCVXdq8PV72lQy1\n PAP7thzphRrnOsjftna+8XsVYrCYGdRLGR2FSvfrGKsCkNyCN8F86sUmF9VyOuU6obWN\n alAg==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCV5jibhKE/4sKF+W46ZC3k+l5KEj5l/wZHey2KPrQuMcFuumDiqsPHctbIKIi2DnKLKcU57epk=@lists.denx.de", "X-Gm-Message-State": "AOJu0YwW4JKiqroJfZ9xu1xtNii/WwV2HamRet79xyqkxZWI9A9RuyQW\n mPj8rKof7KXLCCsHFouhRlMCbEjCM2qwclP/xu4KCgy9CYBwfXv+09QtupLat//AEvCu7W9Q4sb\n Otcdj", "X-Gm-Gg": "AY/fxX4Fhq+e1lP1bX0QiOjqpQns7RkwRpljHD8xByDdx/NOGNFGzaJWCYlUDJCyjCS\n 8dgO2HCGNnKumv/Eoi2xRhCLB5CcpRaopaL5JEH6e2KfxB7kS80MrWdyu8wD5oT0y7dnS4rzMtv\n 4hqQTJzF6OYRC2g6V1UBtvUdVcdaIHHuo+qp+WQHuWveOgbr6G97ESVSaxY+UhzxwjmHlMQXHJo\n dCibXVXrLDpfuM6xtS0iyjejo4CiRKM1HUWUrQXQWY2pOjoEwwjwDdzSf2KoGj9R6XoKfklpig+\n 6OQ+7ZUJKK2XtZtfWUPIUbl/pUMWYk+v+Mw22nJ0B7tBnHvIqBKGSjopGfi3Yq4WVdt7a2XVRTX\n 0JlNNnLzslgwuWm7z912DwueNjDM6Itf14p08MdY4GFavw1Ecde3jbGktITiXxZqn9xm1+uE9j5\n mPZIQOTBq3Bbqmg2E=", "X-Google-Smtp-Source": "\n AGHT+IE5LGUkdaMxRhUzAoSlczZYnuNqJTMVF9GIFy5u21QgK0/VxlB0QZHoEHjPSVooUSlva6K2YA==", "X-Received": "by 2002:a05:6808:d50:b0:450:d056:e0d3 with SMTP id\n 5614622812f47-457b2180550mr686882b6e.56.1766100285289;\n Thu, 18 Dec 2025 15:24:45 -0800 (PST)", "From": "David Lechner <dlechner@baylibre.com>", "Date": "Thu, 18 Dec 2025 17:23:28 -0600", "Subject": "[PATCH 8/9] clk: mediatek: mt8365: remove separate topckgen-cg driver", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-8-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=3326; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=IE6nOUmJFckdMnAVgGL/Y1mwp3YR+wbmpxjJNXsYiZs=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0ideImM/OirtRq2HQSjwaL/sF/zcANZQGlE\n u5QkI/66juJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNIhYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AVRIH/2rwPRI9mBS/fh111VTgZN9RWlPRhzhcZecPWNX\n a77pKmaT2D1qitL4ttG6Pis1qPFFbDSVZ18vpkUbH4N+EAKVME5zpOxUIGZe5MflulFnsVyHs/y\n CSG9Wfik65Z6rIAWTtu1tYwK4XLt2UyQ2aioWcOeoy3zn3M9sILPt+E3KtHtfKoIgamNn3pfHAF\n 2O2pc3z2MWO3usVORZxiJ29ThST3X9ts9qBPqDzU2xGyPY7FhcPACoWKJ+HbHpgyySa1T4VkEbL\n qfEoGZpEg9DebL9K6yhkcq4/0cpnpBfyjXcZCIqLQAwC+b1uWgb+WufrAiCchA4OfuRLgWRczGR\n 1FUQ=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Remove the separate topckgen-cg driver for handling clock gates in the\ntopckgen address space. The devicetree bindings for this were not\nacceptable upstream because it was creating a separate clock controller\nusing the same address space as the main topckgen clock controller. The\ngates are moved to the topckgen tree instead.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8365.c | 49 ++++++++++++---------------------------\n 1 file changed, 15 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex eaa5c2cf0dc..a28547a0cf8 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -500,18 +500,6 @@ static const struct mtk_composite top_muxes[] = {\n \tMUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31),\n };\n \n-static const struct mtk_clk_tree mt8365_topckgen_tree = {\n-\t.xtal_rate = 26 * MHZ,\n-\t.fdivs_offs = CLK_TOP_MFGPLL,\n-\t.muxes_offs = CLK_TOP_AXI_SEL,\n-\t.fclks = top_fixed_clks,\n-\t.fdivs = top_divs,\n-\t.muxes = top_muxes,\n-\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n-\t.num_fdivs = ARRAY_SIZE(top_divs),\n-\t.num_muxes = ARRAY_SIZE(top_muxes),\n-};\n-\n /* topckgen cg */\n static const struct mtk_gate_regs top0_cg_regs = {\n \t.set_ofs = 0,\n@@ -577,6 +565,21 @@ static const struct mtk_gate top_clk_gates[] = {\n \tGATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),\n };\n \n+static const struct mtk_clk_tree mt8365_topckgen_tree = {\n+\t.xtal_rate = 26 * MHZ,\n+\t.fdivs_offs = CLK_TOP_MFGPLL,\n+\t.muxes_offs = CLK_TOP_AXI_SEL,\n+\t.gates_offs = CLK_TOP_AUD_I2S0_M,\n+\t.fclks = top_fixed_clks,\n+\t.fdivs = top_divs,\n+\t.muxes = top_muxes,\n+\t.gates = top_clk_gates,\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n+\t.num_gates = ARRAY_SIZE(top_clk_gates),\n+};\n+\n /* infracfg */\n static const struct mtk_gate_regs ifr2_cg_regs = {\n \t.set_ofs = 0x80,\n@@ -725,13 +728,6 @@ static int mt8365_topckgen_probe(struct udevice *dev)\n \treturn mtk_common_clk_init(dev, &mt8365_topckgen_tree);\n }\n \n-static int mt8365_topckgen_cg_probe(struct udevice *dev)\n-{\n-\treturn mtk_common_clk_gate_init(dev, &mt8365_topckgen_tree, top_clk_gates,\n-\t\t\t\t\tARRAY_SIZE(top_clk_gates),\n-\t\t\t\t\tCLK_TOP_AUD_I2S0_M);\n-}\n-\n static int mt8365_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks,\n@@ -748,11 +744,6 @@ static const struct udevice_id mt8365_topckgen_compat[] = {\n \t{ }\n };\n \n-static const struct udevice_id mt8365_topckgen_cg_compat[] = {\n-\t{ .compatible = \"mediatek,mt8365-topckgen-cg\", },\n-\t{ }\n-};\n-\n static const struct udevice_id mt8365_infracfg_compat[] = {\n \t{ .compatible = \"mediatek,mt8365-infracfg\", },\n \t{ }\n@@ -778,16 +769,6 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {\n \t.flags = DM_FLAG_PRE_RELOC,\n };\n \n-U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {\n-\t.name = \"mt8365-topckgen-cg\",\n-\t.id = UCLASS_CLK,\n-\t.of_match = mt8365_topckgen_cg_compat,\n-\t.probe = mt8365_topckgen_cg_probe,\n-\t.priv_auto = sizeof(struct mtk_cg_priv),\n-\t.ops = &mtk_clk_gate_ops,\n-\t.flags = DM_FLAG_PRE_RELOC,\n-};\n-\n U_BOOT_DRIVER(mtk_clk_infracfg) = {\n \t.name = \"mt8365-infracfg\",\n \t.id = UCLASS_CLK,\n", "prefixes": [ "8/9" ] }