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GET /api/1.0/patches/2175812/?format=api
{ "id": 2175812, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175812/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-6-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:26", "name": "[6/9] clk: mediatek: mt8365: split struct mtk_clk_tree", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "58602092cddaaa63c1047f483aefa80fbf143fc2", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-6-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175812/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=il4GsIR5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-6-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=2836; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=Ve+V2OV3jyDD/6JOGRQ4KNDZf0TvPIifKcboeOXWXLw=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0WmceCNjksN6sjaXW+9UAH9IBBRH53+WPJu\n UlcFRPty3yJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNFhYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AqXcH/210vqNkzF8dbXL2FtBqUd8H9R8EkTEgR0cHc7V\n /5sDyoXjkUH8KPUkK9goKGaDIJOVV10h0ZvarxGRGrHFTfUe1MP2gNCW9V19LQAGqXUX5oyUZ0x\n 9IYPBk4HthtG7gOD8WoyfxDsPQKcbOwliT91kSncK9qx7NlyiQf2JpkARg1CQRnEu2KlPGRL3Uw\n B7U2ATeHRRzp5piOy63OriVx7f+rNJx/elIuzutGmH18DkrIyV5S0lRLcyaNtC0M25XQ/EC/W6H\n hARtuyU3xRmUgeGh13t2xheg1xqJ6bxxjzCiZZSBlM3K9qv2MCX/9LhK/m0Zb5G+6XquOHF6kRb\n hNis=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Split the struct mtk_clk_tree for MT8365 into separate structures for\nthe apmixedsys, topckgen and infracfg clock controllers. This is needed\nto support moving the topckgen gates into the struct mtk_clk_tree. Since\napmixedsys can also have gates, we need separate structures.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8365.c | 24 ++++++++++++++++--------\n 1 file changed, 16 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex 4d0a0487b57..eaa5c2cf0dc 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -67,6 +67,13 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \t 0x03A4, 0, 0, 0),\n };\n \n+static const struct mtk_clk_tree mt8365_apmixed_tree = {\n+\t.xtal_rate = 26 * MHZ,\n+\t.xtal2_rate = 26 * MHZ,\n+\t.plls = apmixed_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+};\n+\n /* topckgen */\n #define FIXED_CLK0(_id, _rate)\t\t\t\t\t\t\\\n \tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n@@ -493,16 +500,13 @@ static const struct mtk_composite top_muxes[] = {\n \tMUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31),\n };\n \n-static const struct mtk_clk_tree mt8365_clk_tree = {\n+static const struct mtk_clk_tree mt8365_topckgen_tree = {\n \t.xtal_rate = 26 * MHZ,\n-\t.xtal2_rate = 26 * MHZ,\n \t.fdivs_offs = CLK_TOP_MFGPLL,\n \t.muxes_offs = CLK_TOP_AXI_SEL,\n-\t.plls = apmixed_plls,\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_divs,\n \t.muxes = top_muxes,\n-\t.num_plls = ARRAY_SIZE(apmixed_plls),\n \t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n \t.num_fdivs = ARRAY_SIZE(top_divs),\n \t.num_muxes = ARRAY_SIZE(top_muxes),\n@@ -707,26 +711,30 @@ static const struct mtk_gate ifr_clks[] = {\n \tGATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),\n };\n \n+static const struct mtk_clk_tree mt8365_infracfg_tree = {\n+\t.xtal_rate = 26 * MHZ,\n+};\n+\n static int mt8365_apmixedsys_probe(struct udevice *dev)\n {\n-\treturn mtk_common_clk_init(dev, &mt8365_clk_tree);\n+\treturn mtk_common_clk_init(dev, &mt8365_apmixed_tree);\n }\n \n static int mt8365_topckgen_probe(struct udevice *dev)\n {\n-\treturn mtk_common_clk_init(dev, &mt8365_clk_tree);\n+\treturn mtk_common_clk_init(dev, &mt8365_topckgen_tree);\n }\n \n static int mt8365_topckgen_cg_probe(struct udevice *dev)\n {\n-\treturn mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates,\n+\treturn mtk_common_clk_gate_init(dev, &mt8365_topckgen_tree, top_clk_gates,\n \t\t\t\t\tARRAY_SIZE(top_clk_gates),\n \t\t\t\t\tCLK_TOP_AUD_I2S0_M);\n }\n \n static int mt8365_infracfg_probe(struct udevice *dev)\n {\n-\treturn mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks,\n+\treturn mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks,\n \t\t\t\t\tARRAY_SIZE(ifr_clks), 0);\n }\n \n", "prefixes": [ "6/9" ] }