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GET /api/1.0/patches/2175811/?format=api
{ "id": 2175811, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175811/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-5-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:25", "name": "[5/9] clk: mediatek: mt8365: fix some clock parents", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "bad5d88303ae739d22c5ce3b1a3751b28f50fdce", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-5-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175811/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=wPrOFx4B;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-5-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=5687; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=cRmt4G6GnRvx5ikfKmXg6b9ic9pxDggwV98nL+KLV+o=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0QjblqcK/2J2GUMuJ6R1MIbaU3dV5Zg87Qk\n se8ai3sv2SJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNEBYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A7DwH/jXYk/hIZGgGp4hK5aZGqrqqAG7StltDOfXgDaD\n +fQpXS7/7IGTJkwec7Nm1sNXXKPYS7s6Qcaj3yZ+bYL7UWFoE/gyEZS4mrsCeE8/PJ8ixHbx8kq\n trZvY88IgF67wHAvy+ekgw4RO1vwGPQOcvGBrgb9htXh6Rs8JrQjgPSWs7HHGAtiyXLhPAHhS99\n 1/LusXk7R9XmfqpqhkhMx+yKKbMg4CVl4IVaLCiYeEd524d97IYASfs3N11P2EFezte+nOj4l6p\n PgtLZEsmNggRGjVJSvMAbf91ggQ3Isc45M/t3cmOZdvg1A81C2JN+KT16qbFzk5DiBOKw2DC/8H\n TP6c=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Fix a number of clock parent definitions for MT8365 clocks. Most of\nthese are just informational or don't make a function change.\n\nThe clocks with the new PLL_FACTOR2 macro and the change in apu_parents\nare fixing actual bugs.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8365.c | 48 ++++++++++++++++++++++-----------------\n 1 file changed, 27 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex 13f63d04ad0..4d0a0487b57 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -72,19 +72,25 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n \n #define FIXED_CLK1(_id, _rate)\t\t\t\t\t\t\\\n-\tFIXED_CLK(_id, CLK_TOP_CLK26M, CLK_PARENT_TOPCKGEN, _rate)\n+\tFIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n \tFIXED_CLK0(CLK_TOP_CLK_NULL, 0),\n-\tFIXED_CLK0(CLK_TOP_I2S0_BCK, 26000000),\n-\tFIXED_CLK1(CLK_TOP_DSI0_LNTC_DSICK, 75000000),\n-\tFIXED_CLK1(CLK_TOP_VPLL_DPIX, 75000000),\n-\tFIXED_CLK1(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000),\n+\tFIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000),\n+\tFIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000),\n+\tFIXED_CLK0(CLK_TOP_VPLL_DPIX, 75000000),\n+\tFIXED_CLK0(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000),\n };\n \n #define PLL_FACTOR(_id, _name, _parent, _mult, _div)\t\t\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n+#define PLL_FACTOR1(_id, _name, _parent, _mult, _div)\t\t\t\\\n+\tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)\n+\n+#define PLL_FACTOR2(_id, _name, _parent, _mult, _div)\t\t\t\\\n+\tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)\n+\n static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_MFGPLL, \"mfgpll_ck\", CLK_APMIXED_MFGPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_SYSPLL_D2, \"syspll_d2\", CLK_APMIXED_MAINPLL, 1, 2),\n@@ -120,20 +126,20 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D4, \"lvdspll_d4\", CLK_APMIXED_LVDSPLL, 1, 4),\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D8, \"lvdspll_d8\", CLK_APMIXED_LVDSPLL, 1, 8),\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D16, \"lvdspll_d16\", CLK_APMIXED_LVDSPLL, 1, 16),\n-\tPLL_FACTOR(CLK_TOP_USB20_192M, \"usb20_192m_ck\", CLK_APMIXED_USB20_EN, 1, 13),\n-\tPLL_FACTOR(CLK_TOP_USB20_192M_D4, \"usb20_192m_d4\", CLK_TOP_USB20_192M, 1, 4),\n-\tPLL_FACTOR(CLK_TOP_USB20_192M_D8, \"usb20_192m_d8\", CLK_TOP_USB20_192M, 1, 8),\n-\tPLL_FACTOR(CLK_TOP_USB20_192M_D16, \"usb20_192m_d16\", CLK_TOP_USB20_192M, 1, 16),\n-\tPLL_FACTOR(CLK_TOP_USB20_192M_D32, \"usb20_192m_d32\", CLK_TOP_USB20_192M, 1, 32),\n+\tPLL_FACTOR(CLK_TOP_USB20_192M, \"usb20_192m_ck\", CLK_APMIXED_UNIVPLL, 1, 13),\n+\tPLL_FACTOR1(CLK_TOP_USB20_192M_D4, \"usb20_192m_d4\", CLK_TOP_USB20_192M, 1, 4),\n+\tPLL_FACTOR1(CLK_TOP_USB20_192M_D8, \"usb20_192m_d8\", CLK_TOP_USB20_192M, 1, 8),\n+\tPLL_FACTOR1(CLK_TOP_USB20_192M_D16, \"usb20_192m_d16\", CLK_TOP_USB20_192M, 1, 16),\n+\tPLL_FACTOR1(CLK_TOP_USB20_192M_D32, \"usb20_192m_d32\", CLK_TOP_USB20_192M, 1, 32),\n \tPLL_FACTOR(CLK_TOP_APLL1, \"apll1_ck\", CLK_APMIXED_APLL1, 1, 1),\n-\tPLL_FACTOR(CLK_TOP_APLL1_D2, \"apll1_d2\", CLK_APMIXED_APLL1, 1, 2),\n-\tPLL_FACTOR(CLK_TOP_APLL1_D4, \"apll1_d4\", CLK_APMIXED_APLL1, 1, 4),\n-\tPLL_FACTOR(CLK_TOP_APLL1_D8, \"apll1_d8\", CLK_APMIXED_APLL1, 1, 8),\n+\tPLL_FACTOR1(CLK_TOP_APLL1_D2, \"apll1_d2\", CLK_TOP_APLL1, 1, 2),\n+\tPLL_FACTOR1(CLK_TOP_APLL1_D4, \"apll1_d4\", CLK_TOP_APLL1, 1, 4),\n+\tPLL_FACTOR1(CLK_TOP_APLL1_D8, \"apll1_d8\", CLK_TOP_APLL1, 1, 8),\n \tPLL_FACTOR(CLK_TOP_APLL2, \"apll2_ck\", CLK_APMIXED_APLL2, 1, 1),\n-\tPLL_FACTOR(CLK_TOP_APLL2_D2, \"apll2_d2\", CLK_APMIXED_APLL2, 1, 2),\n-\tPLL_FACTOR(CLK_TOP_APLL2_D4, \"apll2_d4\", CLK_APMIXED_APLL2, 1, 4),\n-\tPLL_FACTOR(CLK_TOP_APLL2_D8, \"apll2_d8\", CLK_APMIXED_APLL2, 1, 8),\n-\tPLL_FACTOR(CLK_TOP_SYS_26M_D2, \"sys_26m_d2\", CLK_XTAL, 1, 2),\n+\tPLL_FACTOR1(CLK_TOP_APLL2_D2, \"apll2_d2\", CLK_TOP_APLL2, 1, 2),\n+\tPLL_FACTOR1(CLK_TOP_APLL2_D4, \"apll2_d4\", CLK_TOP_APLL2, 1, 4),\n+\tPLL_FACTOR1(CLK_TOP_APLL2_D8, \"apll2_d8\", CLK_TOP_APLL2, 1, 8),\n+\tPLL_FACTOR2(CLK_TOP_SYS_26M_D2, \"sys_26m_d2\", CLK_XTAL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL, \"msdcpll_ck\", CLK_APMIXED_MSDCPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL_D2, \"msdcpll_d2\", CLK_APMIXED_MSDCPLL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_DSPPLL, \"dsppll_ck\", CLK_APMIXED_DSPPLL, 1, 1),\n@@ -141,7 +147,7 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_DSPPLL_D4, \"dsppll_d4\", CLK_APMIXED_DSPPLL, 1, 4),\n \tPLL_FACTOR(CLK_TOP_DSPPLL_D8, \"dsppll_d8\", CLK_APMIXED_DSPPLL, 1, 8),\n \tPLL_FACTOR(CLK_TOP_APUPLL, \"apupll_ck\", CLK_APMIXED_APUPLL, 1, 1),\n-\tPLL_FACTOR(CLK_TOP_CLK26M_D52, \"clk26m_d52\", CLK_XTAL, 1, 52),\n+\tPLL_FACTOR2(CLK_TOP_CLK26M_D52, \"clk26m_d52\", CLK_XTAL, 1, 52),\n };\n \n static const int axi_parents[] = {\n@@ -422,7 +428,7 @@ static const int gcpu_cpm_parents[] = {\n static const int apu_parents[] = {\n \tCLK_TOP_CLK26M,\n \tCLK_TOP_UNIVPLL_D2,\n-\tCLK_APMIXED_APUPLL,\n+\tCLK_TOP_APUPLL,\n \tCLK_TOP_MMPLL,\n \tCLK_TOP_SYSPLL_D3,\n \tCLK_TOP_UNIVPLL1_D2,\n@@ -647,8 +653,8 @@ static const struct mtk_gate ifr_clks[] = {\n \tGATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),\n \t/* IFR3 */\n \tGATE_IFR3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),\n-\tGATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),\n-\tGATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),\n+\tGATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_AXI_SEL, 2),\n+\tGATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_AXI_SEL, 3),\n \tGATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),\n \tGATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),\n \tGATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),\n", "prefixes": [ "5/9" ] }