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GET /api/1.0/patches/2175810/?format=api
{ "id": 2175810, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175810/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-4-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:24", "name": "[4/9] clk: mediatek: fix fixed clock parents", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "75c3818f9709d2833e097fd35fff392a71b068ae", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-4-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175810/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=HeF0zVXC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-4-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=20704;\n i=dlechner@baylibre.com; h=from:subject:message-id;\n bh=/bcUzz/7NAu7Yk73oo4msd8wobevFF9LY9P9X5SGS1M=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0IIBrdubX3B516gc6WyOXS0RMWVJR0sxK2c\n +KLFZQSTJyJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNCBYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AhJ8H/RUyTDn/++gJ9gZD6OvbtAJqx2lVzEfGbO0YbSe\n FXW5J2neW1DDmQ6d2LY9BslmBJjm+DaN3pJZNEvubYSrwhP+ozwcGaR3fqdm2kqVu7eVv2G6Mkb\n xOyo3M8E6lX2y1LJ/Y5b0vuwNfwdirTvOYTd5voiaLMeECGtd9TbYghMPxYgMMbXNfyOyAlJz85\n 64/rqNRnluNnbE1fC5My2zNC/kD0IN5jcTHuCr/rEVfiJZiGNnNNyiDzyiYpbnSKK4JVEYfLlgK\n yFEe9FVAofvmA7epdDAZCUSV716nO+EBn/MhI6kCw1uH/mNC0/lv3UgQRkbzK8TeDQ4QF69HYmx\n PHaQ=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add a flags field to struct mtk_fixed_clk to allow properly resolving\nthe parent clock. All chip-specific clocks are updated to populate this\nfield correctly.\n\nThe parent is currently only used for printing debug information, so\nthere are no functional bugs being fixed.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt7622.c | 23 +++++++++++++----------\n drivers/clk/mediatek/clk-mt7623.c | 33 ++++++++++++++++++---------------\n drivers/clk/mediatek/clk-mt7629.c | 23 +++++++++++++----------\n drivers/clk/mediatek/clk-mt7981.c | 21 ++++++++++++---------\n drivers/clk/mediatek/clk-mt7986.c | 21 ++++++++++++---------\n drivers/clk/mediatek/clk-mt7987.c | 19 +++++++++++--------\n drivers/clk/mediatek/clk-mt7988.c | 29 ++++++++++++++++-------------\n drivers/clk/mediatek/clk-mt8183.c | 12 +++++++++---\n drivers/clk/mediatek/clk-mt8365.c | 16 +++++++++++-----\n drivers/clk/mediatek/clk-mt8512.c | 7 +++++--\n drivers/clk/mediatek/clk-mt8516.c | 12 +++++++++---\n drivers/clk/mediatek/clk-mt8518.c | 14 ++++++++++----\n drivers/clk/mediatek/clk-mtk.c | 3 +--\n drivers/clk/mediatek/clk-mtk.h | 4 +++-\n 14 files changed, 143 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c\nindex 9621d5efe11..93e87ee399d 100644\n--- a/drivers/clk/mediatek/clk-mt7622.c\n+++ b/drivers/clk/mediatek/clk-mt7622.c\n@@ -85,6 +85,9 @@ static const struct mtk_gate apmixed_cgs[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\t\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -95,16 +98,16 @@ static const struct mtk_gate apmixed_cgs[] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),\n-\tFIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),\n-\tFIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),\n-\tFIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),\n-\tFIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),\n-\tFIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),\n-\tFIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),\n+\tFIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),\n+\tFIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000),\n+\tFIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000),\n+\tFIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000),\n+\tFIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000),\n+\tFIXED_CLK0(CLK_TOP_SATA_RBC, 50000000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c\nindex 3509ea67e7d..093577c4ee4 100644\n--- a/drivers/clk/mediatek/clk-mt7623.c\n+++ b/drivers/clk/mediatek/clk-mt7623.c\n@@ -259,6 +259,9 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = {\n \t[CLK_TOP_AUD_I2S6_MCLK]\t\t\t= 158,\n };\n \n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\t\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -269,21 +272,21 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),\n-\tFIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),\n-\tFIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),\n-\tFIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),\n-\tFIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),\n-\tFIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),\n-\tFIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),\n-\tFIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),\n-\tFIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),\n-\tFIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),\n-\tFIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),\n-\tFIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),\n-\tFIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),\n-\tFIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),\n-\tFIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),\n+\tFIXED_CLK0(CLK_TOP_DPI, 108 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_DMPLL, 400 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_VENCPLL, 295.75 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_HDMI_0_PIX340M, 340 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_HDMI_0_DEEP340M, 340 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_HDMI_0_PLL340M, 340 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_HADDS2_FB, 27 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_WBG_DIG_416M, 416 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_DSI0_LNTC_DSI, 143 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_HDMI_SCL_RX, 27 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_32K_EXTERNAL, 32000),\n+\tFIXED_CLK0(CLK_TOP_HDMITX_CLKDIG_CTS, 300 * MHZ),\n+\tFIXED_CLK0(CLK_TOP_AUD_EXT1, 0),\n+\tFIXED_CLK0(CLK_TOP_AUD_EXT2, 0),\n+\tFIXED_CLK0(CLK_TOP_NFI1X_PAD, 0),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c\nindex 5bbac309e9d..582394f594b 100644\n--- a/drivers/clk/mediatek/clk-mt7629.c\n+++ b/drivers/clk/mediatek/clk-mt7629.c\n@@ -61,6 +61,9 @@ static const struct mtk_pll_data apmixed_plls[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\t\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -71,16 +74,16 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),\n-\tFIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),\n-\tFIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),\n-\tFIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),\n-\tFIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),\n-\tFIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),\n-\tFIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),\n-\tFIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),\n+\tFIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),\n+\tFIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000),\n+\tFIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000),\n+\tFIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333),\n+\tFIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000),\n+\tFIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000),\n+\tFIXED_CLK0(CLK_TOP_SATA_RBC, 50000000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c\nindex 73dc5cfe19d..c90fb2ce787 100644\n--- a/drivers/clk/mediatek/clk-mt7981.c\n+++ b/drivers/clk/mediatek/clk-mt7981.c\n@@ -18,6 +18,9 @@\n #define MT7981_CLK_PDN 0x250\n #define MT7981_CLK_PDN_EN_WRITE BIT(31)\n \n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -29,19 +32,19 @@\n \n /* FIXED PLLS */\n static const struct mtk_fixed_clk fixed_pll_clks[] = {\n-\tFIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),\n-\tFIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),\n-\tFIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),\n-\tFIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),\n-\tFIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),\n-\tFIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),\n-\tFIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),\n-\tFIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),\n+\tFIXED_CLK0(CLK_APMIXED_ARMPLL, 1300000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),\n+\tFIXED_CLK0(CLK_APMIXED_MMPLL, 720000000),\n+\tFIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),\n+\tFIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),\n+\tFIXED_CLK0(CLK_APMIXED_MPLL, 416000000),\n+\tFIXED_CLK0(CLK_APMIXED_APLL2, 196608000),\n };\n \n /* TOPCKGEN FIXED CLK */\n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),\n+\tFIXED_CLK0(CLK_TOP_CB_CKSQ_40M, 40000000),\n };\n \n /* TOPCKGEN FIXED DIV */\ndiff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c\nindex 04040f5ff63..d7b4fc0ddf3 100644\n--- a/drivers/clk/mediatek/clk-mt7986.c\n+++ b/drivers/clk/mediatek/clk-mt7986.c\n@@ -23,6 +23,9 @@\n #define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)\n #define VOID_PARENT PARENT(-1, 0)\n \n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -34,19 +37,19 @@\n \n /* FIXED PLLS */\n static const struct mtk_fixed_clk fixed_pll_clks[] = {\n-\tFIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),\n-\tFIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),\n-\tFIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),\n-\tFIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),\n-\tFIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),\n-\tFIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),\n-\tFIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),\n-\tFIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),\n+\tFIXED_CLK0(CLK_APMIXED_ARMPLL, 2000000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),\n+\tFIXED_CLK0(CLK_APMIXED_MMPLL, 1440000000),\n+\tFIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),\n+\tFIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 760000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),\n+\tFIXED_CLK0(CLK_APMIXED_MPLL, 416000000),\n+\tFIXED_CLK0(CLK_APMIXED_APLL2, 196608000),\n };\n \n /* TOPCKGEN FIXED CLK */\n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),\n+\tFIXED_CLK0(CLK_TOP_XTAL, 40000000),\n };\n \n /* TOPCKGEN FIXED DIV */\ndiff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c\nindex 3a30d16a158..12408c2e0b1 100644\n--- a/drivers/clk/mediatek/clk-mt7987.c\n+++ b/drivers/clk/mediatek/clk-mt7987.c\n@@ -19,6 +19,9 @@\n #define MT7987_CLK_PDN\t\t0x250\n #define MT7987_CLK_PDN_EN_WRITE\tBIT(31)\n \n+#define FIXED_CLK0(_id, _rate) \\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)\n \n@@ -33,14 +36,14 @@\n \n /* FIXED PLLS */\n static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {\n-\tFIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),\n-\tFIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),\n-\tFIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),\n-\tFIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),\n-\tFIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),\n-\tFIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),\n-\tFIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000),\n-\tFIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000),\n+\tFIXED_CLK0(CLK_APMIXED_MPLL, 416000000),\n+\tFIXED_CLK0(CLK_APMIXED_APLL2, 196608000),\n+\tFIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),\n+\tFIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),\n+\tFIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),\n+\tFIXED_CLK0(CLK_APMIXED_ARM_LL, 2000000000),\n+\tFIXED_CLK0(CLK_APMIXED_MSDCPLL, 384000000),\n };\n \n static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {\ndiff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c\nindex 71a16b9f19f..c447936cc40 100644\n--- a/drivers/clk/mediatek/clk-mt7988.c\n+++ b/drivers/clk/mediatek/clk-mt7988.c\n@@ -21,6 +21,9 @@\n #define MT7988_ETHDMA_RST_CTRL_OFS\t0x34\n #define MT7988_ETHWARP_RST_CTRL_OFS\t0x8\n \n+#define FIXED_CLK0(_id, _rate) \\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)\n \n@@ -35,23 +38,23 @@\n \n /* FIXED PLLS */\n static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {\n-\tFIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),\n-\tFIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),\n-\tFIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),\n-\tFIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),\n-\tFIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),\n-\tFIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),\n-\tFIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),\n-\tFIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),\n-\tFIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),\n-\tFIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),\n-\tFIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),\n-\tFIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),\n+\tFIXED_CLK0(CLK_APMIXED_NETSYSPLL, 850000000),\n+\tFIXED_CLK0(CLK_APMIXED_MPLL, 416000000),\n+\tFIXED_CLK0(CLK_APMIXED_MMPLL, 720000000),\n+\tFIXED_CLK0(CLK_APMIXED_APLL2, 196608000),\n+\tFIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),\n+\tFIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),\n+\tFIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),\n+\tFIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),\n+\tFIXED_CLK0(CLK_APMIXED_ARM_B, 1500000000),\n+\tFIXED_CLK0(CLK_APMIXED_CCIPLL2_B, 960000000),\n+\tFIXED_CLK0(CLK_APMIXED_USXGMIIPLL, 644533000),\n+\tFIXED_CLK0(CLK_APMIXED_MSDCPLL, 400000000),\n };\n \n /* TOPCKGEN FIXED CLK */\n static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),\n+\tFIXED_CLK0(CLK_TOP_XTAL, 40000000),\n };\n \n /* TOPCKGEN FIXED DIV */\ndiff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c\nindex 5a353e82f3f..9d9d00622db 100644\n--- a/drivers/clk/mediatek/clk-mt8183.c\n+++ b/drivers/clk/mediatek/clk-mt8183.c\n@@ -67,10 +67,16 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \t 0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0),\n };\n \n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n+#define FIXED_CLK1(_id, _rate)\t\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate)\n+\n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),\n-\tFIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000),\n-\tFIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000),\n+\tFIXED_CLK0(CLK_TOP_CLK26M, 26000000),\n+\tFIXED_CLK0(CLK_TOP_ULPOSC, 250000),\n+\tFIXED_CLK1(CLK_TOP_UNIVP_192M, 192000000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex 02d30ab12d8..13f63d04ad0 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -68,12 +68,18 @@ static const struct mtk_pll_data apmixed_plls[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n+#define FIXED_CLK1(_id, _rate)\t\t\t\t\t\t\\\n+\tFIXED_CLK(_id, CLK_TOP_CLK26M, CLK_PARENT_TOPCKGEN, _rate)\n+\n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),\n-\tFIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000),\n-\tFIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),\n-\tFIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),\n-\tFIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),\n+\tFIXED_CLK0(CLK_TOP_CLK_NULL, 0),\n+\tFIXED_CLK0(CLK_TOP_I2S0_BCK, 26000000),\n+\tFIXED_CLK1(CLK_TOP_DSI0_LNTC_DSICK, 75000000),\n+\tFIXED_CLK1(CLK_TOP_VPLL_DPIX, 75000000),\n+\tFIXED_CLK1(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000),\n };\n \n #define PLL_FACTOR(_id, _name, _parent, _mult, _div)\t\t\t\\\ndiff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c\nindex bad8c62601d..e6ced91fd06 100644\n--- a/drivers/clk/mediatek/clk-mt8512.c\n+++ b/drivers/clk/mediatek/clk-mt8512.c\n@@ -59,6 +59,9 @@ static const struct mtk_pll_data apmixed_plls[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -69,8 +72,8 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),\n-\tFIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),\n+\tFIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),\n+\tFIXED_CLK0(CLK_TOP_CLK32K, 32000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c\nindex a84a5f360f5..4985ba3e5ce 100644\n--- a/drivers/clk/mediatek/clk-mt8516.c\n+++ b/drivers/clk/mediatek/clk-mt8516.c\n@@ -49,6 +49,12 @@ static const struct mtk_pll_data apmixed_plls[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n+#define FIXED_CLK1(_id, _parent, _rate)\t\t\\\n+\tFIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -59,9 +65,9 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),\n-\tFIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),\n-\tFIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),\n+\tFIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),\n+\tFIXED_CLK1(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),\n+\tFIXED_CLK1(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c\nindex 43a06217d33..2fc492e7170 100644\n--- a/drivers/clk/mediatek/clk-mt8518.c\n+++ b/drivers/clk/mediatek/clk-mt8518.c\n@@ -51,6 +51,12 @@ static const struct mtk_pll_data apmixed_plls[] = {\n };\n \n /* topckgen */\n+#define FIXED_CLK0(_id, _rate)\t\t\t\\\n+\tFIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)\n+\n+#define FIXED_CLK1(_id, _rate)\t\t\t\\\n+\tFIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate)\n+\n #define FACTOR0(_id, _parent, _mult, _div)\t\\\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n@@ -61,10 +67,10 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \tFACTOR(_id, _parent, _mult, _div, 0)\n \n static const struct mtk_fixed_clk top_fixed_clks[] = {\n-\tFIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),\n-\tFIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),\n-\tFIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),\n-\tFIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),\n+\tFIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),\n+\tFIXED_CLK1(CLK_TOP_FQ_TRNG_OUT0, 500000000),\n+\tFIXED_CLK1(CLK_TOP_FQ_TRNG_OUT1, 500000000),\n+\tFIXED_CLK0(CLK_TOP_CLK32K, 32000),\n };\n \n static const struct mtk_fixed_factor top_fixed_divs[] = {\ndiff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 6ba2fabfd08..e370d304c03 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -798,8 +798,7 @@ static void mtk_topckgen_dump(struct udevice *dev)\n \t\tprintf(\"[FCLK%u] DT: %u\", i, fclk->id);\n \t\tmtk_clk_print_mapped_id(fclk->id, i, tree->id_offs_map);\n \t\tmtk_clk_print_rate(dev, i);\n-\t\t/* FIXME: fclk needs flags to fully determine parent. */\n-\t\tmtk_clk_print_single_parent(fclk->parent, 0);\n+\t\tmtk_clk_print_single_parent(fclk->parent, fclk->flags);\n \t\tprintf(\"\\n\");\n \t}\n \ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex 25fd156ac30..eefcf5a00e2 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -78,12 +78,14 @@ struct mtk_pll_data {\n struct mtk_fixed_clk {\n \tconst int id;\n \tconst int parent;\n+\tconst int flags;\n \tunsigned long rate;\n };\n \n-#define FIXED_CLK(_id, _parent, _rate) {\t\t\\\n+#define FIXED_CLK(_id, _parent, _flags, _rate) {\t\\\n \t\t.id = _id,\t\t\t\t\\\n \t\t.parent = _parent,\t\t\t\\\n+\t\t.flags = _flags,\t\t\t\\\n \t\t.rate = _rate,\t\t\t\t\\\n \t}\n \n", "prefixes": [ "4/9" ] }