Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175809/?format=api
{ "id": 2175809, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175809/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-3-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:23", "name": "[3/9] clk: mediatek: add separate gates_offs for cg gates", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3ad139c04d1585ecb6a7f700e8d3a0869e41d2b2", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-3-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175809/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=d7wHFGLo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=baylibre.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.b=\"d7wHFGLo\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=baylibre.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=dlechner@baylibre.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXRh02pMGz1y2r\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 10:29:04 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C58A283966;\n\tFri, 19 Dec 2025 00:28:36 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id B3AA383642; Fri, 19 Dec 2025 00:24:42 +0100 (CET)", "from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com\n [IPv6:2607:f8b0:4864:20::22a])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1814B836A3\n for <u-boot@lists.denx.de>; Fri, 19 Dec 2025 00:24:40 +0100 (CET)", "by mail-oi1-x22a.google.com with SMTP id\n 5614622812f47-455bef556a8so756489b6e.1\n for <u-boot@lists.denx.de>; Thu, 18 Dec 2025 15:24:40 -0800 (PST)", "from [127.0.1.1] ([2600:8803:e7e4:500:67e5:27b0:56a0:f05d])\n by smtp.gmail.com with ESMTPSA id\n 5614622812f47-457b3be228asm300334b6e.9.2025.12.18.15.24.37\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 18 Dec 2025 15:24:38 -0800 (PST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766100279;\n x=1766705079;\n darn=lists.denx.de;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to; bh=kxyjmoNA+hDeDxXDjMCctO5cwn5c6BxKt7t4ob6PfGE=;\n b=d7wHFGLoWQU4jbFaVJdh7HZxuTekDwzx3WVZLIjNDGfj0HJoVVRF0D/sUjSiA+4jeS\n +G9gqvz9r4WdhkSNEjWM2AM8Xs0m11qVF/PQxNTrSxHnTiZZsgV4d9dt9r5fQJo0bisx\n XYStK1ggmU3xqG45KjtIVI074qieavBEyULij4qoHP/sTiRYA0mRZkrNEhrg+1S8y5gO\n 5YdnVCCw/uLNp5BCyWb9Jxb0yhnvHcdcBFyCHmdkEZRzXj7ZNNsKBnNrWSS48crDGmwZ\n U2cUPzRnBE2Gwb7v5P1zfD9mqdMQwpah9cF0IHsCg6DE4asJeOQ2ngsEMNu37EWcLZfg\n ZTJg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1766100279; x=1766705079;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=kxyjmoNA+hDeDxXDjMCctO5cwn5c6BxKt7t4ob6PfGE=;\n b=HV94gz6kYPjWuanNdmB3etfyZ2DZUDNiKi87Nj1tP+o6B6+ISkdqnbPPGP7ANgijy2\n c9u9lSGxGc7eUR+l5Hs1F7w/NOtRO9WFnsr1WKCsJspx2UKQCYOHbjQakip0IYflzifS\n dEFeUP3uhVr1bwJdkaKjSvyaLeCU9D03YrrdtN5ms1ppqh4fTNedj4GZd7zVlofqEjIV\n 2Y0I4jC73MD7Of6an0ZeLb9uTHh1xOhHsg+DpP2dEMfeoSkru0FSbx9keLJnf4Ta0h2v\n rqlxHNJgsZ4tc4VpgO7MrFB83hBypPZAtxWebsUTfOUBx802yK0+uOR8YBzNrWvnOaPY\n OVzw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCUo7CLa62C9HfiWkxUQQ6rSM8sTMQLFalYJWqUafSVLz2QUt/mVlMXxlYZDOpC+Lg+8FR4gepY=@lists.denx.de", "X-Gm-Message-State": "AOJu0YzDqnqcRzr3cgZK0VpyNFoDG0sW0aoIH8BpYijyRwg2Y/ev8TyW\n 24SSQf2OUjSsl61pjNASdgzhIjZc2tmy/EeeHV+1/vkn27e50E8eXAjZBEvBq7fh/sw=", "X-Gm-Gg": "AY/fxX6SRyZ6cl8t6ikFWD4BnMKKloZKVLb8E3YHIO2QR0mlq14VHjb8qUZPmVAWTba\n mSvfcoHQTw44ta4Zv5E+KM5OqKyjMjzHFHi00S5MoAPXhJPGMAIB6XNDPIyqk9rhMXuk2CnfX6X\n Cn4Ti19+HD+FVuv1daip2tLpkjeMuk2T5HwzXfqJ30Jp59lFqptU9RU1ULRRGFR1roOYkOKg/sh\n QjlHUmrsa0JYl7Z/eM+LB4arHKLE6TA2yRJiB+DLwIgIQ3676AX080Mv4WCaJ5G/mmRucFMYcjY\n WxJRG1xJQkakEyQfXy8dx1pNoxU868/qkGKtUtnL4KMCGLnDfhQ9SLq1SfqSEefPJorn5ECciqa\n CcVTncizBpTHK8sC8bIZkzi4tQL9dXWqnzGKfhzrWL0+eYU08p8xLNiN/m+H9IFN4k7Fp6ulJWS\n DOQZeXR5rGjy0TItIFgQ7kapPa6A==", "X-Google-Smtp-Source": "\n AGHT+IE/lHnKengOTL0J3dqz0XmgwBwjyxn2oBPM+mmxtAM/kJOKLcE55AABqwpfE6xEsFcgV/Calg==", "X-Received": "by 2002:a05:6808:c286:b0:450:1433:f13a with SMTP id\n 5614622812f47-457b1fc27afmr693318b6e.11.1766100278810;\n Thu, 18 Dec 2025 15:24:38 -0800 (PST)", "From": "David Lechner <dlechner@baylibre.com>", "Date": "Thu, 18 Dec 2025 17:23:23 -0600", "Subject": "[PATCH 3/9] clk: mediatek: add separate gates_offs for cg gates", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-3-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=16479;\n i=dlechner@baylibre.com; h=from:subject:message-id;\n bh=b5n2v+60YKlzy9YHoj2mRbQWnuczzsKlXqCherlRlu8=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0Ckv0aZNa/cNrbaKCsWF5xqWmx+9gi3UM85\n lNIetbOXCWJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNAhYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AWtIIAKFVymzleScEwvk+LUeh6I5Ta0u2S9WX2ej16AG\n RaJNLf8L4sZXvFBZmFuMgK2Y8QPVIE0QckB2+p97uDzT3bV/GufeFVpb7UeT6mnZyZd5dzq0lhk\n ymnqz9yks/t8k79JK5jCVXLKESgrgwYzzMHoXhXV6AwyK1FuQ4jk4+RPX5y+PHL+Uxk5LqqF5C6\n eZHC+WfpI0cfrfOPu10PCF+7d/Zu+vWAhhbGI5cUZ6Ar7QAABpUAydsJQ+93o32GyZW/I7Bh7yg\n cSLwya91jXiI7EC/b1VgYC//pn30PJ1/FU9FQA6GKjiOKRHPxAwXYYAt7BcCTpmOwuYgkxlcq8o\n 4mTU=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add a gates_offs field to struct mtk_cg_priv and use that instead of\nstruct mtk_clk_tree.gates_offs.\n\nPrior to this change, struct mtk_clk_tree.gates_offs could be the offset\nof struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on\nthe context. This was confusing and error-prone. For example, in mt8365\nthere is one set of gates that needs an offset and one that does not\nthat share the same struct mtk_clk_tree. This is fixed in this patch by\ngiving the correct offset for each gate separately.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt7622.c | 8 ++++----\n drivers/clk/mediatek/clk-mt7623.c | 8 +++-----\n drivers/clk/mediatek/clk-mt7629.c | 11 +++++------\n drivers/clk/mediatek/clk-mt7981.c | 6 +++---\n drivers/clk/mediatek/clk-mt7986.c | 2 +-\n drivers/clk/mediatek/clk-mt7987.c | 2 +-\n drivers/clk/mediatek/clk-mt7988.c | 8 ++++----\n drivers/clk/mediatek/clk-mt8183.c | 2 +-\n drivers/clk/mediatek/clk-mt8365.c | 5 +++--\n drivers/clk/mediatek/clk-mt8512.c | 4 ++--\n drivers/clk/mediatek/clk-mt8516.c | 2 +-\n drivers/clk/mediatek/clk-mt8518.c | 2 +-\n drivers/clk/mediatek/clk-mtk.c | 24 +++++++++++++-----------\n drivers/clk/mediatek/clk-mtk.h | 4 +++-\n 14 files changed, 45 insertions(+), 43 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c\nindex 16c6f024e72..9621d5efe11 100644\n--- a/drivers/clk/mediatek/clk-mt7622.c\n+++ b/drivers/clk/mediatek/clk-mt7622.c\n@@ -693,7 +693,7 @@ static int mt7622_pericfg_probe(struct udevice *dev)\n static int mt7622_pciesys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs,\n-\t\t\t\t\tARRAY_SIZE(pcie_cgs));\n+\t\t\t\t\tARRAY_SIZE(pcie_cgs), 0);\n }\n \n static int mt7622_pciesys_bind(struct udevice *dev)\n@@ -712,7 +712,7 @@ static int mt7622_pciesys_bind(struct udevice *dev)\n static int mt7622_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs,\n-\t\t\t\t\tARRAY_SIZE(eth_cgs));\n+\t\t\t\t\tARRAY_SIZE(eth_cgs), 0);\n }\n \n static int mt7622_ethsys_bind(struct udevice *dev)\n@@ -731,13 +731,13 @@ static int mt7622_ethsys_bind(struct udevice *dev)\n static int mt7622_sgmiisys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs,\n-\t\t\t\t\tARRAY_SIZE(sgmii_cgs));\n+\t\t\t\t\tARRAY_SIZE(sgmii_cgs), 0);\n }\n \n static int mt7622_ssusbsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs,\n-\t\t\t\t\tARRAY_SIZE(ssusb_cgs));\n+\t\t\t\t\tARRAY_SIZE(ssusb_cgs), 0);\n }\n \n static const struct udevice_id mt7622_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c\nindex 6ce1d729736..3509ea67e7d 100644\n--- a/drivers/clk/mediatek/clk-mt7623.c\n+++ b/drivers/clk/mediatek/clk-mt7623.c\n@@ -1055,15 +1055,13 @@ static int mt7623_topckgen_probe(struct udevice *dev)\n }\n \n static const struct mtk_clk_tree mt7623_clk_gate_tree = {\n-\t/* Each CLK ID for gates clock starts at index 1 */\n-\t.gates_offs = 1,\n \t.xtal_rate = 26 * MHZ,\n };\n \n static int mt7623_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, infra_cgs,\n-\t\t\t\t\tARRAY_SIZE(infra_cgs));\n+\t\t\t\t\tARRAY_SIZE(infra_cgs), 1);\n }\n \n static const struct mtk_clk_tree mt7623_clk_peri_tree = {\n@@ -1086,13 +1084,13 @@ static int mt7623_pericfg_probe(struct udevice *dev)\n static int mt7623_hifsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, hif_cgs,\n-\t\t\t\t\tARRAY_SIZE(hif_cgs));\n+\t\t\t\t\tARRAY_SIZE(hif_cgs), 1);\n }\n \n static int mt7623_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, eth_cgs,\n-\t\t\t\t\tARRAY_SIZE(eth_cgs));\n+\t\t\t\t\tARRAY_SIZE(eth_cgs), 1);\n }\n \n static int mt7623_ethsys_hifsys_bind(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c\nindex e4132f6195f..5bbac309e9d 100644\n--- a/drivers/clk/mediatek/clk-mt7629.c\n+++ b/drivers/clk/mediatek/clk-mt7629.c\n@@ -581,7 +581,6 @@ static const struct mtk_clk_tree mt7629_clk_tree = {\n static const struct mtk_clk_tree mt7629_peri_clk_tree = {\n \t.xtal_rate = 40 * MHZ,\n \t.xtal2_rate = 20 * MHZ,\n-\t.gates_offs = CLK_PERI_PWM1_PD,\n \t.fdivs_offs = CLK_TOP_TO_USB3_SYS,\n \t.muxes_offs = CLK_TOP_AXI_SEL,\n \t.plls = apmixed_plls,\n@@ -635,19 +634,19 @@ static int mt7629_topckgen_probe(struct udevice *dev)\n static int mt7629_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs,\n-\t\t\t\t\tARRAY_SIZE(infra_cgs));\n+\t\t\t\t\tARRAY_SIZE(infra_cgs), 0);\n }\n \n static int mt7629_pericfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs,\n-\t\t\t\t\tARRAY_SIZE(peri_cgs));\n+\t\t\t\t\tARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD);\n }\n \n static int mt7629_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs,\n-\t\t\t\t\tARRAY_SIZE(eth_cgs));\n+\t\t\t\t\tARRAY_SIZE(eth_cgs), 0);\n }\n \n static int mt7629_ethsys_bind(struct udevice *dev)\n@@ -666,13 +665,13 @@ static int mt7629_ethsys_bind(struct udevice *dev)\n static int mt7629_sgmiisys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs,\n-\t\t\t\t\tARRAY_SIZE(sgmii_cgs));\n+\t\t\t\t\tARRAY_SIZE(sgmii_cgs), 0);\n }\n \n static int mt7629_ssusbsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs,\n-\t\t\t\t\tARRAY_SIZE(ssusb_cgs));\n+\t\t\t\t\tARRAY_SIZE(ssusb_cgs), 0);\n }\n \n static const struct udevice_id mt7629_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c\nindex c8adbe538d9..73dc5cfe19d 100644\n--- a/drivers/clk/mediatek/clk-mt7981.c\n+++ b/drivers/clk/mediatek/clk-mt7981.c\n@@ -631,7 +631,7 @@ static const struct mtk_gate sgmii0_cgs[] = {\n static int mt7981_sgmii0sys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,\n-\t\t\t\t\tsgmii0_cgs, ARRAY_SIZE(sgmii0_cgs));\n+\t\t\t\t\tsgmii0_cgs, ARRAY_SIZE(sgmii0_cgs), 0);\n }\n \n static const struct udevice_id mt7981_sgmii0sys_compat[] = {\n@@ -658,7 +658,7 @@ static const struct mtk_gate sgmii1_cgs[] = {\n static int mt7981_sgmii1sys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,\n-\t\t\t\t\tsgmii1_cgs, ARRAY_SIZE(sgmii1_cgs));\n+\t\t\t\t\tsgmii1_cgs, ARRAY_SIZE(sgmii1_cgs), 0);\n }\n \n static const struct udevice_id mt7981_sgmii1sys_compat[] = {\n@@ -699,7 +699,7 @@ static const struct mtk_gate eth_cgs[] = {\n static int mt7981_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,\n-\t\t\t\t\teth_cgs, ARRAY_SIZE(eth_cgs));\n+\t\t\t\t\teth_cgs, ARRAY_SIZE(eth_cgs), 0);\n }\n \n static int mt7981_ethsys_bind(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c\nindex d2ac5ad1bb1..04040f5ff63 100644\n--- a/drivers/clk/mediatek/clk-mt7986.c\n+++ b/drivers/clk/mediatek/clk-mt7986.c\n@@ -637,7 +637,7 @@ static const struct mtk_gate eth_cgs[] = {\n static int mt7986_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, eth_cgs,\n-\t\t\t\t\tARRAY_SIZE(eth_cgs));\n+\t\t\t\t\tARRAY_SIZE(eth_cgs), 0);\n }\n \n static int mt7986_ethsys_bind(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c\nindex e0ca82de01e..3a30d16a158 100644\n--- a/drivers/clk/mediatek/clk-mt7987.c\n+++ b/drivers/clk/mediatek/clk-mt7987.c\n@@ -819,7 +819,7 @@ static const struct mtk_gate eth_cgs[] = {\n static int mt7987_ethsys_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs,\n-\t\t\t\t\tARRAY_SIZE(eth_cgs));\n+\t\t\t\t\tARRAY_SIZE(eth_cgs), 0);\n }\n \n static int mt7987_ethsys_bind(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c\nindex 43820557ba7..71a16b9f19f 100644\n--- a/drivers/clk/mediatek/clk-mt7988.c\n+++ b/drivers/clk/mediatek/clk-mt7988.c\n@@ -893,7 +893,7 @@ static int mt7988_ethdma_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,\n \t\t\t\t\tethdma_mtk_gate,\n-\t\t\t\t\tARRAY_SIZE(ethdma_mtk_gate));\n+\t\t\t\t\tARRAY_SIZE(ethdma_mtk_gate), 0);\n }\n \n static int mt7988_ethdma_bind(struct udevice *dev)\n@@ -952,7 +952,7 @@ static int mt7988_sgmiisys_0_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,\n \t\t\t\t\tsgmiisys_0_mtk_gate,\n-\t\t\t\t\tARRAY_SIZE(sgmiisys_0_mtk_gate));\n+\t\t\t\t\tARRAY_SIZE(sgmiisys_0_mtk_gate), 0);\n }\n \n static const struct udevice_id mt7988_sgmiisys_0_compat[] = {\n@@ -997,7 +997,7 @@ static int mt7988_sgmiisys_1_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,\n \t\t\t\t\tsgmiisys_1_mtk_gate,\n-\t\t\t\t\tARRAY_SIZE(sgmiisys_1_mtk_gate));\n+\t\t\t\t\tARRAY_SIZE(sgmiisys_1_mtk_gate), 0);\n }\n \n static const struct udevice_id mt7988_sgmiisys_1_compat[] = {\n@@ -1044,7 +1044,7 @@ static int mt7988_ethwarp_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,\n \t\t\t\t\tethwarp_mtk_gate,\n-\t\t\t\t\tARRAY_SIZE(ethwarp_mtk_gate));\n+\t\t\t\t\tARRAY_SIZE(ethwarp_mtk_gate), 0);\n }\n \n static int mt7988_ethwarp_bind(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c\nindex 5b41cf4b88c..5a353e82f3f 100644\n--- a/drivers/clk/mediatek/clk-mt8183.c\n+++ b/drivers/clk/mediatek/clk-mt8183.c\n@@ -778,7 +778,7 @@ static int mt8183_topckgen_probe(struct udevice *dev)\n static int mt8183_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks,\n-\t\t\t\t\tARRAY_SIZE(infra_clks));\n+\t\t\t\t\tARRAY_SIZE(infra_clks), 0);\n }\n \n static const struct udevice_id mt8183_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex b6332b14aea..02d30ab12d8 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -708,13 +708,14 @@ static int mt8365_topckgen_probe(struct udevice *dev)\n static int mt8365_topckgen_cg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates,\n-\t\t\t\t\tARRAY_SIZE(top_clk_gates));\n+\t\t\t\t\tARRAY_SIZE(top_clk_gates),\n+\t\t\t\t\tCLK_TOP_AUD_I2S0_M);\n }\n \n static int mt8365_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks,\n-\t\t\t\t\tARRAY_SIZE(ifr_clks));\n+\t\t\t\t\tARRAY_SIZE(ifr_clks), 0);\n }\n \n static const struct udevice_id mt8365_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c\nindex d4f6604c160..bad8c62601d 100644\n--- a/drivers/clk/mediatek/clk-mt8512.c\n+++ b/drivers/clk/mediatek/clk-mt8512.c\n@@ -809,13 +809,13 @@ static int mt8512_topckgen_probe(struct udevice *dev)\n static int mt8512_topckgen_cg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks,\n-\t\t\t\t\tARRAY_SIZE(top_clks));\n+\t\t\t\t\tARRAY_SIZE(top_clks), 0);\n }\n \n static int mt8512_infracfg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks,\n-\t\t\t\t\tARRAY_SIZE(infra_clks));\n+\t\t\t\t\tARRAY_SIZE(infra_clks), 0);\n }\n \n static const struct udevice_id mt8512_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c\nindex d5f922886a3..a84a5f360f5 100644\n--- a/drivers/clk/mediatek/clk-mt8516.c\n+++ b/drivers/clk/mediatek/clk-mt8516.c\n@@ -758,7 +758,7 @@ static int mt8516_topckgen_probe(struct udevice *dev)\n static int mt8516_topckgen_cg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks,\n-\t\t\t\t\tARRAY_SIZE(top_clks));\n+\t\t\t\t\tARRAY_SIZE(top_clks), 0);\n }\n \n static const struct udevice_id mt8516_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c\nindex 92730f3f06c..43a06217d33 100644\n--- a/drivers/clk/mediatek/clk-mt8518.c\n+++ b/drivers/clk/mediatek/clk-mt8518.c\n@@ -1514,7 +1514,7 @@ static int mt8518_topckgen_probe(struct udevice *dev)\n static int mt8518_topckgen_cg_probe(struct udevice *dev)\n {\n \treturn mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks,\n-\t\t\t\t\tARRAY_SIZE(top_clks));\n+\t\t\t\t\tARRAY_SIZE(top_clks), 0);\n }\n \n static const struct udevice_id mt8518_apmixed_compat[] = {\ndiff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex a3dd18363f6..6ba2fabfd08 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -1018,8 +1018,8 @@ static const int mtk_clk_gate_of_xlate(struct clk *clk,\n \tif (ret)\n \t\treturn ret;\n \n-\tif (clk->id >= tree->gates_offs &&\n-\t clk->id < tree->gates_offs + priv->num_gates)\n+\tif (clk->id >= priv->gates_offs &&\n+\t clk->id < priv->gates_offs + priv->num_gates)\n \t\treturn 0;\n \n \treturn -ENOENT;\n@@ -1030,10 +1030,10 @@ static int mtk_clk_gate_enable(struct clk *clk)\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_gate *gate;\n \n-\tif (clk->id < priv->tree->gates_offs)\n+\tif (clk->id < priv->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->gates_offs];\n \treturn mtk_gate_enable(priv->base, gate);\n }\n \n@@ -1042,10 +1042,10 @@ static int mtk_clk_gate_disable(struct clk *clk)\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_gate *gate;\n \n-\tif (clk->id < priv->tree->gates_offs)\n+\tif (clk->id < priv->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->gates_offs];\n \treturn mtk_gate_disable(priv->base, gate);\n }\n \n@@ -1055,10 +1055,10 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)\n \tstruct udevice *parent = priv->parent;\n \tconst struct mtk_gate *gate;\n \n-\tif (clk->id < priv->tree->gates_offs)\n+\tif (clk->id < priv->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->gates_offs];\n \t/*\n \t * With requesting a TOPCKGEN parent, make sure the dev parent\n \t * is actually topckgen. This might not be the case for an\n@@ -1094,8 +1094,8 @@ static void mtk_clk_gate_dump(struct udevice *dev)\n \t\tconst struct mtk_gate *gate = &priv->gates[i];\n \n \t\tprintf(\"[GATE%u] DT: %u\", i, gate->id);\n-\t\tmtk_clk_print_mapped_id(gate->id, i + tree->gates_offs, tree->id_offs_map);\n-\t\tmtk_clk_print_rate(dev, i + tree->gates_offs);\n+\t\tmtk_clk_print_mapped_id(gate->id, i + priv->gates_offs, tree->id_offs_map);\n+\t\tmtk_clk_print_rate(dev, i + priv->gates_offs);\n \t\tmtk_clk_print_single_parent(gate->parent, gate->flags);\n \t\tprintf(\"\\n\");\n \t}\n@@ -1196,7 +1196,8 @@ int mtk_common_clk_infrasys_init(struct udevice *dev,\n \n int mtk_common_clk_gate_init(struct udevice *dev,\n \t\t\t const struct mtk_clk_tree *tree,\n-\t\t\t const struct mtk_gate *gates, int num_gates)\n+\t\t\t const struct mtk_gate *gates, int num_gates,\n+\t\t\t int gates_offs)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(dev);\n \tstruct udevice *parent;\n@@ -1218,6 +1219,7 @@ int mtk_common_clk_gate_init(struct udevice *dev,\n \tpriv->tree = tree;\n \tpriv->gates = gates;\n \tpriv->num_gates = num_gates;\n+\tpriv->gates_offs = gates_offs;\n \n \treturn 0;\n }\ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex 915b872ec36..25fd156ac30 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -290,6 +290,7 @@ struct mtk_cg_priv {\n \tconst struct mtk_clk_tree *tree;\n \tconst struct mtk_gate *gates;\n \tint num_gates;\n+\tint gates_offs;\n };\n \n extern const struct clk_ops mtk_clk_apmixedsys_ops;\n@@ -304,6 +305,7 @@ int mtk_common_clk_infrasys_init(struct udevice *dev,\n \t\t\t\t const struct mtk_clk_tree *tree);\n int mtk_common_clk_gate_init(struct udevice *dev,\n \t\t\t const struct mtk_clk_tree *tree,\n-\t\t\t const struct mtk_gate *gates, int num_gates);\n+\t\t\t const struct mtk_gate *gates, int num_gates,\n+\t\t\t int gates_offs);\n \n #endif /* __DRV_CLK_MTK_H */\n", "prefixes": [ "3/9" ] }