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GET /api/1.0/patches/2175808/?format=api
{ "id": 2175808, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175808/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-mt8365-fixes-v1-2-4f8ff0de3268@baylibre.com>", "date": "2025-12-18T23:23:22", "name": "[2/9] clk: mediatek: mt8365: fix missing and out of order clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c848afe66e274cac081ef2bc90729605cb1676db", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-2-4f8ff0de3268@baylibre.com/mbox/", "series": [ { "id": 485931, "url": "http://patchwork.ozlabs.org/api/1.0/series/485931/?format=api", "date": "2025-12-18T23:23:20", "name": "clk: mediatek: mt8365: fix clocks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485931/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175808/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=j9CCDKN9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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17:23:22 -0600", "Subject": "[PATCH 2/9] clk: mediatek: mt8365: fix missing and out of order\n clocks", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-mt8365-fixes-v1-2-4f8ff0de3268@baylibre.com>", "References": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>", "To": "Julien Masson <jmasson@baylibre.com>, Tom Rini <trini@konsulko.com>,\n Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=5826; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=dpq5ZQMwvaanSPvhuQXU7x/uCM0I5mT7tXyPLEZ3+bA=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRIz7wB4wqGkEKAmKi48obT9F07BKFL7PIbmYg\n SL5BciKtdCJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSM+xYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A8bAH/RjIKZn3kQJIwvuGuSGLf6+i8l+hrU0Bf+Ii8LO\n s8pN5MP7TU6CWxhR82d1tSmyEcVR8MZJWlVU8QPcPxR88qrab0uhLUij2sbLWC+Eaf85prq9+B6\n M/LRKyDiXxwlbMhZRpdBkGugn5apGxAGQopsIw2wYTtHtG/AEe8ezw900vSki1HHX+l4iX5Cm4w\n CugH4Df5NMnYM0iQZ4/UZ99pZFBxvo6B5e8bC/wrOgfpd9MlAccyw2Yy5z8OIU4fcZrZi1taNEj\n 314DtGArYZleEq+PPVXOZPnIC07FvardHG94Szyy6YZlSLOH5sfWRYDIrdHtpsbjdJtiNFAvcIR\n Uj7I=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Fri, 19 Dec 2025 00:28:35 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Fix a few missing clocks and even more clocks in the incorrect order.\nSince the clocks are looked up by index, having them out of order or\nskipping an ID will lead to incorrect clocks being used.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8365.c | 32 +++++++++++++++++---------------\n 1 file changed, 17 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex c88545fc7cf..b6332b14aea 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -80,7 +80,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {\n \tFACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)\n \n static const struct mtk_fixed_factor top_divs[] = {\n-\tPLL_FACTOR(CLK_TOP_SYS_26M_D2, \"sys_26m_d2\", CLK_XTAL, 1, 2),\n+\tPLL_FACTOR(CLK_TOP_MFGPLL, \"mfgpll_ck\", CLK_APMIXED_MFGPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_SYSPLL_D2, \"syspll_d2\", CLK_APMIXED_MAINPLL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_SYSPLL1_D2, \"syspll1_d2\", CLK_APMIXED_MAINPLL, 1, 4),\n \tPLL_FACTOR(CLK_TOP_SYSPLL1_D4, \"syspll1_d4\", CLK_APMIXED_MAINPLL, 1, 8),\n@@ -110,7 +110,6 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_UNIVPLL3_D4, \"univpll3_d4\", CLK_APMIXED_UNIVPLL, 1, 20),\n \tPLL_FACTOR(CLK_TOP_MMPLL, \"mmpll_ck\", CLK_APMIXED_MMPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_MMPLL_D2, \"mmpll_d2\", CLK_APMIXED_MMPLL, 1, 2),\n-\tPLL_FACTOR(CLK_TOP_MFGPLL, \"mfgpll_ck\", CLK_APMIXED_MFGPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D2, \"lvdspll_d2\", CLK_APMIXED_LVDSPLL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D4, \"lvdspll_d4\", CLK_APMIXED_LVDSPLL, 1, 4),\n \tPLL_FACTOR(CLK_TOP_LVDSPLL_D8, \"lvdspll_d8\", CLK_APMIXED_LVDSPLL, 1, 8),\n@@ -128,6 +127,7 @@ static const struct mtk_fixed_factor top_divs[] = {\n \tPLL_FACTOR(CLK_TOP_APLL2_D2, \"apll2_d2\", CLK_APMIXED_APLL2, 1, 2),\n \tPLL_FACTOR(CLK_TOP_APLL2_D4, \"apll2_d4\", CLK_APMIXED_APLL2, 1, 4),\n \tPLL_FACTOR(CLK_TOP_APLL2_D8, \"apll2_d8\", CLK_APMIXED_APLL2, 1, 8),\n+\tPLL_FACTOR(CLK_TOP_SYS_26M_D2, \"sys_26m_d2\", CLK_XTAL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL, \"msdcpll_ck\", CLK_APMIXED_MSDCPLL, 1, 1),\n \tPLL_FACTOR(CLK_TOP_MSDCPLL_D2, \"msdcpll_d2\", CLK_APMIXED_MSDCPLL, 1, 2),\n \tPLL_FACTOR(CLK_TOP_DSPPLL, \"dsppll_ck\", CLK_APMIXED_DSPPLL, 1, 1),\n@@ -484,7 +484,7 @@ static const struct mtk_composite top_muxes[] = {\n static const struct mtk_clk_tree mt8365_clk_tree = {\n \t.xtal_rate = 26 * MHZ,\n \t.xtal2_rate = 26 * MHZ,\n-\t.fdivs_offs = CLK_TOP_SYSPLL_D2,\n+\t.fdivs_offs = CLK_TOP_MFGPLL,\n \t.muxes_offs = CLK_TOP_AXI_SEL,\n \t.plls = apmixed_plls,\n \t.fclks = top_fixed_clks,\n@@ -540,16 +540,6 @@ static const struct mtk_gate_regs top2_cg_regs = {\n \t}\n \n static const struct mtk_gate top_clk_gates[] = {\n-\tGATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),\n-\tGATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),\n-\tGATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),\n-\tGATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),\n-\tGATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),\n-\tGATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),\n-\tGATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),\n-\tGATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),\n-\tGATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),\n-\tGATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),\n \tGATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0),\n \tGATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1),\n \tGATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2),\n@@ -559,6 +549,16 @@ static const struct mtk_gate top_clk_gates[] = {\n \tGATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6),\n \tGATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7),\n \tGATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8),\n+\tGATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),\n+\tGATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),\n+\tGATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),\n+\tGATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),\n+\tGATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),\n+\tGATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),\n+\tGATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),\n+\tGATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),\n+\tGATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),\n+\tGATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),\n };\n \n /* infracfg */\n@@ -648,6 +648,7 @@ static const struct mtk_gate ifr_clks[] = {\n \tGATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),\n \tGATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),\n \tGATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),\n+\tGATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11),\n \tGATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),\n \tGATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),\n \tGATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),\n@@ -669,6 +670,7 @@ static const struct mtk_gate ifr_clks[] = {\n \tGATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),\n \tGATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),\n \tGATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),\n+\tGATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16),\n \tGATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),\n \tGATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),\n \tGATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),\n@@ -680,8 +682,8 @@ static const struct mtk_gate ifr_clks[] = {\n \tGATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),\n \t/* IFR6 */\n \tGATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),\n-\tGATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),\n-\tGATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),\n+\tGATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 1),\n+\tGATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 2),\n \tGATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),\n \tGATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),\n \tGATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),\n", "prefixes": [ "2/9" ] }