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GET /api/1.0/patches/2175727/?format=api
{ "id": 2175727, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175727/?format=api", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/1.0/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218200353.301866-4-calebs@linux.ibm.com>", "date": "2025-12-18T20:03:52", "name": "[3/4] ppc/pnv: Add unimplemented quad and core regs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a10f80e2bf97e82688c89ddc62373464aa338272", "submitter": { "id": 90855, "url": "http://patchwork.ozlabs.org/api/1.0/people/90855/?format=api", "name": "Caleb Schlossin", "email": "calebs@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20251218200353.301866-4-calebs@linux.ibm.com/mbox/", "series": [ { "id": 485909, "url": "http://patchwork.ozlabs.org/api/1.0/series/485909/?format=api", "date": "2025-12-18T20:03:52", "name": "Power10 PowerVM bringup fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485909/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175727/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=cBsw5BOo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org 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DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit adds the read/write functionality for few core and\nquad registers.\n\nSigned-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>\nSigned-off-by: Caleb Schlossin <calebs@linux.ibm.com>\n---\n hw/ppc/pnv_core.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 81 insertions(+)", "diff": "diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c\nindex fb2dfc7ba2..84a2fa6364 100644\n--- a/hw/ppc/pnv_core.c\n+++ b/hw/ppc/pnv_core.c\n@@ -184,10 +184,18 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {\n * POWER10 core controls\n */\n \n+#define PNV10_XSCOM_EC_IMA_EVENT_MASK 0x400\n #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412\n #define PNV10_XSCOM_EC_CORE_THREAD_INFO 0x413\n+#define PNV10_XSCOM_EC_CORE_FIRMASK 0x443\n+#define PNV10_XSCOM_EC_CORE_FIRMASK_AND 0x444\n+#define PNV10_XSCOM_EC_CORE_FIRMASK_OR 0x445\n #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449\n #define PNV10_XSCOM_EC_CORE_RAS_STATUS 0x454\n+#define PNV10_XSCOM_EC_SPATTN_OR 0x497\n+#define PNV10_XSCOM_EC_SPATTN_AND 0x498\n+#define PNV10_XSCOM_EC_SPATTN 0x499\n+#define PNV10_XSCOM_EC_SPATTN_MASK 0x49A\n \n static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,\n unsigned int width)\n@@ -223,6 +231,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,\n }\n }\n break;\n+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK:\n+ return 0;\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:\n+ case PNV10_XSCOM_EC_SPATTN_OR:\n+ case PNV10_XSCOM_EC_SPATTN_AND:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: Write only register, ignoring \"\n+ \"xscom read at 0x%08x\\n\", __func__, offset);\n+ break;\n+ case PNV10_XSCOM_EC_SPATTN:\n+ case PNV10_XSCOM_EC_SPATTN_MASK:\n+ return 0;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp read 0x%08x\\n\", __func__,\n offset);\n@@ -283,6 +304,15 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,\n }\n break;\n \n+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:\n+ case PNV10_XSCOM_EC_SPATTN_OR:\n+ case PNV10_XSCOM_EC_SPATTN_AND:\n+ case PNV10_XSCOM_EC_SPATTN:\n+ case PNV10_XSCOM_EC_SPATTN_MASK:\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp write 0x%08x\\n\", __func__,\n offset);\n@@ -568,6 +598,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {\n * POWER10 Quads\n */\n \n+#define P10_XSCOM_EQ3_MODE_REG1 0x1160a\n+#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG 0x11650\n+#define P10_XSCOM_EQ3_HTM_MODE 0x11680\n+#define P10_XSCOM_EQ3_HTM_IMA_PDBAR 0x1168b\n+#define P10_XSCOM_EQ2_MODE_REG1 0x1260a\n+#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG 0x12650\n+#define P10_XSCOM_EQ2_HTM_MODE 0x12680\n+#define P10_XSCOM_EQ2_HTM_IMA_PDBAR 0x1268b\n+#define P10_XSCOM_EQ1_MODE_REG1 0x1460a\n+#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG 0x14650\n+#define P10_XSCOM_EQ1_HTM_MODE 0x14680\n+#define P10_XSCOM_EQ1_HTM_IMA_PDBAR 0x1468b\n+#define P10_XSCOM_EQ0_MODE_REG1 0x1860a\n+#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG 0x18650\n+#define P10_XSCOM_EQ0_HTM_MODE 0x18680\n+#define P10_XSCOM_EQ0_HTM_IMA_PDBAR 0x1868b\n+\n static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,\n unsigned int width)\n {\n@@ -575,6 +622,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,\n uint64_t val = -1;\n \n switch (offset) {\n+ case P10_XSCOM_EQ0_MODE_REG1:\n+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ0_HTM_MODE:\n+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ1_MODE_REG1:\n+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ1_HTM_MODE:\n+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ2_MODE_REG1:\n+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ2_HTM_MODE:\n+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ3_MODE_REG1:\n+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ3_HTM_MODE:\n+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:\n+ return 0;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp read 0x%08x\\n\", __func__,\n offset);\n@@ -589,6 +653,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,\n uint32_t offset = addr >> 3;\n \n switch (offset) {\n+ case P10_XSCOM_EQ0_MODE_REG1:\n+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ0_HTM_MODE:\n+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ1_MODE_REG1:\n+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ1_HTM_MODE:\n+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ2_MODE_REG1:\n+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ2_HTM_MODE:\n+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ3_MODE_REG1:\n+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ3_HTM_MODE:\n+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp write 0x%08x\\n\", __func__,\n offset);\n", "prefixes": [ "3/4" ] }