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GET /api/1.0/patches/2175698/?format=api
{ "id": 2175698, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175698/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218183122.408690-3-sergeev0xef@gmail.com>", "date": "2025-12-18T18:31:17", "name": "[RFC,2/6] target/riscv: Reimplement Smcdeleg/Ssccfg via read_*, write_* methods", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e1e107b74d20e52d366519544c836ed65d64413", "submitter": { "id": 92294, "url": "http://patchwork.ozlabs.org/api/1.0/people/92294/?format=api", "name": "Aleksandr Sergeev", "email": "sergeev0xef@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218183122.408690-3-sergeev0xef@gmail.com/mbox/", "series": [ { "id": 485896, "url": "http://patchwork.ozlabs.org/api/1.0/series/485896/?format=api", "date": "2025-12-18T18:31:20", "name": "More extendable PMU subsystem.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485896/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175698/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=BuLzkFvw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from 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"Subject": "[RFC PATCH 2/6] target/riscv: Reimplement Smcdeleg/Ssccfg via read_*,\n write_* methods", "Date": "Thu, 18 Dec 2025 21:31:17 +0300", "Message-ID": "<20251218183122.408690-3-sergeev0xef@gmail.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218183122.408690-1-sergeev0xef@gmail.com>", "References": "<20251218183122.408690-1-sergeev0xef@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::129;\n envelope-from=sergeev0xef@gmail.com; helo=mail-lf1-x129.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 13:32:41 -0500", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Methods rmw_cd_mhpmcounter(), rmw_cd_mhpmcounterh(),\nrmw_cd_mhpmevent(), rmw_cd_mhpmeventh(), rmw_cd_ctr_cfg(),\nrmw_cd_ctr_cfgh() contain the same code as read_hmpcounter(),\nwrite_mhpmcounter(), etc. To avoid the same logic\nbeing implemented twice, lets re-call methods from one another.\n\nSigned-off-by: Aleksandr Sergeev <sergeev0xef@gmail.com>\nReviewed-by: Alexei Filippov <halip0503@gmail.com>\n---\n target/riscv/csr.c | 80 +++++++++++++---------------------------------\n 1 file changed, 22 insertions(+), 58 deletions(-)", "diff": "diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 8bdbc71160..81475ec9a3 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -1419,9 +1419,9 @@ static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx,\n }\n \n if (!wr_mask && val) {\n- riscv_pmu_read_ctr(env, val, false, ctr_idx);\n+ read_hpmcounter(env, CSR_MCYCLE + ctr_idx, val);\n } else if (wr_mask) {\n- riscv_pmu_write_ctr(env, new_val, ctr_idx);\n+ write_mhpmcounter(env, CSR_MCYCLE + ctr_idx, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1438,9 +1438,9 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,\n }\n \n if (!wr_mask && val) {\n- riscv_pmu_read_ctr(env, val, true, ctr_idx);\n+ read_hpmcounterh(env, CSR_MCYCLEH + ctr_idx, val);\n } else if (wr_mask) {\n- riscv_pmu_write_ctrh(env, new_val, ctr_idx);\n+ write_mhpmcounterh(env, CSR_MCYCLEH + ctr_idx, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1448,31 +1448,18 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,\n return 0;\n }\n \n-static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,\n+static int rmw_cd_mhpmevent(CPURISCVState *env, int ctr_idx,\n target_ulong *val, target_ulong new_val,\n target_ulong wr_mask)\n {\n- uint64_t mhpmevt_val = new_val;\n-\n if (wr_mask != 0 && wr_mask != -1) {\n return -EINVAL;\n }\n \n if (!wr_mask && val) {\n- *val = env->mhpmevent_val[evt_index];\n- if (riscv_cpu_cfg(env)->ext_sscofpmf) {\n- *val &= ~MHPMEVENT_BIT_MINH;\n- }\n+ read_mhpmevent(env, ctr_idx - 3 + CSR_MHPMEVENT3, val);\n } else if (wr_mask) {\n- wr_mask &= ~MHPMEVENT_BIT_MINH;\n- mhpmevt_val = (new_val & wr_mask) |\n- (env->mhpmevent_val[evt_index] & ~wr_mask);\n- if (riscv_cpu_mxl(env) == MXL_RV32) {\n- mhpmevt_val = mhpmevt_val |\n- ((uint64_t)env->mhpmeventh_val[evt_index] << 32);\n- }\n- env->mhpmevent_val[evt_index] = mhpmevt_val;\n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ write_mhpmevent(env, ctr_idx - 3 + CSR_MHPMEVENT3, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1480,29 +1467,18 @@ static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,\n return 0;\n }\n \n-static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index,\n+static int rmw_cd_mhpmeventh(CPURISCVState *env, int ctr_idx,\n target_ulong *val, target_ulong new_val,\n target_ulong wr_mask)\n {\n- uint64_t mhpmevth_val;\n- uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];\n-\n if (wr_mask != 0 && wr_mask != -1) {\n return -EINVAL;\n }\n \n if (!wr_mask && val) {\n- *val = env->mhpmeventh_val[evt_index];\n- if (riscv_cpu_cfg(env)->ext_sscofpmf) {\n- *val &= ~MHPMEVENTH_BIT_MINH;\n- }\n+ read_mhpmeventh(env, ctr_idx - 3 + CSR_MHPMEVENT3H, val);\n } else if (wr_mask) {\n- wr_mask &= ~MHPMEVENTH_BIT_MINH;\n- env->mhpmeventh_val[evt_index] =\n- (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask);\n- mhpmevth_val = env->mhpmeventh_val[evt_index];\n- mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);\n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ write_mhpmeventh(env, ctr_idx - 3 + CSR_MHPMEVENT3H, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1514,21 +1490,18 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,\n target_ulong new_val, target_ulong wr_mask)\n {\n switch (cfg_index) {\n- case 0: /* CYCLECFG */\n+ case HPM_MCYCLE_IDX:\n if (wr_mask) {\n- wr_mask &= ~MCYCLECFG_BIT_MINH;\n- env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask);\n+ write_mcyclecfg(env, CSR_MCYCLE, new_val, 0);\n } else {\n- *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH;\n+ read_mcyclecfg(env, CSR_MCYCLE, val);\n }\n break;\n- case 2: /* INSTRETCFG */\n+ case HPM_MINSTRET_IDX:\n if (wr_mask) {\n- wr_mask &= ~MINSTRETCFG_BIT_MINH;\n- env->minstretcfg = (new_val & wr_mask) |\n- (env->minstretcfg & ~wr_mask);\n+ write_minstretcfg(env, CSR_MINSTRET, new_val, 0);\n } else {\n- *val = env->minstretcfg &= ~MHPMEVENTH_BIT_MINH;\n+ read_minstretcfg(env, CSR_MINSTRET, val);\n }\n break;\n default:\n@@ -1540,28 +1513,19 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,\n static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,\n target_ulong new_val, target_ulong wr_mask)\n {\n-\n- if (riscv_cpu_mxl(env) != MXL_RV32) {\n- return RISCV_EXCP_ILLEGAL_INST;\n- }\n-\n switch (cfg_index) {\n- case 0: /* CYCLECFGH */\n+ case HPM_MCYCLE_IDX:\n if (wr_mask) {\n- wr_mask &= ~MCYCLECFGH_BIT_MINH;\n- env->mcyclecfgh = (new_val & wr_mask) |\n- (env->mcyclecfgh & ~wr_mask);\n+ write_mcyclecfgh(env, CSR_MCYCLEH, new_val, 0);\n } else {\n- *val = env->mcyclecfgh;\n+ read_mcyclecfgh(env, CSR_MCYCLEH, val);\n }\n break;\n- case 2: /* INSTRETCFGH */\n+ case HPM_MINSTRET_IDX:\n if (wr_mask) {\n- wr_mask &= ~MINSTRETCFGH_BIT_MINH;\n- env->minstretcfgh = (new_val & wr_mask) |\n- (env->minstretcfgh & ~wr_mask);\n+ write_minstretcfgh(env, CSR_MINSTRETH, new_val, 0);\n } else {\n- *val = env->minstretcfgh;\n+ read_minstretcfgh(env, CSR_MINSTRETH, val);\n }\n break;\n default:\n", "prefixes": [ "RFC", "2/6" ] }