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GET /api/1.0/patches/2175693/?format=api
{ "id": 2175693, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175693/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218183122.408690-6-sergeev0xef@gmail.com>", "date": "2025-12-18T18:31:20", "name": "[RFC,5/6] target/riscv: Add PMU events implementation for `virt`", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8b27b225736fc432643c65f62ab03c61e5e123ef", "submitter": { "id": 92294, "url": "http://patchwork.ozlabs.org/api/1.0/people/92294/?format=api", "name": "Aleksandr Sergeev", "email": "sergeev0xef@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218183122.408690-6-sergeev0xef@gmail.com/mbox/", "series": [ { "id": 485896, "url": "http://patchwork.ozlabs.org/api/1.0/series/485896/?format=api", "date": "2025-12-18T18:31:20", "name": "More extendable PMU subsystem.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485896/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175693/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=P1Yi1bAA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-lf1-x12e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 13:32:45 -0500", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add PMU events implementation for `virt` machine\naccording to SBI spec.\n\nSigned-off-by: Aleksandr Sergeev <sergeev0xef@gmail.com>\nReviewed-by: Alexei Filippov <halip0503@gmail.com>\n---\n hw/misc/Kconfig | 3 +\n hw/misc/meson.build | 1 +\n hw/misc/virt_pmu.c | 142 +++++++++++++++++++++++++++++++++++++\n hw/riscv/Kconfig | 1 +\n hw/riscv/virt.c | 4 +-\n include/hw/misc/virt_pmu.h | 91 ++++++++++++++++++++++++\n target/riscv/cpu.c | 8 +++\n target/riscv/pmu.c | 53 --------------\n target/riscv/pmu.h | 1 -\n 9 files changed, 248 insertions(+), 56 deletions(-)\n create mode 100644 hw/misc/virt_pmu.c\n create mode 100644 include/hw/misc/virt_pmu.h", "diff": "diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig\nindex fccd735c24..099200f711 100644\n--- a/hw/misc/Kconfig\n+++ b/hw/misc/Kconfig\n@@ -150,6 +150,9 @@ config IOTKIT_SYSINFO\n config PVPANIC_COMMON\n bool\n \n+config VIRT_PMU\n+ bool\n+\n config PVPANIC_PCI\n bool\n default y if PCI_DEVICES\ndiff --git a/hw/misc/meson.build b/hw/misc/meson.build\nindex b1d8d8e5d2..977a3ac620 100644\n--- a/hw/misc/meson.build\n+++ b/hw/misc/meson.build\n@@ -34,6 +34,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))\n system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'))\n system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))\n system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))\n+specific_ss.add(when: 'CONFIG_VIRT_PMU', if_true: files('virt_pmu.c'))\n \n subdir('macio')\n \ndiff --git a/hw/misc/virt_pmu.c b/hw/misc/virt_pmu.c\nnew file mode 100644\nindex 0000000000..afba06de0e\n--- /dev/null\n+++ b/hw/misc/virt_pmu.c\n@@ -0,0 +1,142 @@\n+/*\n+ * RISC-V Virt machine PMU emulation.\n+ *\n+ * Copyright (c) 2025 Syntacore.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/error-report.h\"\n+#include \"target/riscv/cpu.h\"\n+#include \"target/riscv/pmu.h\"\n+#include \"include/hw/misc/virt_pmu.h\"\n+#include \"system/device_tree.h\"\n+\n+#define SBI_CACHE_EVENT_ID_CNT (SBI_PMU_HW_CACHE_NODE - SBI_PMU_HW_CACHE_L1D + 1)\n+#define SBI_CACHE_OP_ID_CNT (SBI_PMU_HW_CACHE_OP_PREFETCH - SBI_PMU_HW_CACHE_OP_READ + 1)\n+#define SBI_EVT_CTR_SIZE (SBI_CACHE_EVENT_ID_CNT * SBI_CACHE_OP_ID_CNT + 3)\n+\n+void riscv_virt_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)\n+{\n+ uint32_t fdt_event_mhpmctr_map[SBI_EVT_CTR_SIZE][3] = {};\n+ uint32_t event_mhpmctr_idx = 0;\n+\n+ uint32_t event_idx_low, event_idx_high;\n+\n+ /* SBI_PMU_HW_CPU_CYCLES */\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][0] = cpu_to_be32(SBI_PMU_HW_CPU_CYCLES);\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][1] = cpu_to_be32(SBI_PMU_HW_CPU_CYCLES);\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][2] = cpu_to_be32(cmask | 1 << 0);\n+ event_mhpmctr_idx++;\n+\n+ /* SBI_PMU_HW_INSTRUCTIONS */\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][0] =\n+ cpu_to_be32(SBI_PMU_HW_INSTRUCTIONS);\n+\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][1] =\n+ cpu_to_be32(SBI_PMU_HW_INSTRUCTIONS);\n+\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][2] = cpu_to_be32(cmask | 1 << 2);\n+ event_mhpmctr_idx++;\n+\n+ /* Other generic type events */\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][0] =\n+ cpu_to_be32(SBI_PMU_HW_CACHE_REFERENCES);\n+\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][1] =\n+ cpu_to_be32(SBI_PMU_HW_REF_CPU_CYCLES);\n+\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][2] = cpu_to_be32(cmask);\n+ event_mhpmctr_idx++;\n+\n+ /* Cache type */\n+ for (uint32_t ev_id = 0; ev_id < SBI_CACHE_EVENT_ID_CNT; ++ev_id) {\n+ for (uint32_t op_id = 0; op_id < SBI_CACHE_OP_ID_CNT; ++op_id) {\n+ event_idx_low = FIELD_DP32(0, SBI_MHPMEVENT_CACHE, OP, op_id);\n+ event_idx_low = FIELD_DP32(event_idx_low, SBI_MHPMEVENT_CACHE, EVENT, ev_id);\n+ event_idx_low = FIELD_DP32(event_idx_low, SBI_MHPMEVENT, TYPE,\n+ RISCV_SBI_EVENT_TYPE_CACHE);\n+ event_idx_low = FIELD_DP32(event_idx_low, SBI_MHPMEVENT_CACHE, RESULT,\n+ SBI_PMU_HW_CACHE_RESULT_ACCESS);\n+\n+ event_idx_high = FIELD_DP32(event_idx_low, SBI_MHPMEVENT_CACHE, RESULT,\n+ SBI_PMU_HW_CACHE_RESULT_MISS);\n+\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][0] = cpu_to_be32(event_idx_low);\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][1] = cpu_to_be32(event_idx_high);\n+ fdt_event_mhpmctr_map[event_mhpmctr_idx][2] = cpu_to_be32(cmask);\n+ event_mhpmctr_idx++;\n+ }\n+ }\n+\n+ g_assert(event_mhpmctr_idx <= SBI_EVT_CTR_SIZE);\n+\n+ /* This a OpenSBI specific DT property documented in OpenSBI docs */\n+ qemu_fdt_setprop(fdt, pmu_name, \"riscv,event-to-mhpmcounters\",\n+ fdt_event_mhpmctr_map,\n+ event_mhpmctr_idx * sizeof(fdt_event_mhpmctr_map[0]));\n+}\n+\n+bool riscv_virt_supported_events(CPURISCVState *env, uint32_t ctr_idx)\n+{\n+ uint32_t sbi_event_type = FIELD_EX32(env->mhpmevent_val[ctr_idx],\n+ SBI_MHPMEVENT, TYPE);\n+ uint32_t sbi_cache_event;\n+ uint32_t sbi_cache_op;\n+ uint32_t sbi_cache_result;\n+\n+ switch (sbi_event_type) {\n+ case RISCV_SBI_EVENT_TYPE_GEN:\n+ return sbi_event_type <= SBI_PMU_HW_REF_CPU_CYCLES;\n+ case RISCV_SBI_EVENT_TYPE_CACHE:\n+ sbi_cache_event = FIELD_EX32(sbi_event_type, SBI_MHPMEVENT_CACHE, EVENT);\n+ sbi_cache_op = FIELD_EX32(sbi_event_type, SBI_MHPMEVENT_CACHE, OP);\n+ sbi_cache_result = FIELD_EX32(sbi_event_type, SBI_MHPMEVENT_CACHE, RESULT);\n+\n+ return sbi_cache_event <= SBI_PMU_HW_CACHE_NODE &&\n+ sbi_cache_op <= SBI_PMU_HW_CACHE_OP_PREFETCH &&\n+ sbi_cache_result <= SBI_PMU_HW_CACHE_RESULT_MISS;\n+ default:\n+ return false;\n+ }\n+}\n+\n+RISCVException riscv_virt_pmu_ctr_read(CPURISCVState *env, uint32_t ctr_idx,\n+ uint64_t *value)\n+{\n+ uint32_t sbi_event_type = FIELD_EX32(env->mhpmevent_val[ctr_idx],\n+ SBI_MHPMEVENT, TYPE);\n+\n+ switch (sbi_event_type) {\n+ /* If we want to handle some events separately */\n+ default:\n+ /* In case we do not want handle it separately */\n+ return riscv_pmu_ctr_read_general(env, ctr_idx, value);\n+ }\n+}\n+\n+RISCVException riscv_virt_pmu_ctr_write(CPURISCVState *env, uint32_t ctr_idx,\n+ uint64_t value)\n+{\n+ uint32_t sbi_event_type = FIELD_EX32(env->mhpmevent_val[ctr_idx],\n+ SBI_MHPMEVENT, TYPE);\n+\n+ switch (sbi_event_type) {\n+ /* If we want to handle some events separately */\n+ default:\n+ /* In case we do not want handle it separately */\n+ return riscv_pmu_ctr_write_general(env, ctr_idx, value);\n+ }\n+}\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex fc9c35bd98..920b65d733 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -49,6 +49,7 @@ config RISCV_VIRT\n imply VIRTIO_VGA\n imply TEST_DEVICES\n imply TPM_TIS_SYSBUS\n+ select VIRT_PMU\n select DEVICE_TREE\n select RISCV_NUMA\n select GOLDFISH_RTC\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex 17909206c7..7b0e6869db 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -30,7 +30,6 @@\n #include \"hw/char/serial-mm.h\"\n #include \"target/riscv/cpu.h\"\n #include \"hw/core/sysbus-fdt.h\"\n-#include \"target/riscv/pmu.h\"\n #include \"hw/riscv/riscv_hart.h\"\n #include \"hw/riscv/iommu.h\"\n #include \"hw/riscv/riscv-iommu-bits.h\"\n@@ -58,6 +57,7 @@\n #include \"qapi/qapi-visit-common.h\"\n #include \"hw/virtio/virtio-iommu.h\"\n #include \"hw/uefi/var-service-api.h\"\n+#include \"hw/misc/virt_pmu.h\"\n \n /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */\n static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)\n@@ -735,7 +735,7 @@ static void create_fdt_pmu(RISCVVirtState *s)\n \n qemu_fdt_add_subnode(ms->fdt, pmu_name);\n qemu_fdt_setprop_string(ms->fdt, pmu_name, \"compatible\", \"riscv,pmu\");\n- riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);\n+ riscv_virt_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);\n }\n \n static void create_fdt_sockets(RISCVVirtState *s,\ndiff --git a/include/hw/misc/virt_pmu.h b/include/hw/misc/virt_pmu.h\nnew file mode 100644\nindex 0000000000..ea9ace5f6a\n--- /dev/null\n+++ b/include/hw/misc/virt_pmu.h\n@@ -0,0 +1,91 @@\n+/*\n+ * RISC-V Virt machine PMU header file.\n+ * Copyright (C) 2025, Syntacore Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n+ * Also add information on how to contact you by electronic and paper mail.\n+ */\n+\n+#ifndef RISCV_VIRT_PMU_H\n+#define RISCV_VIRT_PMU_H\n+\n+#include \"target/riscv/cpu.h\"\n+#include \"qapi/error.h\"\n+\n+typedef enum riscv_sbi_pmu_types {\n+ RISCV_SBI_EVENT_TYPE_GEN = 0x0,\n+ RISCV_SBI_EVENT_TYPE_CACHE = 0x1,\n+ RISCV_SBI_EVENT_TYPE_RAW = 0x2,\n+ RISCV_SBI_EVENT_TYPE_RAW_V2 = 0x3,\n+ RISCV_SBI_EVENT_TYPE_FIRMWARE = 0xf,\n+} riscv_sbi_pmu_types;\n+\n+REG32(SBI_MHPMEVENT, 0x323)\n+ FIELD(SBI_MHPMEVENT, CODE, 0, 16)\n+ FIELD(SBI_MHPMEVENT, TYPE, 16, 4)\n+\n+/* Generic type events */\n+\n+typedef enum riscv_sbi_pmu_hw {\n+ SBI_PMU_HW_NO_EVENT = 0x00000,\n+ SBI_PMU_HW_CPU_CYCLES = 0x00001,\n+ SBI_PMU_HW_INSTRUCTIONS = 0x00002,\n+ SBI_PMU_HW_CACHE_REFERENCES = 0x00003,\n+ SBI_PMU_HW_CACHE_MISSES = 0x00004,\n+ SBI_PMU_HW_BRANCH_INSTRUCTIONS = 0x00005,\n+ SBI_PMU_HW_BRANCH_MISSES = 0x00006,\n+ SBI_PMU_HW_BUS_CYCLES = 0x00007,\n+ SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 0x00008,\n+ SBI_PMU_HW_STALLED_CYCLES_BACKEND = 0x00009,\n+ SBI_PMU_HW_REF_CPU_CYCLES = 0x0000A,\n+} riscv_sbi_pmu_hw;\n+\n+/* Cache type events */\n+\n+typedef enum riscv_sbi_pmu_cache_event {\n+ SBI_PMU_HW_CACHE_L1D = 0x0,\n+ SBI_PMU_HW_CACHE_L1I = 0x1,\n+ SBI_PMU_HW_CACHE_LL = 0x2,\n+ SBI_PMU_HW_CACHE_DTLB = 0x3,\n+ SBI_PMU_HW_CACHE_ITLB = 0x4,\n+ SBI_PMU_HW_CACHE_BPU = 0x5,\n+ SBI_PMU_HW_CACHE_NODE = 0x6,\n+} riscv_sbi_pmu_cache_event;\n+\n+typedef enum riscv_sbi_pmu_cache_op {\n+ SBI_PMU_HW_CACHE_OP_READ = 0,\n+ SBI_PMU_HW_CACHE_OP_WRITE = 1,\n+ SBI_PMU_HW_CACHE_OP_PREFETCH = 2,\n+} riscv_sbi_pmu_cache_op;\n+\n+typedef enum riscv_sbi_pmu_cache_result {\n+ SBI_PMU_HW_CACHE_RESULT_ACCESS = 0,\n+ SBI_PMU_HW_CACHE_RESULT_MISS = 1,\n+} riscv_sbi_pmu_cache_result;\n+\n+REG32(SBI_MHPMEVENT_CACHE, 0x323)\n+ FIELD(SBI_MHPMEVENT_CACHE, RESULT, 0, 1)\n+ FIELD(SBI_MHPMEVENT_CACHE, OP, 1, 2)\n+ FIELD(SBI_MHPMEVENT_CACHE, EVENT, 3, 13)\n+\n+\n+void riscv_virt_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);\n+bool riscv_virt_supported_events(CPURISCVState *env, uint32_t ctr_idx);\n+RISCVException riscv_virt_pmu_ctr_read(CPURISCVState *env, uint32_t ctr_idx,\n+ uint64_t *value);\n+RISCVException riscv_virt_pmu_ctr_write(CPURISCVState *env, uint32_t ctr_idx,\n+ uint64_t value);\n+\n+#endif /* RISCV_VIRT_PMU_H */\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 73d4280d7c..40853d7214 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -37,6 +37,7 @@\n #include \"kvm/kvm_riscv.h\"\n #include \"tcg/tcg-cpu.h\"\n #include \"tcg/tcg.h\"\n+#include \"hw/misc/virt_pmu.h\"\n \n /* RISC-V CPU definitions */\n static const char riscv_single_letter_exts[] = \"IEMAFDQCBPVH\";\n@@ -1125,6 +1126,13 @@ static void riscv_cpu_init(Object *obj)\n cpu->env.vext_ver = VEXT_VERSION_1_00_0;\n cpu->cfg.max_satp_mode = -1;\n \n+#ifndef CONFIG_USER_ONLY\n+ /* Default PMU implementation */\n+ env->pmu_ctr_write = riscv_virt_pmu_ctr_write;\n+ env->pmu_ctr_read = riscv_virt_pmu_ctr_read;\n+ env->pmu_vendor_support = riscv_virt_supported_events;\n+#endif /* CONFIG_USER_ONLY */\n+\n if (mcc->def->profile) {\n mcc->def->profile->enabled = true;\n }\ndiff --git a/target/riscv/pmu.c b/target/riscv/pmu.c\nindex 5109fd14bf..899d5941bb 100644\n--- a/target/riscv/pmu.c\n+++ b/target/riscv/pmu.c\n@@ -23,62 +23,9 @@\n #include \"cpu.h\"\n #include \"pmu.h\"\n #include \"exec/icount.h\"\n-#include \"system/device_tree.h\"\n \n #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */\n \n-/*\n- * To keep it simple, any event can be mapped to any programmable counters in\n- * QEMU. The generic cycle & instruction count events can also be monitored\n- * using programmable counters. In that case, mcycle & minstret must continue\n- * to provide the correct value as well. Heterogeneous PMU per hart is not\n- * supported yet. Thus, number of counters are same across all harts.\n- */\n-void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)\n-{\n- uint32_t fdt_event_ctr_map[15] = {};\n-\n- /*\n- * The event encoding is specified in the SBI specification\n- * Event idx is a 20bits wide number encoded as follows:\n- * event_idx[19:16] = type\n- * event_idx[15:0] = code\n- * The code field in cache events are encoded as follows:\n- * event_idx.code[15:3] = cache_id\n- * event_idx.code[2:1] = op_id\n- * event_idx.code[0:0] = result_id\n- */\n-\n- /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */\n- fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);\n- fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);\n- fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);\n-\n- /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */\n- fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);\n- fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);\n- fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);\n-\n- /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */\n- fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);\n- fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);\n- fdt_event_ctr_map[8] = cpu_to_be32(cmask);\n-\n- /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */\n- fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);\n- fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);\n- fdt_event_ctr_map[11] = cpu_to_be32(cmask);\n-\n- /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */\n- fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);\n- fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);\n- fdt_event_ctr_map[14] = cpu_to_be32(cmask);\n-\n- /* This a OpenSBI specific DT property documented in OpenSBI docs */\n- qemu_fdt_setprop(fdt, pmu_name, \"riscv,event-to-mhpmcounters\",\n- fdt_event_ctr_map, sizeof(fdt_event_ctr_map));\n-}\n-\n static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)\n {\n CPURISCVState *env = &cpu->env;\ndiff --git a/target/riscv/pmu.h b/target/riscv/pmu.h\nindex 283e311b04..e0603b7e33 100644\n--- a/target/riscv/pmu.h\n+++ b/target/riscv/pmu.h\n@@ -26,7 +26,6 @@\n \n void riscv_pmu_timer_cb(void *priv);\n void riscv_pmu_init(RISCVCPU *cpu, Error **errp);\n-void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);\n int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,\n uint32_t ctr_idx);\n uint32_t riscv_pmu_csrno_to_ctr_idx(int csrno);\n", "prefixes": [ "RFC", "5/6" ] }