Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175673/?format=api
{ "id": 2175673, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175673/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218171459.75831-9-claudio.bantaloukas@arm.com>", "date": "2025-12-18T17:14:58", "name": "[v5,8/9] aarch64: add 8-bit floating-point sum of outer products and accumulate", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2b1f4ccc8381f7f931c688b7b86b3dfb13716e6a", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218171459.75831-9-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485887, "url": "http://patchwork.ozlabs.org/api/1.0/series/485887/?format=api", "date": "2025-12-18T17:14:53", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485887/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175673/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=A4mUbAzz;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=A4mUbAzz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=A4mUbAzz;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=A4mUbAzz", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com", "sourceware.org; spf=pass smtp.mailfrom=arm.com", "server2.sourceware.org;\n arc=pass smtp.remote-ip=52.101.83.6" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXHgJ4tS2z1y2F\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 04:27:56 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 939104BA2E07\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 17:27:49 +0000 (GMT)", "from GVXPR05CU001.outbound.protection.outlook.com\n (mail-swedencentralazon11013006.outbound.protection.outlook.com\n [52.101.83.6])\n by sourceware.org (Postfix) with ESMTPS id 56DB64BA2E26\n for <gcc-patches@gcc.gnu.org>; Thu, 18 Dec 2025 17:18:08 +0000 (GMT)", "from DU7PR01CA0046.eurprd01.prod.exchangelabs.com\n (2603:10a6:10:50e::29) by AS2PR08MB8879.eurprd08.prod.outlook.com\n (2603:10a6:20b:5f6::7) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 17:18:03 +0000", "from DU6PEPF00009525.eurprd02.prod.outlook.com\n (2603:10a6:10:50e:cafe::c8) by DU7PR01CA0046.outlook.office365.com\n (2603:10a6:10:50e::29) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.8 via Frontend Transport; Thu,\n 18 Dec 2025 17:18:06 +0000", "from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by\n DU6PEPF00009525.mail.protection.outlook.com (10.167.8.6) with Microsoft SMTP\n Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6 via\n Frontend Transport; Thu, 18 Dec 2025 17:18:02 +0000", "from DB9PR05CA0016.eurprd05.prod.outlook.com (2603:10a6:10:1da::21)\n by DU4PR08MB11215.eurprd08.prod.outlook.com (2603:10a6:10:570::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 17:15:25 +0000", "from DB1PEPF000509F3.eurprd02.prod.outlook.com\n (2603:10a6:10:1da:cafe::1f) by DB9PR05CA0016.outlook.office365.com\n (2603:10a6:10:1da::21) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.8 via Frontend Transport; Thu,\n 18 Dec 2025 17:15:22 +0000", "from nebula.arm.com (172.205.89.229) by\n DB1PEPF000509F3.mail.protection.outlook.com (10.167.242.149) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9434.6 via Frontend Transport; Thu, 18 Dec 2025 17:15:25 +0000", "from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EX03.Arm.com\n (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 17:15:08 +0000", "from e72c20ac6da1.eu-west-1.compute.internal (10.249.56.29) by\n mail.arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29 via Frontend\n Transport; Thu, 18 Dec 2025 17:15:08 +0000" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 939104BA2E07", "OpenDKIM Filter v2.11.0 sourceware.org 56DB64BA2E26" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 56DB64BA2E26", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 56DB64BA2E26", "ARC-Seal": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1766078288; cv=pass;\n b=UPXsjnj/9/bU2Nfhu4HcXjfJSqXFGWOXLzECjjo/WVIgXdd+VYv7YiFAJHvLE+Y65DIq5Le4/5j56WoKYl45Vv8VeTMsf7GNEhM9+sA4h01WQBIFa4KFCfLzMw1FsJguMBAwtiBr02sNT0GKI2HkAkFJejO7lSm2pc0pN3j4bpU=", "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=LOe22mZqtljeG2CYwArbGlYYHVsc91qu1LZcO4iOWo5zl7CCh/z1rlyMyTKYUhSYN8hxL+rwp5h1cXkvY++17tZ4Df3seAmO0DfQHUpJztCYgFjpOk6FLBMtfSPqgkui1nDU72jQE+nWNj6m7/P1PG0W1ylB6zKy4JGV3aOoEAe3t4dCJi0CG7RIKB5F7d+4bJpqMRmVxr+TP1m9mBvUhlxeOAQaL62FFpCrrAJPwi8m6ael67IIw42t/lThd0xqyEN+sVu0914TnOSlNFLCZ1maF+BMc9Xa8a+VnLRR0cqdv7UzlmipG3NIlYDompoqi5w4adb5hFAwDshrFXf59Q==", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=CGyMZuVk0X4/0HnSw8vqSid9V2X6DFQp7d2x1HGWAnPeoBSPYheif4159ChPQSdAWnmCa9NvjzCEG0AiZBtl/reQhQBTbNjsnGv8J84nePUTaBDhamXrWbtKexfrd1bhlMf5TNnsrnzGUHUi8NLnN2jPQn+UbLPNDe7FK9xz+JV4HeVaElT1G4svOIv2i5CET8LgRPjTiotsX5ml51o3MvIFwGnZr9W0DFDwQy+EL9hlOYYPPAnETf6V77bKWHVKR+2FZVeaUGU3Jc7EdYiy3fUcuTvQUvFtMSln/FdK19CLlBZH0AQcXXngqT1S0Xr0RqqPuXEvNPhzcMulGHvx0Q==" ], "ARC-Message-Signature": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766078288; c=relaxed/simple;\n bh=o7eDCo614s7kQhvChyjZkSlBgLZJAmnMyJ4bsWknG+0=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID:\n MIME-Version;\n b=WJflVV9Ya4eCLHXVFi4oFq+cCLNUrWljF/0PUOfRKlBTdexbsHkR5J1MGhsaJqNEaIRwu6fYKF7w5tGMFyqq8Yb3Ix2sNCCJzv4VZatptG6Dh+zoK1sT9yn3NefJvCcYv8qoC5Ry4ScT8eWePoaeWpPJ0VAEJAyhzVJITm1gMik=", "i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=IImtnB1b/b/Eu7ptJO1KFb+tQgeQ5gPbWXRlLSFsIq4=;\n b=Ff8W5SS7e+ypW31ZqU1Q8uj6qCt6+ZVY4iZIC2eAH+mTPU1LGZv2k41ptTSXRZEmQttdxDM1a0hJz00XEPgGL7nm0kjDEumuTVN8eD9DgMWr0BhkK4r7wx5Omzk1g3SD5brLhmEEqBk6298L8xqItXARm9vKvluZukY3+ig3K+b2vE6G5GYp3BRB8qBkHxGTT1/xCi3vUtlK+Dih/nHC1B+1konh9FqBL4+QAq7qEzhK9kuc+lcbrrlM79WHeX21gbpjnUZrtL5W05OaGllMiI9t0zY8PhHNipwKrE01xh8Mr2OuMAHALOxCI+sfnxuyKJt7/35YfGC5JKOMqEXCtA==", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=IImtnB1b/b/Eu7ptJO1KFb+tQgeQ5gPbWXRlLSFsIq4=;\n b=h5r3RzzR3zljmshz8yQQhNvR023+9MJ0x4Z9hdh0Ank2sgl0gk6PPve4ze0KArk7Bx7suFj6ObZuiYQcnVk4QqdtmexbS2ep3uDuJFCjoSdGoGj8C/timXUeEBNNGQ7EdHQjGZkeK+PW6u49UoBROOCLkcdN/7ouS1LC2iW0SnxKC/GO0S7fozeMFExWEdqlDYfvSFFmomXyFVFpBqu4jUePRKxnXdD3HFY3blwqBroMMjuOcThvyNk6A+Axw0/R5OCceGqA6BcyVqtApc09sU5+H6dsHtiWPO5TdMlkdXdqmgXbPn7r1b75KMszumyIUF2sOc8c1i5qLbz4bWCv+A==" ], "ARC-Authentication-Results": [ "i=3; server2.sourceware.org", "i=2; mx.microsoft.com 1; spf=pass (sender ip is\n 4.158.2.129) smtp.rcpttodomain=oss.qualcomm.com smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1\n spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com])", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 172.205.89.229) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=IImtnB1b/b/Eu7ptJO1KFb+tQgeQ5gPbWXRlLSFsIq4=;\n b=A4mUbAzzMbd06n8sEl9LVUGWTCYTTHHJ6UbY3af6b/bUBMDzfoOenvrNpSsGBSRn0eDfdw+HQwPwg+zkYAJepL+/68DXh8c48dqcDceeB4AKLnLDE2mSQGSmN+1ZvdMlaV/tm8Vn6llNrfI2YvFZcIq1GJ8Li5M43mhptZVB3qs=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=IImtnB1b/b/Eu7ptJO1KFb+tQgeQ5gPbWXRlLSFsIq4=;\n b=A4mUbAzzMbd06n8sEl9LVUGWTCYTTHHJ6UbY3af6b/bUBMDzfoOenvrNpSsGBSRn0eDfdw+HQwPwg+zkYAJepL+/68DXh8c48dqcDceeB4AKLnLDE2mSQGSmN+1ZvdMlaV/tm8Vn6llNrfI2YvFZcIq1GJ8Li5M43mhptZVB3qs=" ], "X-MS-Exchange-Authentication-Results": [ "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v5 8/9] aarch64: add 8-bit floating-point sum of outer\n products and accumulate", "Date": "Thu, 18 Dec 2025 17:14:58 +0000", "Message-ID": "<20251218171459.75831-9-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "References": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509F3:EE_|DU4PR08MB11215:EE_|DU6PEPF00009525:EE_|AS2PR08MB8879:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3f64bc24-fe91-4d34-a3be-08de3e596671", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|36860700013|1800799024|82310400026|376014|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n XwyxjZv/4EtJpmwyqOSqwXEwQoWgWPYIj9bcmOT1o9d1vAWAYzBkG2lXXnFlVTWhsye9Gu3WHGyLeWPoNOJw2/blZ2KDpOJXjEV8cV4C6fmaIsHFFRzQ+vAMjSGvtJCsDQyo5J+9THM5d11qaMyGJDf0tDrbqEjlTypHNu3ybURCjcnn8NNWGzbxEajlcfNJJdkfeWisIU83ULfKW1Q7eagntPsN29FO0+Q5xjTWobwUyKzRfv5OSXrgTfdwF2cp3iqrAUQQZ8NEssbGqXu6o3mXgoo2Z9lEGRMVrsn5+EM9IgsX2sl02DyXBNHvB9B7j4DU7yBsFppKfi0i2dUjQc6ts4qMmj9D/3XSt2ZBbfn8/TO2CaIrjZp7ARQQLcmr9tbGKve1f3frO6eZpKkPv7Sa+K9KnEz/XY6YiVQvVxgbM5fCJ8+HaP+C4dudWQ+slWutx5P4kNVXGj2J2nQMiyg+kMewCb43jN7yLzzq5D5NtgFY97a9/HUYWjnpwfRqits2FVzLtw5rjFHd55czBPFbKKrcnpxk1zqQoD8/JsHdQTHqua8V5W8XRoV5fpyxkWdEpdRJwoBULLnFx5CW8xwVtEwOi9XecQfb09OjZQ+LQpS6dUpX5LtOVKciI0NBNOLMHBrX5wKmBvluXk2qqyh0dhzJ3REGhvBWdYsmcxkDRu8kymAEgT4yZHyPnkb/3DkMfw+lfttZlfV3WROxqNKxWkcAwQKTOwJI/ewhwt5YT28Z06GfMRadI23VsK4KXT2sNjMveY3u/g2GiSo7TtDAIYf98o9KIgn5tSyTbPJXJIkmek8d7mwfgCaqCrrpp6aYzcJu7VS9MX5l78ChZVIYB2aQUFvgJl0QFoOmXhSBeh7KGd3GCBVxMdeZ1jib1wZ8KWskBEEWUx43P2ROj8sAyDeQNzrR8vqz8JGrgM+eEW0QfkqhzBzeB6Spu+AtBt9dqgqz3lKOVPPWB4JKnfPvx6oBiiH3kf/n6Cn+dMPoAYUwOocvvJqjqJmylTcNOXN4eHKLSD1q8/285TrbR0TVB22IJS5ROK2Ms6xgVPjAgtK263ZgKE0bFKzgp5UfI9hhjib4uOPqI9LuNuctZoulTN/w517gJ3XDTl8f1q2g+Ih5gUTN0Ldr24IZNzyF+hsTLPtVOnhUAHMZQ42NdN6D4if1fbbrZxxbcHWuwlvlcTnL3kDpryVvv44z23wQl50M5Y6CH+d4ry0qx7PVS3UAS3mqZQX/mhosBq+vA89L8OV0mI1OzeF5rs+wrNMnR2l9gY5/8FI64eggJsPqvWhJlLY55B5S3vZJaHXWE7HvSWVsbBYk3QHZsfrK3iXjdr112c0b5QensgARvSTldqv9SdS4MyeEBh9PzAoG9IcqeLbcs9x8KRC1sBuJAkHzD4mU7QVCi/bc9+Uah4rVjkHlI9QXW62T/y3E4kSiMhY6lQ7QsPwe9/8jUg7+PLfX7xfF/AY69XFFJzvpaWBBtLAjRNjS+JVYztxSwZRYb3oR/LHK21nufavpEyXhECoTap/CVAFy5Jva4chZpZsB7gjBM4ILyI+bs+2Wa32zYWIl3EKJDsBQFRyDAq9fEadL", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; CTRY:IE; LANG:en;\n SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent;\n CAT:NONE;\n SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(13003099007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [ "DU4PR08MB11215", "AS2PR08MB8879" ], "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n DU6PEPF00009525.eurprd02.prod.outlook.com", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id-Prvs": "\n ff0bd27f-4e62-492b-96a3-08de3e590902", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|14060799003|82310400026|1800799024|376014|36860700013|35042699022|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n n4xROgj8NLqBRPFm72j9MhiKe7xPaYvL4RASmDDE889nAA9jpN658G4kGQ02cWe1UNVHk7iAGQ7cabVfDlOj9QsusLBLYEI5jL+OkScolZ4fqWD7iwd21xI1Qlpi9taHFhVTOM5JIxH1ANLJaNT/J5JwBicEqGR2VotkXovH/kZvLEthoMQ6vlBCz0MX49L8mBetpaVwZ0g22vY+q/w8eVwWjKndIaCfO7slm4sa8FxnlVF5Y2guhbHx/Ffe9qyrXwdgAe7CTc/1tIx98uEki18nbTTySQNJAwRLg1ZHWYW9ey5rqKojS/veC+OvefJ2cGq0y36Ck4WjatCYFI97gSxYFf3Ff6qh0AvMjBpwKM1iBNzyGc/wLwWLqOvXahhf7jDfWOCE++S6TFqKy5P15aco4f9n51TW3c6+ZXvNHUESBg+fjPpjfmkSvpMX3WC1jVKD4wYkQld3XWaMDm+nfOQ9TsanqlueaoSXiR4kY7V0ZOibnSxzwOKn+HAfGZ1ro4DJ1381+RdRmOr/LfoCl1o7fxGGo/VwsEK7lc1bQlc6GSCUyx6SSd9+RwcFqfjakxnnl3/IOBPomo2S3ulI6DkVYAsZ+mylZf7WN0kZgKam3SatXBjk92PeuTtxeWuOLGQFRphLbqYtmhW9jx83kdnrmDvbmEEFWd3HI6ZvMkpDYMesrsd62indesvoPoaXjlFXh/f5kVxK3r8YpaTCElal+ya9HpmJQ9lD04idan72zmxnPN9nHn47iZaSBr+gBVfgTM07/G+7KkkkSIkfidW1xzEmj1LSruQgzcJwJZFyilXBbKswSer/OdPSUO9H1rmLogSrNlDLiklGcgBzzGsphYozuGAMl6UXEl78NJl6Fif6pkd0jLj02grM57vDPnNNnnG5lAtIIioiIh67A2iioiFr2yeFaJMitUIYxCKK0TCg5rN5TPLoeXXWUPNHi3WXgZa0MCbRWawd3KuB11Xqsk7mJpBQxq3N3UT7Tdafy5UWWxSZ/hhEh9crwIVsQG1bVqgkXsgs7y6Qbg1fG3w0w8evOCVkTKU0I/7bxCCPLZmCvi+fzc4BoVu45S/JINgaVZiS7EmajO8fxRGYADo+EBmqcd0a3jxFjZ1zQPrQpbY6nXQYoWsuJ3IRMj8KHeX18bqGPSGe50tl3KnuPU5MNdY3L7+dN62HZgAZNwPASO1VS/GKcyYm00BoxtOHHVRRYvpZSwH5cw++zQVHG/vSFbBQFWqhfONiA2gKm0qnbQYjzwMe8Xwm0K6dVgh6CITpgmazfeVPn6lMmnu17OVfmN7RSxMaCDuQSPQ12GDCQXTgALutjcczWWCKtvkzwqicjUMEd7xfxKPBFvX7d1fGaUy4GERB0shGKkK4fDpt6P7U2xHgqlRB8KSfvnnDAbS3mbuKhMiL0dB4pw9aGs2I1aA7hqF6v8gXjSRKHR5xz2vZehkqz8xjaDYxx0DOCjjlgr5YJqVu2Hn6u2eokSluImFlZ+eE/oPDAOZD2KB9WTaCqS+TGDSARFdKrDzVBAdo0rxi3ympR5uanJmF86OdQ9PJ3X5jasZvZ01Jd2JYKaOmBsRuACapJRLioqF6", "X-Forefront-Antispam-Report": "CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(14060799003)(82310400026)(1800799024)(376014)(36860700013)(35042699022)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 17:18:02.3841 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3f64bc24-fe91-4d34-a3be-08de3e596671", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU6PEPF00009525.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for FMOPA (widening, 2-way, FP8 to FP16) when\nsme-f8f16 is enabled using svmopa_za16[_mf8]_m_fpm and for FMOPA (widening,\n4-way) when sme-f8f32 is enabled using svmopa_za32[_mf8]_m_fpm.\n\nAsm tests for the new intrinsics are added, similar to those for existing\nmopa_z16 intrinsics. Tests for the binary_za_m shape are added.\n\ngcc:\n\t* config/aarch64/aarch64-sme.md\n\t(@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>): Add\n\tnew define_insn.\n\t* config/aarch64/aarch64-sve-builtins-shapes.cc\n\t(struct binary_za_m_base): Support fpm argument.\n\t* config/aarch64/aarch64-sve-builtins-sme.cc (svmopa_za): Extend for\n\tfp8.\n\t* config/aarch64/aarch64-sve-builtins-sme.def (svmopa): Add new\n\tDEF_SME_ZA_FUNCTION_GS_FPM entries.\n\ngcc/testsuite:\n\n\t* gcc.target/aarch64/sme/acle-asm/test_sme_acle.h: (TEST_UNIFORM_ZA):\n\tAdd fpm0 parameter.\n\t* gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c: Add tests for\n\tvariants accepting fpm.\n\t* gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c: Likewise.\n---\n gcc/config/aarch64/aarch64-sme.md | 20 +++++++++++\n .../aarch64/aarch64-sve-builtins-shapes.cc | 2 +-\n .../aarch64/aarch64-sve-builtins-sme.cc | 2 +-\n .../aarch64/aarch64-sve-builtins-sme.def | 2 ++\n gcc/config/aarch64/aarch64-sve2.md | 2 +-\n .../aarch64/sme/acle-asm/test_sme_acle.h | 2 +-\n .../aarch64/sme2/acle-asm/mopa_za16_mf8.c | 36 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/mopa_za32_mf8.c | 36 +++++++++++++++++++\n .../sve/acle/general-c/binary_za_m_1.c | 14 ++++++++\n 9 files changed, 112 insertions(+), 4 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md\nindex e8301ae72a7..0e1cdafb6dc 100644\n--- a/gcc/config/aarch64/aarch64-sme.md\n+++ b/gcc/config/aarch64/aarch64-sme.md\n@@ -2378,6 +2378,8 @@ (define_insn \"*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x124:mode>\"\n ;; - BFMOPS (SME_B16B16)\n ;; - FMOPA\n ;; - FMOPS\n+;; - FMOPA (SME_F8F16)\n+;; - FMOPA (SME_F8F32)\n ;; -------------------------------------------------------------------------\n \n (define_insn \"@aarch64_sme_<optab><mode><mode>\"\n@@ -2410,6 +2412,24 @@ (define_insn \"@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>\"\n \"<b><optab>\\tza%0.<VNx4SI_ONLY:Vetype>, %1/m, %2/m, %3.<SVE_FULL_HF:Vetype>, %4.<SVE_FULL_HF:Vetype>\"\n )\n \n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:DI 0 \"const_int_operand\")\n+\t (match_operand:<SME_ZA_F8F16_32:VPRED> 1 \"register_operand\" \"Upl\")\n+\t (match_operand:<SME_ZA_F8F16_32:VPRED> 2 \"register_operand\" \"Upl\")\n+\t (match_operand:VNx16QI_ONLY 3 \"register_operand\" \"w\")\n+\t (match_operand:VNx16QI_ONLY 4 \"register_operand\" \"w\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP_MOP))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza%0.<SME_ZA_F8F16_32:Vetype>, %1/m, %2/m, %3.b, %4.b\"\n+)\n+\n ;; =========================================================================\n ;; == Table lookup\n ;; =========================================================================\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\nindex 59f313d08f2..ea4be3733c2 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n@@ -692,7 +692,7 @@ struct binary_za_m_base : public overloaded_base<1>\n resolve (function_resolver &r) const override\n {\n type_suffix_index type;\n- if (!r.check_num_arguments (5)\n+ if (!r.check_num_arguments (r.fpm_mode == FPM_set ? 6: 5)\n \t|| !r.require_integer_immediate (0)\n \t|| !r.require_vector_type (1, VECTOR_TYPE_svbool_t)\n \t|| !r.require_vector_type (2, VECTOR_TYPE_svbool_t)\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\nindex 43ef05c673a..20a6ebc4059 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n@@ -651,7 +651,7 @@ FUNCTION (svmls_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SMLS,\n \t\t\t\t\t\t UNSPEC_SME_UMLS,\n \t\t\t\t\t\t UNSPEC_SME_FMLS))\n FUNCTION (svmopa_za, sme_2mode_function, (UNSPEC_SME_SMOPA, UNSPEC_SME_UMOPA,\n-\t\t\t\t\t UNSPEC_SME_FMOPA))\n+\t\t\t\t\t UNSPEC_SME_FMOPA, UNSPEC_SME_FMOPA))\n FUNCTION (svmops_za, sme_2mode_function, (UNSPEC_SME_SMOPS, UNSPEC_SME_UMOPS,\n \t\t\t\t\t UNSPEC_SME_FMOPS))\n FUNCTION (svread_za, svread_za_impl,)\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\nindex f9ad6837f44..6306ee33a14 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n@@ -270,6 +270,7 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_h_mf8,\n \t\t\t vg2, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg2, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_h_mf8, none, za_m, set)\n #undef REQUIRED_EXTENSIONS\n \n #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n@@ -277,6 +278,7 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_s_mf8,\n \t\t\t vg4, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg4, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_s_mf8, none, za_m, set)\n #undef REQUIRED_EXTENSIONS\n \n #undef DEF_SME_ZA_FUNCTION\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex 11cc53bbb50..407f1698c41 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3666,7 +3666,7 @@ (define_insn \"@aarch64_sve2_fp8_cvtn<mode>\"\n \t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n \t (reg:DI FPM_REGNUM)]\n \t UNSPEC_FP8FCVTN))]\n- \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_STREAMING_SME2\"\n+ \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_SSVE_FP8\"\n \"<b>fcvtn\\t%0.b, %1\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\nindex aaadab2f773..75e3413768e 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\n@@ -46,7 +46,7 @@\n \n #define TEST_UNIFORM_ZA(NAME, TYPE, CODE1, CODE2)\t\t\\\n PROTO (NAME, void, (TYPE z0, TYPE z1, svbool_t p0,\t\t\\\n-\t\t svbool_t p1))\t\t\t\t\\\n+\t\t svbool_t p1, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n INVOKE (CODE1, CODE2);\t\t\t\t\t\\\n }\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\nnew file mode 100644\nindex 00000000000..e88b7a4814c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\n@@ -0,0 +1,36 @@\n+/* { dg-do assemble { target aarch64_asm_sme-f8f16_ok } } */\n+/* { dg-do compile { target { ! aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+sme-f8f16\"\n+/*\n+** mopa_za16_mf8_0_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.h, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_0_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (0, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za16_m_fpm (0, p0, p1, z0, z1, fpm0))\n+\n+/*\n+** mopa_za16_mf8_0_p1_p0_z1_z0:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.h, p1/m, p0/m, z1\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_0_p1_p0_z1_z0, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (0, p1, p0, z1, z0, fpm0),\n+\t\t svmopa_za16_m_fpm (0, p1, p0, z1, z0, fpm0))\n+\n+/*\n+** mopa_za16_mf8_1_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza1\\.h, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_1_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (1, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za16_m_fpm (1, p0, p1, z0, z1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c\nnew file mode 100644\nindex 00000000000..74a665fea6b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c\n@@ -0,0 +1,36 @@\n+/* { dg-do assemble { target aarch64_asm_sme-f8f32_ok } } */\n+/* { dg-do compile { target { ! aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+sme-f8f32\"\n+/*\n+** mopa_za32_mf8_0_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.s, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_0_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (0, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za32_m_fpm (0, p0, p1, z0, z1, fpm0))\n+\n+/*\n+** mopa_za32_mf8_0_p1_p0_z1_z0:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.s, p1/m, p0/m, z1\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_0_p1_p0_z1_z0, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (0, p1, p0, z1, z0, fpm0),\n+\t\t svmopa_za32_m_fpm (0, p1, p0, z1, z0, fpm0))\n+\n+/*\n+** mopa_za32_mf8_1_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza1\\.s, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_1_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (1, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za32_m_fpm (1, p0, p1, z0, z1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\nindex 44c3e48e916..5f013bd4194 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\n@@ -46,3 +46,17 @@ f4 (svbool_t pg, svint16_t s16) __arm_streaming __arm_inout(\"za\")\n svmopa_za64_m (-1, pg, pg, s16, s16); /* { dg-error {passing -1 to argument 1 of 'svmopa_za64_m', which expects a value in the range \\[0, 7\\]} } */\n svmopa_za64_m (8, pg, pg, s16, s16); /* { dg-error {passing 8 to argument 1 of 'svmopa_za64_m', which expects a value in the range \\[0, 7\\]} } */\n }\n+\n+#pragma GCC target (\"arch=armv9-a+sme-f8f16+sme-f8f32\")\n+\n+void\n+f5 (svbool_t pg, svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout(\"za\")\n+{\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8); /* { dg-error {too few arguments to function 'svmopa_za16_mf8_m_fpm'} } */\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8, fpm);\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8, fpm, fpm); /* { dg-error {too many arguments to function 'svmopa_za16_mf8_m_fpm'; expected 6, have 7} } */\n+\n+ svmopa_za16_mf8_m_fpm(-1, pg, pg, mf8, mf8, fpm); /* { dg-error {passing -1 to argument 1 of 'svmopa_za16_mf8_m_fpm', which expects a value in the range \\[0, 1\\]} } */\n+ svmopa_za16_mf8_m_fpm(2, pg, pg, mf8, mf8, fpm); /* { dg-error {passing 2 to argument 1 of 'svmopa_za16_mf8_m_fpm', which expects a value in the range \\[0, 1\\]} } */\n+ svmopa_za32_mf8_m_fpm(4, pg, pg, mf8, mf8, fpm); /* { dg-error {passing 4 to argument 1 of 'svmopa_za32_mf8_m_fpm', which expects a value in the range \\[0, 3\\]} } */\n+}\n", "prefixes": [ "v5", "8/9" ] }