Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175665/?format=api
{ "id": 2175665, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175665/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218171459.75831-5-claudio.bantaloukas@arm.com>", "date": "2025-12-18T17:14:54", "name": "[v5,4/9] aarch64: add narrowing sme2 conversions to fp8", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "01043d620c529f1f055c13c2c037b10f46410070", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218171459.75831-5-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485887, "url": "http://patchwork.ozlabs.org/api/1.0/series/485887/?format=api", "date": "2025-12-18T17:14:53", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485887/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175665/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=PVPX61GR;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=PVPX61GR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=PVPX61GR;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=PVPX61GR", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com", "sourceware.org; spf=pass smtp.mailfrom=arm.com", "server2.sourceware.org;\n arc=pass smtp.remote-ip=40.107.130.25" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXHWz6Mzlz1y2f\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 04:21:35 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id D65594BA23E2\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 17:21:33 +0000 (GMT)", "from MRWPR03CU001.outbound.protection.outlook.com\n (mail-francesouthazon11011025.outbound.protection.outlook.com\n [40.107.130.25])\n by sourceware.org (Postfix) with ESMTPS id 4ADE04BA2E05\n for <gcc-patches@gcc.gnu.org>; Thu, 18 Dec 2025 17:18:28 +0000 (GMT)", "from AM8P191CA0013.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:21a::18)\n by DBAPR08MB5558.eurprd08.prod.outlook.com (2603:10a6:10:1b3::19)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.8; Thu, 18 Dec\n 2025 17:18:22 +0000", "from AMS0EPF000001B7.eurprd05.prod.outlook.com\n (2603:10a6:20b:21a:cafe::d) by AM8P191CA0013.outlook.office365.com\n (2603:10a6:20b:21a::18) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6 via Frontend Transport; Thu,\n 18 Dec 2025 17:18:21 +0000", "from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by\n AMS0EPF000001B7.mail.protection.outlook.com (10.167.16.171) with Microsoft\n SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6\n via Frontend Transport; Thu, 18 Dec 2025 17:18:20 +0000", "from DB3PR06CA0015.eurprd06.prod.outlook.com (2603:10a6:8:1::28) by\n AS4PR08MB7878.eurprd08.prod.outlook.com (2603:10a6:20b:51d::8) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9434.6; Thu, 18 Dec 2025 17:15:27 +0000", "from DB3PEPF0000885E.eurprd02.prod.outlook.com\n (2603:10a6:8:1:cafe::78) by DB3PR06CA0015.outlook.office365.com\n (2603:10a6:8:1::28) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.7 via Frontend Transport; Thu,\n 18 Dec 2025 17:15:29 +0000", "from nebula.arm.com (172.205.89.229) by\n DB3PEPF0000885E.mail.protection.outlook.com (10.167.242.9) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9434.6 via Frontend Transport; Thu, 18 Dec 2025 17:15:27 +0000", "from AZ-NEU-EXJ02.Arm.com (10.240.25.139) by AZ-NEU-EX03.Arm.com\n (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 17:15:08 +0000", "from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EXJ02.Arm.com\n (10.240.25.139) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 17:15:07 +0000", "from e72c20ac6da1.eu-west-1.compute.internal (10.249.56.29) by\n mail.arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29 via Frontend\n Transport; Thu, 18 Dec 2025 17:15:07 +0000" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org D65594BA23E2", "OpenDKIM Filter v2.11.0 sourceware.org 4ADE04BA2E05" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 4ADE04BA2E05", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 4ADE04BA2E05", "ARC-Seal": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1766078308; cv=pass;\n b=MK6R1N077VN16KwNHsm4BFxOHp/jsUNCzWeIST3ckplfYTQAcOil/rHHuyPjYZ5wI0o3zPOApq0FptElcTECUhVelkJXn7JW0oUQ+fMiLaqlHlhAa7A6Qh1ikvy1re7N3hhSqIhHbKp4kUEAQP1m1O4RefoA46unMnzbWU51kR8=", "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=fwyNzMyzVmdE+SG0INhqZKK1IPuj9a1glh8BAZN+uyz5BwT27SJYjUWfEOuLwoW/0nDfqTSNU8YQJ6DI+3umpI0pzSSPkiihG1UUmD2A6tKGiTneIOadxy5+UGAKckKXzU+/eJEpCSmlL29d1AT3w+8fMJmpXobG9YhKXjlzP3rX6xADkdeLl25o1wRKCL5t9nNPLG45mddJQ8AmIPr+GZIwEJyap0/gw4dfj1Xjy1s8VbcKC7GK/YQ4nt+VOa7YQ3CSqnNH14WPC1ZrOOIfOqNOvpg4/xZDnp0pg7NXAN22EgFdyFm1JXkW/L7I80N0/5iMFXqUPVZPixqgmh9UIQ==", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=mcfFsefkqrnCh22dOvKcJN9Tg1xPpWcat+mQnGlJMuoOZVkZInEfAQew6hY3dWyqg4VcP5AkVwkF5yOV13E2xObqWZgVGCiLXNZ97BB/Y8y5+2DTGcoRhE3wVc1QrV1+nhGLHINzb/NPsM/2/RVln7/nAjqaqJgJq0I8auN3AdvHxx//y8X7OLbgrrgQeA9Rotk1rNQUFEfnIpWBlPJpBIBSRPBvBhYcZ/J82xd/yet3TDSCiDEmBuRalFfUSMtrV4azYZU7x8OPQlD/J8E5rBe2KIdWtB7Oyteh+IvLGjI5T4IR9/U5BTL1//D4ALzDyiLkaq5pE9AKRoDQ164LYQ==" ], "ARC-Message-Signature": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766078308; c=relaxed/simple;\n bh=Zi/0O+q50Ntw426QemAFCONgY0HuSgmqfn+La8ZmajY=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID:\n MIME-Version;\n b=cpYmv0cBncOYD7lqFq12DQovwpHT0EnPxqFEQnue6YGd6AxE6wg+ine27M2ckU0sRdNU7LXLaYWpy7COp5and5Xoe0V+j2iF22+WYnxp7RnHWFflnB47DEkakMOw5+kuBE/wREDcljCKagTLx5gV2qkOZfprj51wZLXDbN3M4f8=", "i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=DR0YD4wUu4CdZjjoaWvoxdXwCJ2RY78tZazAzCjfycnvzUQBoi1Ye54dTbahcsjErSPIrRzJIrAE6Mxs+BrSYk4HByyStZlM+EBcSw6/GLT8Ma+QPyZjEMNhBerbMCO6erc0kUjBJlX43dAV09WSTYkXrx7PDpgClH9TraCZJ8Rv2xWTZICL7O3P8M39/RJ7o5R3/DQ0+yjXY7NamN3S9Rt5h1MjIFBGyzVBvQRyFcRwkYn2lF09s8N5T1NYuTMTDDsI09dpEip6VJ6OkD8kgQPlY0JfbH6LWT/5WK5E4Nz2+h7FKhzwqhuSMSAeQul5TO5t/XOEuiGiGBy1mzUxWg==", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=bEtLEqSXByo2tHE6BwmpMmtOsrCQ3/5lNhNSyDW3oDhiV1YMJNxdjM0COMpY50i9ilwUf1tgLGr3Tzoc69Dy2Lkr0anniunEY5NBSiPAF2XVvDoa5r+sD5ztYNao+Aww2Rc6EGD2dYItevI8ci9IAEJKhMHnHTmke1kYZ9LHwIf3Eag7rsFJ44FjVg/nures8cTYXZ7McxN6zyNiG1GcCftyyaG4QeyOIb8ERKxU+GrOJ8OJFa7YNrHXSNichtGleYoK/7l14OCvAUEtDNMpNsgRceDQogqOfUKt3vBGVAMfX1sIcUsDm8e4g+DRb3NN7oVzebQJ2FYdiI412U5jzw==" ], "ARC-Authentication-Results": [ "i=3; server2.sourceware.org", "i=2; mx.microsoft.com 1; spf=pass (sender ip is\n 4.158.2.129) smtp.rcpttodomain=oss.qualcomm.com smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1\n spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com])", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 172.205.89.229) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=PVPX61GRijDIRKk8N8CyHKF9Flvh/CiPLrLHQqsD6d2kgEqfOtHQX1MNOKBqixYpqVKef8LoPRSngwllwtTFzxf+UA7wfmUw57QuvhlSNLkdvMppc/NvF10MoLw/EfMUypMfGvnFBoxHgxkkJgxgs5DETPequF5N1YuP0vNQsZM=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=PVPX61GRijDIRKk8N8CyHKF9Flvh/CiPLrLHQqsD6d2kgEqfOtHQX1MNOKBqixYpqVKef8LoPRSngwllwtTFzxf+UA7wfmUw57QuvhlSNLkdvMppc/NvF10MoLw/EfMUypMfGvnFBoxHgxkkJgxgs5DETPequF5N1YuP0vNQsZM=" ], "X-MS-Exchange-Authentication-Results": [ "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v5 4/9] aarch64: add narrowing sme2 conversions to fp8", "Date": "Thu, 18 Dec 2025 17:14:54 +0000", "Message-ID": "<20251218171459.75831-5-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "References": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB3PEPF0000885E:EE_|AS4PR08MB7878:EE_|AMS0EPF000001B7:EE_|DBAPR08MB5558:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a6aa4dcc-aa02-4e09-192b-08de3e597125", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|1800799024|36860700013|376014|82310400026|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n 2DDxonFA7Aclyjo1UO3s7aC0HRKoZLnAhtiZKIgLkteAN1uaIxA8ExBfWADWSVbzdcspUMnz5yFKz1y99MOHcZo3cTFYGcAWYc8idJD3WPUVJEfJX9pH+BOT4AurZujIqZCG6ImygeoWhToDBm7xyo9O64EefaVYX9agdqf+Hp/+ScIMJwZQKlGjGAFe5HojIQJLy2p1BGs32butnezp0Z4A6ic2kEtHSmDSdzUFtbOwYBBBT911D+QS083kHZ7pZ3naf2QbI9+86BQvW9QjbzwRyzIYTA9P5LDQJcI74L+2X2wUZuMW4ArKEK4Q/lm8edVyBrexiGCQvwD7pfY2Mx8fJg4SzxH93YBAdvGbzS1Y4IDdBOH/4Svvac7qSH3yY94kZf0DaQNN5rxO9DCKPAq7CwXQMMKsmTEsjoYfvghsMFfH27WRB1YqFnBveF33i18iklqUkvluzFV9JNIyCpg+EJuASGi5ZnWIUOs0nvYGtvwY7N8rtphv723f5xX5qaKEfHyYBP5hIh4KYbm5p3A3uRsP4jq+xpdpRZZT9uqmtWCn/hZQRoC+L8qqafDaIy5wf2AP18052OkazxeH5qQH6JvOs1NLyjYOPbV4zbteV5nGWEY+Qn3Gy/uKjTDPlwMZtnfUZJRuixsL/ljqjQarI415n50Yn41uzeqwP9IUdLYzxv/p9mQPSH2xXiW1+slixKNhbHI9fkIV4T+eIxgSSzudqG55FSYtKT/QMYA27Y1u0O7UAIkYbEjlERuV0Qc/DhaWRFTjdFa59JXuAQ8oCDJ+OCbgPTlPU5SqTq6ut7apxlLrDIKQZRu6ufMekjByLIDcjIRQR89VFgXa7n2WqMnVW2uge/w+puWRrLy/c1PJJK70CBxhtvmAckgJByLMYJ7oQVUW8fXVyTH+RL3K3o1vLW+7tqZYtJwGh8ipW9HimlWJhHfGS962fmo4SklH3nST9h/blwAPSao18B+xnGnYBxM2bzvd57hf+yRyA+t47sIVjlOYWcg8iEBJ2JMeLj/YHVcB4IkKmsM27mAaokrzA/7XQHZY3JXZHpCjUCQUsLPUSTAWwFa9tQ0GcAB3GCgL/ShFGTVKXc7o7i9f0LeXwSprmj/f1UQBb+1pj2T/uL8KwloPqx1cnkEir6uY5GHEV3cGTmXUHSnOxrwb30tikjtRgmq/by3FJTb//d9GmW+LI2jwgVdjGh2OnU1W/JWG4BsbvgCCZbafXdGJuhRUpu8jO6wH1kfzdlzjW8VNwbX4V1t6eL05vCJBu+p0zUx697Bc/lw6H9qnAJ+u1EeVG9uym0mO/AI6mUdk/75YG1aKSukPMlojTsXfSh9I9PkzBv5aexSbGwL8JCvSW0B70ksAntFh/QHmJXtDgmGLlHsIWfbcngnIEBOEmIWYZ3CWkd6w8TAfh++V/pjoMrAkWFQj4CAj36HtA/trpmYGsNjyXOPmjHAjmQuautLiRE3OUmME047gzc2cyhJljLphQcTI168+AD/JpNvVzNHwhNgMXgeAT3pf3rDvbJCfM5F+fmg+uoGEaMpabs+JKEGx9sP3H+8B7w4H5vR5M1R3xFvDXS3odxUSZfUK", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; CTRY:IE; LANG:en;\n SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent;\n CAT:NONE;\n SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(13003099007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [ "AS4PR08MB7878", "DBAPR08MB5558" ], "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n AMS0EPF000001B7.eurprd05.prod.outlook.com", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id-Prvs": "\n 16e74d73-e853-43a6-8e6b-08de3e590a14", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|35042699022|14060799003|82310400026|1800799024|36860700013|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n zOkxtkB0zt/HWrNzB3kJTvWA1pz8Ai1HU/apaUaWwi6ybF1ABAXxWAfgXFXG/7xD189R06S7Ex5lkgzae/DTwPmoOMnU4ZPDbGWTavEPUhZR7R7GcWj3tputcX/qzHi5wU0rrI0eIURZIcK8IV+NHq3Bf018MoDLFj8Co4OU7kYO1vNmD/UmtfE9006pRDFOhUdAozvFP+JPELdceZXquYAzt4tEEqk19XOM9v8Bk1zvPoOkR1ZDZ3tdvpeiOEB2NEibtA1SlUs3BqYWuRHibEYPQg/OrYF34czq92BCNzdW8arXtcWb8a78q3gBz8XGDUeH1obly9EwNJmymSzd8XyUHyIp7tFJY2crlVw2nNefrLsh3UHV017uT72Oz/yrFvr3njQhmsooWasr/j8Rxmt2k5tOdCjc1FWAAYFIs3mGs9vlfQUUDf4iET9ju0r/IIrjKrofJQEjNmAk9nkMz+HBz3+J5dgZCeFofM5uiJOZJ18y49BZSU7rktpH4e//5DEWj9TZanb6nrWjB8IqNObUSD6Ubx0y7xTDKCObc9+VXskNjrs9pya0wTW1LmMM+a4Zri7xWp58h24OdKG3QDlcMx8i5p7oGEZp7JYSvlQxUHluLQZSg/j/4GIWbwmAgsILWZldaQr9MTPcG+qHE4NiXJP0Vpe+UdS6TCbgV3SLgzgNS7uhdaWA5H2SOimdUJzlrWh8W0Q2aL82z2i5ZK4Cay8iP3LGcZPZEPU5mD5BTqepEiw3rsk8KgpXBRj5TYNVrxo1EC8bbxvrivvtF/dzeMwIbIiBYBLUqrIoZSq7oPmQ1nlH0cUDWBsAH0HZ1WRlpH/e+7GBWJ+EOJ2dqnk0HOMTGqYNjPZMDaxoBLDT23PVoD9YKfoeXYv0i//Xdk9YruEfQaMUgtuX+oRFpqUNMoOEsDIw1igPgE5xxj4Ka2v1ybf0UyIvGFUEDJSY1a+CQ0Ke6uattGcjVwKxmBgF6IUQ5s/0CtX/m5KGVthM8xMB1om4IOSEa71DInMOI8/WPrK3CirT9XzgoYSAqgqZt68JlXonrs2vgdc0RZQ1uHohqlqAtKxHm48dleAdGYCnPjbyMGAo5PIGkA1POWscr9Xzte3U3wvx8SNDSP98rQwLE19nHRkSiQUU+r8rCHIzsl88EhM3uwMCn5p5mB7Ih02ytCJhFiVKRwOKv4V204osUUgWsSikTeLmdiuTgER26MpFUGJEwf0l6pHlm9OblmNbBYAghAcOVHSHBkq4lzyaAVYurR31Ku57JYyFsISbFPKyzp63xPcFGpXfD9FsudDQkokSmVgspIS4cZbLP30pSc8tQPiT5Y7THlZVGCmBbu7hTdCAyf8uth/DmpNL5CCXyWB+Ao0zzH5tyi90yzGqsX8ze5AYEEua34rdQVH40xddhEE5uoTk0sCQs265+F5IX/7xEUBDhsdy2t+/xUm+eA0ngEG++OZMNCdDB7LKv1nqYYnGB7dh1hTazzr3qkxk2QTCfo5hMg8zI962swnt+gzuugteh407wu/wiHEBR88+RyJtj1qf13u0pMDO+L/V2h/hxHfVEd5Z7fCLtPhJtG8HznoyJjxiPkZa", "X-Forefront-Antispam-Report": "CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(376014)(35042699022)(14060799003)(82310400026)(1800799024)(36860700013)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 17:18:20.3443 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a6aa4dcc-aa02-4e09-192b-08de3e597125", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AMS0EPF000001B7.eurprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds the following intrinsics (all __arm_streaming only) along with\nasm tests for them.\n\nBFCVT, FCVT Convert to packed 8-bit floating-point format:\n- svmfloat8_t svcvt_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_bf16_x2]_fpm(svbfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\nFCVTN Convert to interleaved 8-bit floating-point format.\n- svmfloat8_t svcvtn_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\ngcc/\n\t* config/aarch64/aarch64-sve-builtins-base.cc (svcvt_impl): Update to\n\thandle fp8 cases.\n\t* config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtn): Added\n\tDEF_SVE_FUNCTION_GS_FPM instances.\n\t* config/aarch64/aarch64-sve2.md\n\t(@aarch64_sve2_fp8_cvtn<mode>): Updated define_insn for additional case.\n\t(@aarch64_sme2_fp8_cvt<mode>): Added new define_insn.\n\t* config/aarch64/iterators.md (VNx16F_NARROW): Added new iterator to\n\thandle narrowing SVE floating point operations.\n\t(UNSPEC_FCVT): Added new unspec.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c: Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n\t(TEST_X2_NARROW): Added fpm0 argument for intrinsics.\n\t(TEST_X4_NARROW): Likewise.\n---\n .../aarch64/aarch64-sve-builtins-base.cc | 26 ++++---\n .../aarch64/aarch64-sve-builtins-sve2.def | 3 +\n gcc/config/aarch64/aarch64-sve2.md | 14 +++-\n gcc/config/aarch64/iterators.md | 4 ++\n .../aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sve/acle/asm/test_sve_acle.h | 2 +\n 9 files changed, 293 insertions(+), 12 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\nindex ecc06877cac..622485effb3 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n@@ -779,17 +779,23 @@ public:\n {\n \tmachine_mode mode0 = e.result_mode ();\n \tmachine_mode mode1 = GET_MODE (e.args[0]);\n-\tconvert_optab optab;\n-\tif (e.type_suffix (0).integer_p)\n-\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n-\telse if (e.type_suffix (1).integer_p)\n-\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab : sfloat_optab;\n-\telse if (e.type_suffix (0).element_bits\n-\t\t < e.type_suffix (1).element_bits)\n-\t optab = trunc_optab;\n+\tif (e.fpm_mode == aarch64_sve::FPM_set)\n+\t icode = code_for_aarch64_sme2_fp8_cvt (mode1);\n \telse\n-\t optab = sext_optab;\n-\ticode = convert_optab_handler (optab, mode0, mode1);\n+\t {\n+\t convert_optab optab;\n+\t if (e.type_suffix (0).integer_p)\n+\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n+\t else if (e.type_suffix (1).integer_p)\n+\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab\n+\t\t\t\t\t\t : sfloat_optab;\n+\t else if (e.type_suffix (0).element_bits\n+\t\t < e.type_suffix (1).element_bits)\n+\t optab = trunc_optab;\n+\t else\n+\t optab = sext_optab;\n+\t icode = convert_optab_handler (optab, mode0, mode1);\n+\t }\n \tgcc_assert (icode != CODE_FOR_nothing);\n \treturn e.use_exact_insn (icode);\n }\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\nindex c271b97de87..869e006ffde 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n@@ -421,6 +421,9 @@ DEF_SVE_FUNCTION_GS_FPM (svdot_lane, ternary_mfloat8_lane_group_selection, h_flo\n \n #define REQUIRED_EXTENSIONS \\\n streaming_only (AARCH64_FL_SME2 | AARCH64_FL_FP8)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtn_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvtn, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt1, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt2, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvtl1, unary_convert, cvt_mf8, x2, none, set)\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex ab8098d3327..da7a7a3c23c 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3635,10 +3635,10 @@ (define_insn \"@aarch64_sve_cvtn<mode>\"\n (define_insn \"@aarch64_sve2_fp8_cvtn<mode>\"\n [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n \t(unspec:VNx16QI\n-\t [(match_operand:SVE_FULL_HFx2 1 \"aligned_register_operand\" \"Uw2\")\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n \t (reg:DI FPM_REGNUM)]\n \t UNSPEC_FP8FCVTN))]\n- \"TARGET_SSVE_FP8\"\n+ \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_STREAMING_SME2\"\n \"<b>fcvtn\\t%0.b, %1\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n@@ -3666,6 +3666,16 @@ (define_insn \"@aarch64_sve_cvtnt<mode>\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n \n+(define_insn \"@aarch64_sme2_fp8_cvt<mode>\"\n+ [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n+\t(unspec:VNx16QI\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t UNSPEC_FCVT))]\n+ \"TARGET_SSME2_FP8\"\n+ \"<b>fcvt\\t%0.b, %1\"\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP<-INT] Multi-vector conversions\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 026c3101e38..e6f59d22d0c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -712,6 +712,9 @@ (define_mode_iterator VNx4_WIDE [VNx4SI])\n (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])\n (define_mode_iterator VNx2_WIDE [VNx2DI])\n \n+;; Used for narrowing SVE floating point operations.\n+(define_mode_iterator VNx16F_NARROW [VNx16BF VNx16HF VNx16SF])\n+\n ;; All SVE predicate modes.\n (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])\n \n@@ -1061,6 +1064,7 @@ (define_c_enum \"unspec\"\n UNSPEC_F2CVTL\t; Used in aarch64-sve2.md.\n UNSPEC_F2CVTLT\t; Used in aarch64-sve2.md.\n UNSPEC_FADDP\t; Used in aarch64-sve2.md.\n+ UNSPEC_FCVT\t\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNB\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNT\t; Used in aarch64-sve2.md.\n UNSPEC_FMAXNMP\t; Used in aarch64-sve2.md.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\nnew file mode 100644\nindex 00000000000..bdda0fd36d6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#pragma GCC target \"+fp8+bf16\"\n+#include \"test_sme2_acle.h\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tbfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svbfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_bf16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\nnew file mode 100644\nindex 00000000000..93792e90945\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_f16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..a9ee10de0df\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvt_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvt_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvt_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvt_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvt_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvt_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..2d0bd7eda0e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvtn_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvtn_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvtn_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvtn_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvtn_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvtn_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvtn_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvtn_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\nindex 7c156c4cf2a..8d4ed537c87 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n@@ -733,6 +733,7 @@\n #define TEST_X2_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register ZTYPE z5 __asm (\"z5\");\t\t\t\t\\\n register TTYPE z6 __asm (\"z6\");\t\t\t\t\\\n@@ -749,6 +750,7 @@\n #define TEST_X4_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register TTYPE z4 __asm (\"z4\");\t\t\t\t\\\n register TTYPE z16 __asm (\"z16\");\t\t\t\t\\\n", "prefixes": [ "v5", "4/9" ] }