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GET /api/1.0/patches/2175660/?format=api
{ "id": 2175660, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175660/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-improvements-v1-5-72db131ba148@baylibre.com>", "date": "2025-12-18T17:17:03", "name": "[5/8] clk: mediatek: add of_xlate ops", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "5dcb14ccd9a4f711df85fcbc332b70fef090b765", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-improvements-v1-5-72db131ba148@baylibre.com/mbox/", "series": [ { "id": 485889, "url": "http://patchwork.ozlabs.org/api/1.0/series/485889/?format=api", "date": "2025-12-18T17:16:58", "name": "clk: mediatek: implement of_xlate and dump", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485889/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175660/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=v7Sl1yeS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-improvements-v1-5-72db131ba148@baylibre.com>", "References": "<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>", "To": "Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=16947;\n i=dlechner@baylibre.com; h=from:subject:message-id;\n bh=IvUTpNs5/CRdXgTJXChrdLOrx+ltCJbvW41tHxJ0hYo=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRDcwPP7udZkHYlN/C7x5wyverKmvqmH1bBOsO\n cHdOqaSy6aJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUQ3MBYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A97kH/1Meud61GaxMIxB5Z5w08edp4OrzAajtt7ggfGf\n NvFBZ8oXeABgwZb8CZvFScbmKCfVgMa/Q6Ky7Qlds2iP2W+egx38UUH9EopGPdi8xb4zQJBDS/9\n 1oVlsZOkEmI/ucTG37Kqbe8fEoC7m2Xa+4t8uB9gieO1dRNCO5xcde/y0FmkV0Da0HjIChsdl5+\n tU+/63/W49FTWOJsu5U+IYGIpRo60BXQ7yaOCylJR560Olypdbur4gqMaH3R6GA3VpV5d1nvJgx\n J/+TbQ5OSgd65VjkJGVsDTZijvOk5kOmb9JNEhn2DaHzn5xiJrPyws9hLTkF0Ni14uz0etN00/w\n X09A=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 18:18:40 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add driver-specific of_xlate ops for MediaTek clocks. This provides\nbetter checking of the args passed from the devicetree. Compared to\nthe default of_xlate implementation, this will return -EINVAL if there\nare zero args (id is always required) and -ENOENT if the id is out of\nrange for the clock type. This will protect against out of bounds array\naccesses later on when the clk->id is used to index into the clock\ndata arrays.\n\nIf there is a id_offs_map, then we have to do that translation first\nbefore checking the id to see if it is in range. There is no sense in\ndoing the mapping multiple times, so we save the mapped ID in clk->id\nand remove mtk_clk_get_id().\n\nmtk_clk_find_parent_rate() also had to be updated since it creates a\ntemporary struct clk to represent the parent clock. It now has do the\ntranslation in case the parent clock also uses an id_offs_map.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mtk.c | 244 ++++++++++++++++++++++++++++++-----------\n 1 file changed, 183 insertions(+), 61 deletions(-)", "diff": "diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 6ed0f23f685..1539dc6cbcc 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -35,16 +35,35 @@\n \n /* shared functions */\n \n-static int mtk_clk_get_id(struct clk *clk)\n+static const int mtk_common_clk_of_xlate(struct clk *clk,\n+\t\t\t\t\t struct ofnode_phandle_args *args,\n+\t\t\t\t\t const struct mtk_clk_tree *tree)\n {\n-\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = clk->id;\n+\tint id;\n+\n+\tif (args->args_count != 1) {\n+\t\tdebug(\"Invalid args_count: %d\\n\", args->args_count);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tid = args->args[0];\n \n \t/* Remap the clk ID to the one expected by driver */\n-\tif (priv->tree->id_offs_map)\n-\t\tid = priv->tree->id_offs_map[id];\n+\tif (tree->id_offs_map) {\n+\t\tif (id >= tree->id_offs_map_size)\n+\t\t\treturn -ENOENT;\n+\n+\t\tid = tree->id_offs_map[id];\n+\t}\n \n-\treturn id;\n+\t/* Some IDs in the map may not be valid. */\n+\tif (id < 0)\n+\t\treturn -ENOENT;\n+\n+\tclk->id = id;\n+\tclk->data = 0;\n+\n+\treturn 0;\n }\n \n static int mtk_dummy_enable(struct clk *clk)\n@@ -110,13 +129,23 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate)\n static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,\n \t\t\t\t struct udevice *pdev)\n {\n-\tstruct clk parent = { .id = id, };\n+\tstruct ofnode_phandle_args args = {\n+\t\t.args_count = 1,\n+\t\t.args = { id },\n+\t};\n+\tstruct clk parent = { };\n+\tint ret;\n \n \tif (pdev)\n \t\tparent.dev = pdev;\n \telse\n \t\tparent.dev = clk->dev;\n \n+\targs.node = dev_ofnode(parent.dev);\n+\tret = ((struct clk_ops *)parent.dev->driver->ops)->of_xlate(&parent, &args);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn clk_get_rate(&parent);\n }\n \n@@ -166,6 +195,29 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,\n \n /* apmixedsys functions */\n \n+static const int mtk_apmixedsys_of_xlate(struct clk *clk,\n+\t\t\t\t\t struct ofnode_phandle_args *args)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\tint ret;\n+\n+\tret = mtk_common_clk_of_xlate(clk, args, tree);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* apmixedsys only uses plls and gates. */\n+\n+\tif (tree->plls && clk->id < tree->num_plls)\n+\t\treturn 0;\n+\n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates)\n+\t\treturn 0;\n+\n+\treturn -ENOENT;\n+}\n+\n static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,\n \t\t\t\t\t u32 fin, u32 pcw, int postdiv)\n {\n@@ -274,15 +326,14 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id,\n static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tu32 pcw = 0;\n \tu32 postdiv;\n \n-\tif (priv->tree->gates && id >= priv->tree->gates_offs)\n+\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs)\n \t\treturn -EINVAL;\n \n-\tmtk_pll_calc_values(priv, id, &pcw, &postdiv, rate);\n-\tmtk_pll_set_rate_regs(priv, id, pcw, postdiv);\n+\tmtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate);\n+\tmtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv);\n \n \treturn 0;\n }\n@@ -291,18 +342,17 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_pll_data *pll;\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \tu32 postdiv;\n \tu32 pcw;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && id >= priv->tree->gates_offs) {\n-\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_clk_find_parent_rate(clk, gate->parent, NULL);\n \t}\n \n-\tpll = &priv->tree->plls[id];\n+\tpll = &priv->tree->plls[clk->id];\n \n \tpostdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &\n \t\t POSTDIV_MASK;\n@@ -319,17 +369,16 @@ static int mtk_apmixedsys_enable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_pll_data *pll;\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \tu32 r;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && id >= priv->tree->gates_offs) {\n-\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_gate_enable(priv->base, gate);\n \t}\n \n-\tpll = &priv->tree->plls[id];\n+\tpll = &priv->tree->plls[clk->id];\n \n \tr = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;\n \twritel(r, priv->base + pll->pwr_reg);\n@@ -358,17 +407,16 @@ static int mtk_apmixedsys_disable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_pll_data *pll;\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \tu32 r;\n \n \t/* GATE handling */\n-\tif (priv->tree->gates && id >= priv->tree->gates_offs) {\n-\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tif (priv->tree->gates && clk->id >= priv->tree->gates_offs) {\n+\t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\treturn mtk_gate_disable(priv->base, gate);\n \t}\n \n-\tpll = &priv->tree->plls[id];\n+\tpll = &priv->tree->plls[clk->id];\n \n \tif (pll->flags & HAVE_RST_BAR) {\n \t\tr = readl(priv->base + pll->reg + REG_CON0);\n@@ -391,6 +439,33 @@ static int mtk_apmixedsys_disable(struct clk *clk)\n \n /* topckgen functions */\n \n+static const int mtk_topckgen_of_xlate(struct clk *clk,\n+\t\t\t\t struct ofnode_phandle_args *args)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\tint ret;\n+\n+\tret = mtk_common_clk_of_xlate(clk, args, tree);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* topckgen only uses fclks, fdivs and muxes. */\n+\n+\tif (tree->fclks && clk->id < tree->num_fclks)\n+\t\treturn 0;\n+\n+\tif (tree->fdivs && clk->id >= tree->fdivs_offs &&\n+\t clk->id < tree->fdivs_offs + tree->num_fdivs)\n+\t\treturn 0;\n+\n+\tif (tree->muxes && clk->id >= tree->muxes_offs &&\n+\t clk->id < tree->muxes_offs + tree->num_muxes)\n+\t\treturn 0;\n+\n+\treturn -ENOENT;\n+}\n+\n static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,\n \t\t\t\t ulong parent_rate)\n {\n@@ -421,6 +496,9 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)\n \t\trate = priv->tree->xtal_rate;\n \t}\n \n+\tif (((long)rate) < 0)\n+\t\treturn rate;\n+\n \treturn mtk_factor_recalc_rate(fdiv, rate);\n }\n \n@@ -486,15 +564,14 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,\n static ulong mtk_topckgen_get_rate(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \n-\tif (id < priv->tree->fdivs_offs)\n-\t\treturn priv->tree->fclks[id].rate;\n-\telse if (id < priv->tree->muxes_offs)\n-\t\treturn mtk_topckgen_get_factor_rate(clk, id -\n+\tif (clk->id < priv->tree->fdivs_offs)\n+\t\treturn priv->tree->fclks[clk->id].rate;\n+\telse if (clk->id < priv->tree->muxes_offs)\n+\t\treturn mtk_topckgen_get_factor_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->fdivs_offs);\n \telse\n-\t\treturn mtk_topckgen_get_mux_rate(clk, id -\n+\t\treturn mtk_topckgen_get_mux_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->muxes_offs);\n }\n \n@@ -502,13 +579,12 @@ static int mtk_clk_mux_enable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_composite *mux;\n-\tint id = mtk_clk_get_id(clk);\n \tu32 val;\n \n-\tif (id < priv->tree->muxes_offs)\n+\tif (clk->id < priv->tree->muxes_offs)\n \t\treturn 0;\n \n-\tmux = &priv->tree->muxes[id - priv->tree->muxes_offs];\n+\tmux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];\n \tif (mux->gate_shift < 0)\n \t\treturn 0;\n \n@@ -536,13 +612,12 @@ static int mtk_clk_mux_disable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct mtk_composite *mux;\n-\tint id = mtk_clk_get_id(clk);\n \tu32 val;\n \n-\tif (id < priv->tree->muxes_offs)\n+\tif (clk->id < priv->tree->muxes_offs)\n \t\treturn 0;\n \n-\tmux = &priv->tree->muxes[id - priv->tree->muxes_offs];\n+\tmux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];\n \tif (mux->gate_shift < 0)\n \t\treturn 0;\n \n@@ -563,10 +638,9 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)\n {\n \tstruct mtk_clk_priv *parent_priv = dev_get_priv(parent->dev);\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tu32 parent_type;\n \n-\tif (id < priv->tree->muxes_offs)\n+\tif (clk->id < priv->tree->muxes_offs)\n \t\treturn 0;\n \n \tif (!parent_priv)\n@@ -574,36 +648,62 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)\n \n \tparent_type = parent_priv->tree->flags & CLK_PARENT_MASK;\n \treturn mtk_clk_mux_set_parent(priv->base, parent->id, parent_type,\n-\t\t\t&priv->tree->muxes[id - priv->tree->muxes_offs]);\n+\t\t\t&priv->tree->muxes[clk->id - priv->tree->muxes_offs]);\n }\n \n /* infrasys functions */\n \n+static const int mtk_infrasys_of_xlate(struct clk *clk,\n+\t\t\t\t struct ofnode_phandle_args *args)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\tint ret;\n+\n+\tret = mtk_common_clk_of_xlate(clk, args, tree);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* ifrasys only uses fdivs, muxes and gates. */\n+\n+\tif (tree->fdivs && clk->id >= tree->fdivs_offs &&\n+\t clk->id < tree->fdivs_offs + tree->num_fdivs)\n+\t\treturn 0;\n+\n+\tif (tree->muxes && clk->id >= tree->muxes_offs &&\n+\t clk->id < tree->muxes_offs + tree->num_muxes)\n+\t\treturn 0;\n+\n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates)\n+\t\treturn 0;\n+\n+\treturn -ENOENT;\n+}\n+\n static int mtk_clk_infrasys_enable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n \t/* MUX handling */\n-\tif (!priv->tree->gates || id < priv->tree->gates_offs)\n+\tif (!priv->tree->gates || clk->id < priv->tree->gates_offs)\n \t\treturn mtk_clk_mux_enable(clk);\n \n-\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \treturn mtk_gate_enable(priv->base, gate);\n }\n \n static int mtk_clk_infrasys_disable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n \t/* MUX handling */\n-\tif (!priv->tree->gates || id < priv->tree->gates_offs)\n+\tif (!priv->tree->gates || clk->id < priv->tree->gates_offs)\n \t\treturn mtk_clk_mux_disable(clk);\n \n-\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \treturn mtk_gate_disable(priv->base, gate);\n }\n \n@@ -625,6 +725,9 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)\n \t\trate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);\n \t}\n \n+\tif (((long)rate) < 0)\n+\t\treturn rate;\n+\n \treturn mtk_factor_recalc_rate(fdiv, rate);\n }\n \n@@ -658,24 +761,23 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)\n static ulong mtk_infrasys_get_rate(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tulong rate;\n \n-\tif (id < priv->tree->fdivs_offs) {\n-\t\trate = priv->tree->fclks[id].rate;\n-\t} else if (id < priv->tree->muxes_offs) {\n-\t\trate = mtk_infrasys_get_factor_rate(clk, id -\n+\tif (clk->id < priv->tree->fdivs_offs) {\n+\t\trate = priv->tree->fclks[clk->id].rate;\n+\t} else if (clk->id < priv->tree->muxes_offs) {\n+\t\trate = mtk_infrasys_get_factor_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->fdivs_offs);\n \t/* No gates defined or ID is a MUX */\n-\t} else if (!priv->tree->gates || id < priv->tree->gates_offs) {\n-\t\trate = mtk_infrasys_get_mux_rate(clk, id -\n+\t} else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) {\n+\t\trate = mtk_infrasys_get_mux_rate(clk, clk->id -\n \t\t\t\t\t\t priv->tree->muxes_offs);\n \t/* Only valid with muxes + gates implementation */\n \t} else {\n \t\tstruct udevice *parent = NULL;\n \t\tconst struct mtk_gate *gate;\n \n-\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\t\tgate = &priv->tree->gates[clk->id - priv->tree->gates_offs];\n \t\tif (gate->flags & CLK_PARENT_TOPCKGEN)\n \t\t\tparent = priv->parent;\n \t\t/*\n@@ -693,29 +795,45 @@ static ulong mtk_infrasys_get_rate(struct clk *clk)\n \n /* CG functions */\n \n+static const int mtk_clk_gate_of_xlate(struct clk *clk,\n+\t\t\t\t struct ofnode_phandle_args *args)\n+{\n+\tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\tint ret;\n+\n+\tret = mtk_common_clk_of_xlate(clk, args, tree);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + priv->num_gates)\n+\t\treturn 0;\n+\n+\treturn -ENOENT;\n+}\n+\n static int mtk_clk_gate_enable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n-\tif (id < priv->tree->gates_offs)\n+\tif (clk->id < priv->tree->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n \treturn mtk_gate_enable(priv->base, gate);\n }\n \n static int mtk_clk_gate_disable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n-\tif (id < priv->tree->gates_offs)\n+\tif (clk->id < priv->tree->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n \treturn mtk_gate_disable(priv->base, gate);\n }\n \n@@ -723,13 +841,12 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tstruct udevice *parent = priv->parent;\n-\tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n-\tif (id < priv->tree->gates_offs)\n+\tif (clk->id < priv->tree->gates_offs)\n \t\treturn -EINVAL;\n \n-\tgate = &priv->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->gates[clk->id - priv->tree->gates_offs];\n \t/*\n \t * With requesting a TOPCKGEN parent, make sure the dev parent\n \t * is actually topckgen. This might not be the case for an\n@@ -753,6 +870,7 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)\n }\n \n const struct clk_ops mtk_clk_apmixedsys_ops = {\n+\t.of_xlate = mtk_apmixedsys_of_xlate,\n \t.enable = mtk_apmixedsys_enable,\n \t.disable = mtk_apmixedsys_disable,\n \t.set_rate = mtk_apmixedsys_set_rate,\n@@ -760,12 +878,14 @@ const struct clk_ops mtk_clk_apmixedsys_ops = {\n };\n \n const struct clk_ops mtk_clk_fixed_pll_ops = {\n+\t.of_xlate = mtk_topckgen_of_xlate,\n \t.enable = mtk_dummy_enable,\n \t.disable = mtk_dummy_enable,\n \t.get_rate = mtk_topckgen_get_rate,\n };\n \n const struct clk_ops mtk_clk_topckgen_ops = {\n+\t.of_xlate = mtk_topckgen_of_xlate,\n \t.enable = mtk_clk_mux_enable,\n \t.disable = mtk_clk_mux_disable,\n \t.get_rate = mtk_topckgen_get_rate,\n@@ -773,6 +893,7 @@ const struct clk_ops mtk_clk_topckgen_ops = {\n };\n \n const struct clk_ops mtk_clk_infrasys_ops = {\n+\t.of_xlate = mtk_infrasys_of_xlate,\n \t.enable = mtk_clk_infrasys_enable,\n \t.disable = mtk_clk_infrasys_disable,\n \t.get_rate = mtk_infrasys_get_rate,\n@@ -780,6 +901,7 @@ const struct clk_ops mtk_clk_infrasys_ops = {\n };\n \n const struct clk_ops mtk_clk_gate_ops = {\n+\t.of_xlate = mtk_clk_gate_of_xlate,\n \t.enable = mtk_clk_gate_enable,\n \t.disable = mtk_clk_gate_disable,\n \t.get_rate = mtk_clk_gate_get_rate,\n", "prefixes": [ "5/8" ] }