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GET /api/1.0/patches/2175657/?format=api
{ "id": 2175657, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175657/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-clk-mtk-improvements-v1-1-72db131ba148@baylibre.com>", "date": "2025-12-18T17:16:59", "name": "[1/8] clk: mediatek: add array size fields to clk trees", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "7597ab4fb21872e41494d22dfe60eee5227cdf47", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/1.0/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-improvements-v1-1-72db131ba148@baylibre.com/mbox/", "series": [ { "id": 485889, "url": "http://patchwork.ozlabs.org/api/1.0/series/485889/?format=api", "date": "2025-12-18T17:16:58", "name": "clk: mediatek: implement of_xlate and dump", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485889/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175657/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=I8qDO0UU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251218-clk-mtk-improvements-v1-1-72db131ba148@baylibre.com>", "References": "<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>", "In-Reply-To": "<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>", "To": "Lukasz Majewski <lukma@denx.de>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=12913;\n i=dlechner@baylibre.com; h=from:subject:message-id;\n bh=cMpTfFIPl9oMTPcJrIRpafETipdLGaqTOcja91qTtu8=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRDcVE5STkLmNCKSGAMMR4mT+xt2iDrO6WvCNz\n 8gr31/99ASJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUQ3FRYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AsHAH/RbB+aeQMnEzwApgIO/7+Qyx0EhCCjgFWDRvQiK\n dKze+VCf+ONIQMPWrdJDcK2fT0KMKsSjGa2F5OXHBg2jpf8h99AwPm3hWkOEaUUfQ82h7MPyiT9\n 1sWNKiyKrQw97pDyRK672If/hJdGsix8pG7MehfvPfMvHtyTULmY6Q86Xj7n2dtsa0eeS3capVO\n KbH60NIx+w8DXkDh5jYxqocfdRCAxk0vNQBfsJ5esSl4yz8zSAU8a/EBD75ZnW0zoxxtI1o3ML5\n I+jnRSqsB5B2yLAQ7aXlat1r+LFDwXVFABT3j76YmFmLjHg8DQXU9+jGuL6N4Vk1r5UfAF4Xdtp\n pnVc=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 18:18:40 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to\nthe mtk_clk_tree struct and populate them in the clk trees for all\nexisting drivers.\n\nCurrently, there is no bounds checking when accessing the arrays in\nthe clk tree structs. Adding these fields will allow for bounds checking\nin the future.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt7622.c | 9 +++++++++\n drivers/clk/mediatek/clk-mt7623.c | 6 ++++++\n drivers/clk/mediatek/clk-mt7629.c | 8 ++++++++\n drivers/clk/mediatek/clk-mt7981.c | 7 +++++++\n drivers/clk/mediatek/clk-mt7986.c | 7 +++++++\n drivers/clk/mediatek/clk-mt7987.c | 5 +++++\n drivers/clk/mediatek/clk-mt7988.c | 6 ++++++\n drivers/clk/mediatek/clk-mt8183.c | 4 ++++\n drivers/clk/mediatek/clk-mt8365.c | 4 ++++\n drivers/clk/mediatek/clk-mt8512.c | 4 ++++\n drivers/clk/mediatek/clk-mt8516.c | 4 ++++\n drivers/clk/mediatek/clk-mt8518.c | 4 ++++\n drivers/clk/mediatek/clk-mtk.h | 5 +++++\n 13 files changed, 73 insertions(+)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c\nindex 23b9787612a..ccad3820c1b 100644\n--- a/drivers/clk/mediatek/clk-mt7622.c\n+++ b/drivers/clk/mediatek/clk-mt7622.c\n@@ -604,6 +604,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {\n \t.plls = apmixed_plls,\n \t.gates_offs = CLK_APMIXED_MAIN_CORE_EN,\n \t.gates = apmixed_cgs,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_gates = ARRAY_SIZE(apmixed_cgs),\n };\n \n static const struct mtk_clk_tree mt7622_infra_clk_tree = {\n@@ -612,6 +614,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = {\n \t.gates_offs = CLK_INFRA_DBGCLK_PD,\n \t.muxes = infra_muxes,\n \t.gates = infra_cgs,\n+\t.num_muxes = ARRAY_SIZE(infra_muxes),\n+\t.num_gates = ARRAY_SIZE(infra_cgs),\n };\n \n static const struct mtk_clk_tree mt7622_peri_clk_tree = {\n@@ -620,6 +624,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = {\n \t.gates_offs = CLK_PERI_THERM_PD,\n \t.muxes = peri_muxes,\n \t.gates = peri_cgs,\n+\t.num_muxes = ARRAY_SIZE(peri_muxes),\n+\t.num_gates = ARRAY_SIZE(peri_cgs),\n };\n \n static const struct mtk_clk_tree mt7622_clk_tree = {\n@@ -629,6 +635,9 @@ static const struct mtk_clk_tree mt7622_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt7622_mcucfg_probe(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c\nindex d0b80f48b0a..cfc711ad216 100644\n--- a/drivers/clk/mediatek/clk-mt7623.c\n+++ b/drivers/clk/mediatek/clk-mt7623.c\n@@ -997,6 +997,7 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {\n \t.xtal2_rate = 26 * MHZ,\n \t.id_offs_map = pll_id_offs_map,\n \t.plls = apmixed_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n };\n \n static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {\n@@ -1007,6 +1008,9 @@ static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt7623_mcucfg_probe(struct udevice *dev)\n@@ -1063,6 +1067,8 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = {\n \t.gates_offs = peri_id_offs_map[CLK_PERI_NFI],\n \t.muxes = peri_muxes,\n \t.gates = peri_cgs,\n+\t.num_muxes = ARRAY_SIZE(peri_muxes),\n+\t.num_gates = ARRAY_SIZE(peri_cgs),\n \t.xtal_rate = 26 * MHZ,\n };\n \ndiff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c\nindex 94fc5e51456..e0eff01561c 100644\n--- a/drivers/clk/mediatek/clk-mt7629.c\n+++ b/drivers/clk/mediatek/clk-mt7629.c\n@@ -572,6 +572,10 @@ static const struct mtk_clk_tree mt7629_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static const struct mtk_clk_tree mt7629_peri_clk_tree = {\n@@ -584,6 +588,10 @@ static const struct mtk_clk_tree mt7629_peri_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt7629_mcucfg_probe(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c\nindex 6130c93d5e6..9cb2aff2bee 100644\n--- a/drivers/clk/mediatek/clk-mt7981.c\n+++ b/drivers/clk/mediatek/clk-mt7981.c\n@@ -513,6 +513,7 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {\n \t.fdivs_offs = CLK_APMIXED_NR_CLK,\n \t.xtal_rate = 40 * MHZ,\n \t.fclks = fixed_pll_clks,\n+\t.num_fclks = ARRAY_SIZE(fixed_pll_clks),\n };\n \n static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {\n@@ -521,6 +522,9 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n \t.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,\n };\n \n@@ -531,6 +535,9 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {\n \t.fdivs = infra_fixed_divs,\n \t.muxes = infra_muxes,\n \t.gates = infracfg_gates,\n+\t.num_fdivs = ARRAY_SIZE(infra_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(infra_muxes),\n+\t.num_gates = ARRAY_SIZE(infracfg_gates),\n \t.flags = CLK_INFRASYS,\n };\n \ndiff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c\nindex cf298af644c..afff3167284 100644\n--- a/drivers/clk/mediatek/clk-mt7986.c\n+++ b/drivers/clk/mediatek/clk-mt7986.c\n@@ -519,6 +519,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {\n \t.fdivs_offs = CLK_APMIXED_NR_CLK,\n \t.xtal_rate = 40 * MHZ,\n \t.fclks = fixed_pll_clks,\n+\t.num_fclks = ARRAY_SIZE(fixed_pll_clks),\n \t.flags = CLK_APMIXED,\n };\n \n@@ -528,6 +529,9 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n \t.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,\n };\n \n@@ -538,6 +542,9 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {\n \t.fdivs = infra_fixed_divs,\n \t.muxes = infra_muxes,\n \t.gates = infracfg_gates,\n+\t.num_fdivs = ARRAY_SIZE(infra_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(infra_muxes),\n+\t.num_gates = ARRAY_SIZE(infracfg_gates),\n \t.flags = CLK_INFRASYS,\n };\n \ndiff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c\nindex b662d680b15..8e37803e97b 100644\n--- a/drivers/clk/mediatek/clk-mt7987.c\n+++ b/drivers/clk/mediatek/clk-mt7987.c\n@@ -46,6 +46,7 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {\n static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {\n \t.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),\n \t.fclks = apmixedsys_mtk_plls,\n+\t.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),\n \t.flags = CLK_APMIXED,\n \t.xtal_rate = 40 * MHZ,\n };\n@@ -442,6 +443,8 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {\n \t.muxes_offs = CLK_TOP_NETSYS_SEL,\n \t.fdivs = topckgen_mtk_fixed_factors,\n \t.muxes = topckgen_mtk_muxes,\n+\t.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),\n+\t.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),\n \t.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,\n \t.xtal_rate = MT7987_XTAL_RATE,\n };\n@@ -765,6 +768,8 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {\n \t.gates_offs = CLK_INFRA_66M_GPT_BCK,\n \t.muxes = infracfg_mtk_mux,\n \t.gates = infracfg_mtk_gates,\n+\t.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),\n+\t.num_gates = ARRAY_SIZE(infracfg_mtk_gates),\n \t.flags = CLK_BYPASS_XTAL,\n \t.xtal_rate = MT7987_XTAL_RATE,\n };\ndiff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c\nindex c6da42f970b..d594fc6df39 100644\n--- a/drivers/clk/mediatek/clk-mt7988.c\n+++ b/drivers/clk/mediatek/clk-mt7988.c\n@@ -773,6 +773,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = {\n static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {\n \t.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),\n \t.fclks = apmixedsys_mtk_plls,\n+\t.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),\n \t.flags = CLK_APMIXED,\n \t.xtal_rate = 40 * MHZ,\n };\n@@ -783,6 +784,9 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {\n \t.fclks = topckgen_mtk_fixed_clks,\n \t.fdivs = topckgen_mtk_fixed_factors,\n \t.muxes = topckgen_mtk_muxes,\n+\t.num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),\n+\t.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),\n \t.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,\n \t.xtal_rate = 40 * MHZ,\n };\n@@ -792,6 +796,8 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {\n \t.gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,\n \t.muxes = infracfg_mtk_mux,\n \t.gates = infracfg_mtk_gates,\n+\t.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),\n+\t.num_gates = ARRAY_SIZE(infracfg_mtk_gates),\n \t.flags = CLK_BYPASS_XTAL,\n \t.xtal_rate = 40 * MHZ,\n };\ndiff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c\nindex 9612a62e56a..7a1953ef6fd 100644\n--- a/drivers/clk/mediatek/clk-mt8183.c\n+++ b/drivers/clk/mediatek/clk-mt8183.c\n@@ -599,6 +599,10 @@ static const struct mtk_clk_tree mt8183_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static const struct mtk_gate_regs infra0_cg_regs = {\ndiff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c\nindex 53eca73b98d..7897044e1ad 100644\n--- a/drivers/clk/mediatek/clk-mt8365.c\n+++ b/drivers/clk/mediatek/clk-mt8365.c\n@@ -490,6 +490,10 @@ static const struct mtk_clk_tree mt8365_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n /* topckgen cg */\ndiff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c\nindex ab270673442..6d98403bc45 100644\n--- a/drivers/clk/mediatek/clk-mt8512.c\n+++ b/drivers/clk/mediatek/clk-mt8512.c\n@@ -790,6 +790,10 @@ static const struct mtk_clk_tree mt8512_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt8512_apmixedsys_probe(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c\nindex 623f88499f1..c21b9894ad6 100644\n--- a/drivers/clk/mediatek/clk-mt8516.c\n+++ b/drivers/clk/mediatek/clk-mt8516.c\n@@ -739,6 +739,10 @@ static const struct mtk_clk_tree mt8516_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt8516_apmixedsys_probe(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c\nindex ba8cc584d46..48ef209ebbd 100644\n--- a/drivers/clk/mediatek/clk-mt8518.c\n+++ b/drivers/clk/mediatek/clk-mt8518.c\n@@ -1495,6 +1495,10 @@ static const struct mtk_clk_tree mt8518_clk_tree = {\n \t.fclks = top_fixed_clks,\n \t.fdivs = top_fixed_divs,\n \t.muxes = top_muxes,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.num_fclks = ARRAY_SIZE(top_fixed_clks),\n+\t.num_fdivs = ARRAY_SIZE(top_fixed_divs),\n+\t.num_muxes = ARRAY_SIZE(top_muxes),\n };\n \n static int mt8518_apmixedsys_probe(struct udevice *dev)\ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex 89479001ba8..05c22fce10d 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -265,6 +265,11 @@ struct mtk_clk_tree {\n \tconst struct mtk_fixed_factor *fdivs;\n \tconst struct mtk_composite *muxes;\n \tconst struct mtk_gate *gates;\n+\tconst int num_plls;\n+\tconst int num_fclks;\n+\tconst int num_fdivs;\n+\tconst int num_muxes;\n+\tconst int num_gates;\n \tu32 flags;\n };\n \n", "prefixes": [ "1/8" ] }