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GET /api/1.0/patches/2175600/?format=api
{ "id": 2175600, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175600/?format=api", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/1.0/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218151509.361617-5-heikki.krogerus@linux.intel.com>", "date": "2025-12-18T15:15:03", "name": "[v2,4/6] i2c: designware: Combine the init functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d5bdd7c71a583e09ad45db54900dd8fa48f9f228", "submitter": { "id": 23674, "url": "http://patchwork.ozlabs.org/api/1.0/people/23674/?format=api", "name": "Heikki Krogerus", "email": "heikki.krogerus@linux.intel.com" }, "delegate": { "id": 149066, "url": "http://patchwork.ozlabs.org/api/1.0/users/149066/?format=api", "username": "cazzacarna", "first_name": "Andi", "last_name": "Shyti", "email": "andi.shyti@kernel.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20251218151509.361617-5-heikki.krogerus@linux.intel.com/mbox/", "series": [ { "id": 485867, "url": "http://patchwork.ozlabs.org/api/1.0/series/485867/?format=api", "date": "2025-12-18T15:14:59", "name": "i2c: designware: Enable mode swapping", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485867/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175600/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-i2c+bounces-14646-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-i2c@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=faHeHmBZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=\"78739549\"", "E=Sophos;i=\"6.21,158,1763452800\";\n d=\"scan'208\";a=\"78739549\"", "E=Sophos;i=\"6.21,158,1763452800\";\n d=\"scan'208\";a=\"197857504\"" ], "X-ExtLoop1": "1", "From": "Heikki Krogerus <heikki.krogerus@linux.intel.com>", "To": "Andi Shyti <andi.shyti@kernel.org>,\n\tMika Westerberg <mika.westerberg@linux.intel.com>", "Cc": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n\tJan Dabros <jsd@semihalf.com>,\n\tRaag Jadav <raag.jadav@intel.com>,\n\tlinux-i2c@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 4/6] i2c: designware: Combine the init functions", "Date": "Thu, 18 Dec 2025 16:15:03 +0100", "Message-ID": "<20251218151509.361617-5-heikki.krogerus@linux.intel.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20251218151509.361617-1-heikki.krogerus@linux.intel.com>", "References": "<20251218151509.361617-1-heikki.krogerus@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-i2c@vger.kernel.org", "List-Id": "<linux-i2c.vger.kernel.org>", "List-Subscribe": "<mailto:linux-i2c+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-i2c+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "Providing a single function for controller initialisation.\nThe controller initialisation has the same steps for master\nand slave modes, except the timing parameters are only\nneeded in master mode.\n\nSigned-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>\n---\n drivers/i2c/busses/i2c-designware-amdisp.c | 4 +-\n drivers/i2c/busses/i2c-designware-common.c | 81 +++++++++++++++++++++-\n drivers/i2c/busses/i2c-designware-core.h | 3 +-\n drivers/i2c/busses/i2c-designware-master.c | 70 +------------------\n drivers/i2c/busses/i2c-designware-slave.c | 44 ------------\n 5 files changed, 85 insertions(+), 117 deletions(-)", "diff": "diff --git a/drivers/i2c/busses/i2c-designware-amdisp.c b/drivers/i2c/busses/i2c-designware-amdisp.c\nindex 450793d5f839..ec9259dd2a4f 100644\n--- a/drivers/i2c/busses/i2c-designware-amdisp.c\n+++ b/drivers/i2c/busses/i2c-designware-amdisp.c\n@@ -163,8 +163,8 @@ static int amd_isp_dw_i2c_plat_runtime_resume(struct device *dev)\n \n \tif (!i_dev->shared_with_punit)\n \t\ti2c_dw_prepare_clk(i_dev, true);\n-\tif (i_dev->init)\n-\t\ti_dev->init(i_dev);\n+\n+\ti2c_dw_init(i_dev);\n \n \treturn 0;\n }\ndiff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c\nindex 1823e4b71004..8e99549b37a3 100644\n--- a/drivers/i2c/busses/i2c-designware-common.c\n+++ b/drivers/i2c/busses/i2c-designware-common.c\n@@ -358,6 +358,83 @@ static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0;\n \n #endif\t/* CONFIG_ACPI */\n \n+static void i2c_dw_configure_mode(struct dw_i2c_dev *dev)\n+{\n+\tswitch (dev->mode) {\n+\tcase DW_IC_MASTER:\n+\t\tregmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);\n+\t\tregmap_write(dev->map, DW_IC_RX_TL, 0);\n+\t\tregmap_write(dev->map, DW_IC_CON, dev->master_cfg);\n+\t\tbreak;\n+\tcase DW_IC_SLAVE:\n+\t\tregmap_write(dev->map, DW_IC_TX_TL, 0);\n+\t\tregmap_write(dev->map, DW_IC_RX_TL, 0);\n+\t\tregmap_write(dev->map, DW_IC_CON, dev->slave_cfg);\n+\t\tregmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void i2c_dw_write_timings(struct dw_i2c_dev *dev)\n+{\n+\t/* Write standard speed timing parameters */\n+\tregmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);\n+\tregmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);\n+\n+\t/* Write fast mode/fast mode plus timing parameters */\n+\tregmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);\n+\tregmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);\n+\n+\t/* Write high speed timing parameters if supported */\n+\tif (dev->hs_hcnt && dev->hs_lcnt) {\n+\t\tregmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);\n+\t\tregmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);\n+\t}\n+}\n+\n+/**\n+ * i2c_dw_init() - Initialize the DesignWare I2C hardware\n+ * @dev: device private data\n+ *\n+ * This functions configures and enables the DesigWare I2C hardware.\n+ *\n+ * Return: 0 on success, or negative errno otherwise.\n+ */\n+int i2c_dw_init(struct dw_i2c_dev *dev)\n+{\n+\tint ret;\n+\n+\tret = i2c_dw_acquire_lock(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Disable the adapter */\n+\t__i2c_dw_disable(dev);\n+\n+\t/*\n+\t * Mask SMBus interrupts to block storms from broken\n+\t * firmware that leaves IC_SMBUS=1; the handler never\n+\t * services them.\n+\t */\n+\tregmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);\n+\n+\tif (dev->mode == DW_IC_MASTER)\n+\t\ti2c_dw_write_timings(dev);\n+\n+\t/* Write SDA hold time if supported */\n+\tif (dev->sda_hold_time)\n+\t\tregmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);\n+\n+\ti2c_dw_configure_mode(dev);\n+\n+\ti2c_dw_release_lock(dev);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(i2c_dw_init);\n+\n static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)\n {\n \tu32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);\n@@ -798,7 +875,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev)\n \tif (ret)\n \t\treturn ret;\n \n-\tret = dev->init(dev);\n+\tret = i2c_dw_init(dev);\n \tif (ret)\n \t\treturn ret;\n \n@@ -891,7 +968,7 @@ static int i2c_dw_runtime_resume(struct device *device)\n \tif (!dev->shared_with_punit)\n \t\ti2c_dw_prepare_clk(dev, true);\n \n-\tdev->init(dev);\n+\ti2c_dw_init(dev);\n \n \treturn 0;\n }\ndiff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h\nindex 0f58c4b50377..82465b134c34 100644\n--- a/drivers/i2c/busses/i2c-designware-core.h\n+++ b/drivers/i2c/busses/i2c-designware-core.h\n@@ -240,7 +240,6 @@ struct reset_control;\n * @semaphore_idx: Index of table with semaphore type attached to the bus. It's\n *\t-1 if there is no semaphore.\n * @shared_with_punit: true if this bus is shared with the SoC's PUNIT\n- * @init: function to initialize the I2C hardware\n * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing\n * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE\n * @rinfo: I²C GPIO recovery information\n@@ -301,7 +300,6 @@ struct dw_i2c_dev {\n \tvoid\t\t\t(*release_lock)(void);\n \tint\t\t\tsemaphore_idx;\n \tbool\t\t\tshared_with_punit;\n-\tint\t\t\t(*init)(struct dw_i2c_dev *dev);\n \tint\t\t\t(*set_sda_hold_time)(struct dw_i2c_dev *dev);\n \tint\t\t\tmode;\n \tstruct i2c_bus_recovery_info rinfo;\n@@ -408,6 +406,7 @@ static inline void i2c_dw_configure(struct dw_i2c_dev *dev)\n }\n \n int i2c_dw_probe(struct dw_i2c_dev *dev);\n+int i2c_dw_init(struct dw_i2c_dev *dev);\n \n #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)\n int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);\ndiff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c\nindex 91540a4520a3..33432bbaec1f 100644\n--- a/drivers/i2c/busses/i2c-designware-master.c\n+++ b/drivers/i2c/busses/i2c-designware-master.c\n@@ -31,16 +31,6 @@\n #define AMD_TIMEOUT_MAX_US\t250\n #define AMD_MASTERCFG_MASK\tGENMASK(15, 0)\n \n-static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)\n-{\n-\t/* Configure Tx/Rx FIFO threshold levels */\n-\tregmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);\n-\tregmap_write(dev->map, DW_IC_RX_TL, 0);\n-\n-\t/* Configure the I2C master */\n-\tregmap_write(dev->map, DW_IC_CON, dev->master_cfg);\n-}\n-\n static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)\n {\n \tunsigned int comp_param1;\n@@ -195,58 +185,6 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)\n \treturn 0;\n }\n \n-/**\n- * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware\n- * @dev: device private data\n- *\n- * This functions configures and enables the I2C master.\n- * This function is called during I2C init function, and in case of timeout at\n- * run time.\n- *\n- * Return: 0 on success, or negative errno otherwise.\n- */\n-static int i2c_dw_init_master(struct dw_i2c_dev *dev)\n-{\n-\tint ret;\n-\n-\tret = i2c_dw_acquire_lock(dev);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Disable the adapter */\n-\t__i2c_dw_disable(dev);\n-\n-\t/*\n-\t * Mask SMBus interrupts to block storms from broken\n-\t * firmware that leaves IC_SMBUS=1; the handler never\n-\t * services them.\n-\t */\n-\tregmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);\n-\n-\t/* Write standard speed timing parameters */\n-\tregmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);\n-\tregmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);\n-\n-\t/* Write fast mode/fast mode plus timing parameters */\n-\tregmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);\n-\tregmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);\n-\n-\t/* Write high speed timing parameters if supported */\n-\tif (dev->hs_hcnt && dev->hs_lcnt) {\n-\t\tregmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);\n-\t\tregmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);\n-\t}\n-\n-\t/* Write SDA hold time if supported */\n-\tif (dev->sda_hold_time)\n-\t\tregmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);\n-\n-\ti2c_dw_configure_fifo_master(dev);\n-\ti2c_dw_release_lock(dev);\n-\n-\treturn 0;\n-}\n-\n static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)\n {\n \tstruct i2c_msg *msgs = dev->msgs;\n@@ -843,9 +781,9 @@ i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num)\n \tret = i2c_dw_wait_transfer(dev);\n \tif (ret) {\n \t\tdev_err(dev->dev, \"controller timed out\\n\");\n-\t\t/* i2c_dw_init_master() implicitly disables the adapter */\n+\t\t/* i2c_dw_init() implicitly disables the adapter */\n \t\ti2c_recover_bus(&dev->adapter);\n-\t\ti2c_dw_init_master(dev);\n+\t\ti2c_dw_init(dev);\n \t\tgoto done;\n \t}\n \n@@ -950,7 +888,7 @@ static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)\n \n \ti2c_dw_prepare_clk(dev, true);\n \treset_control_deassert(dev->rst);\n-\ti2c_dw_init_master(dev);\n+\ti2c_dw_init(dev);\n }\n \n static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)\n@@ -999,8 +937,6 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev)\n \n \tinit_completion(&dev->cmd_complete);\n \n-\tdev->init = i2c_dw_init_master;\n-\n \tret = i2c_dw_set_timings_master(dev);\n \tif (ret)\n \t\treturn ret;\ndiff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c\nindex c0baf53e97d8..9fc8faa33735 100644\n--- a/drivers/i2c/busses/i2c-designware-slave.c\n+++ b/drivers/i2c/busses/i2c-designware-slave.c\n@@ -21,48 +21,6 @@\n \n #include \"i2c-designware-core.h\"\n \n-static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)\n-{\n-\t/* Configure Tx/Rx FIFO threshold levels. */\n-\tregmap_write(dev->map, DW_IC_TX_TL, 0);\n-\tregmap_write(dev->map, DW_IC_RX_TL, 0);\n-\n-\t/* Configure the I2C slave. */\n-\tregmap_write(dev->map, DW_IC_CON, dev->slave_cfg);\n-\tregmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);\n-}\n-\n-/**\n- * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware\n- * @dev: device private data\n- *\n- * This function configures and enables the I2C in slave mode.\n- * This function is called during I2C init function, and in case of timeout at\n- * run time.\n- *\n- * Return: 0 on success, or negative errno otherwise.\n- */\n-static int i2c_dw_init_slave(struct dw_i2c_dev *dev)\n-{\n-\tint ret;\n-\n-\tret = i2c_dw_acquire_lock(dev);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Disable the adapter. */\n-\t__i2c_dw_disable(dev);\n-\n-\t/* Write SDA hold time if supported */\n-\tif (dev->sda_hold_time)\n-\t\tregmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);\n-\n-\ti2c_dw_configure_fifo_slave(dev);\n-\ti2c_dw_release_lock(dev);\n-\n-\treturn 0;\n-}\n-\n int i2c_dw_reg_slave(struct i2c_client *slave)\n {\n \tstruct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);\n@@ -232,8 +190,6 @@ int i2c_dw_probe_slave(struct dw_i2c_dev *dev)\n \tif (dev->flags & ACCESS_POLLING)\n \t\treturn -EOPNOTSUPP;\n \n-\tdev->init = i2c_dw_init_slave;\n-\n \treturn 0;\n }\n \n", "prefixes": [ "v2", "4/6" ] }