Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175593/?format=api
{ "id": 2175593, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175593/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218142621.57402-7-claudio.bantaloukas@arm.com>", "date": "2025-12-18T14:26:18", "name": "[v4,6/8] aarch64: add Multi-vector 8-bit floating-point multiply-add long", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "247f1daeebc4d0c9730fe4d0f550e8b6fac321a8", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-7-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485861, "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api", "date": "2025-12-18T14:26:12", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175593/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=ex2YIRFt;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=ex2YIRFt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=ex2YIRFt;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=ex2YIRFt", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com", "sourceware.org; spf=pass smtp.mailfrom=arm.com", "server2.sourceware.org;\n arc=pass smtp.remote-ip=40.107.159.65" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXCv839Lrz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 01:37:56 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 774384BA2E28\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 14:37:54 +0000 (GMT)", "from OSPPR02CU001.outbound.protection.outlook.com\n (mail-norwayeastazon11013065.outbound.protection.outlook.com [40.107.159.65])\n by sourceware.org (Postfix) with ESMTPS id A52CB4BA2E28\n for <gcc-patches@gcc.gnu.org>; Thu, 18 Dec 2025 14:28:34 +0000 (GMT)", "from CWXP123CA0013.GBRP123.PROD.OUTLOOK.COM (2603:10a6:401:73::25)\n by AS2PR08MB8381.eurprd08.prod.outlook.com (2603:10a6:20b:558::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 14:28:24 +0000", "from AM1PEPF000252E1.eurprd07.prod.outlook.com\n (2603:10a6:401:73:cafe::9d) by CWXP123CA0013.outlook.office365.com\n (2603:10a6:401:73::25) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.7 via Frontend Transport; Thu,\n 18 Dec 2025 14:28:18 +0000", "from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by\n AM1PEPF000252E1.mail.protection.outlook.com (10.167.16.59) with Microsoft\n SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6\n via Frontend Transport; Thu, 18 Dec 2025 14:28:22 +0000", "from CWLP265CA0458.GBRP265.PROD.OUTLOOK.COM (2603:10a6:400:1d4::18)\n by AS4PR08MB7783.eurprd08.prod.outlook.com (2603:10a6:20b:517::17)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.8; Thu, 18 Dec\n 2025 14:27:04 +0000", "from AMS1EPF00000048.eurprd04.prod.outlook.com\n (2603:10a6:400:1d4:cafe::58) by CWLP265CA0458.outlook.office365.com\n (2603:10a6:400:1d4::18) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.8 via Frontend Transport; Thu,\n 18 Dec 2025 14:26:48 +0000", "from nebula.arm.com (172.205.89.229) by\n AMS1EPF00000048.mail.protection.outlook.com (10.167.16.132) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9434.6 via Frontend Transport; Thu, 18 Dec 2025 14:27:04 +0000", "from AZ-NEU-EXJ02.Arm.com (10.240.25.139) by AZ-NEU-EX03.Arm.com\n (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 14:26:28 +0000", "from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EXJ02.Arm.com\n (10.240.25.139) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 14:26:28 +0000", "from e72c20ac6da1.eu-west-1.compute.internal (10.249.56.29) by\n mail.arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29 via Frontend\n Transport; Thu, 18 Dec 2025 14:26:28 +0000" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 774384BA2E28", "OpenDKIM Filter v2.11.0 sourceware.org A52CB4BA2E28" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org A52CB4BA2E28", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org A52CB4BA2E28", "ARC-Seal": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1766068115; cv=pass;\n b=b7vo/X8aBwjk3ExLqiSLuGGn6Hn/zWP13DzqzrknXVQw4fQMjfOiBWrP0A5TZqKctB4AWmctecPa+IcRJ10r7d1l/CBtHPWWP4VB8W0dUaZNUhexVVZx5l75TFo33E88tYrpy9k2Njn3C3+m84ABokMDlbDkzu1SHNtbxuBue7k=", "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=W151k/Idso85oICnQhPaFb8+M76suStwUYnnYDmoUWQQC6+4agMVeVbgeMEw3m0RAvJoVSJGBTjgY+CS7Kqp3p1PjRHeMc7j/NDTOX11+hAEOsiOvcKEm/Y6zMtuhvO3GWXCpsHt0guk7ypOEmOzATY2KQ79n1SuLmyQJNAT9jjMGL26Zd47D7Nv7Sl4FDbhMSqMHJectr1H9cZYRrHhj6zQD/+MQ/reznKapd+G3FxhmLkClzKXjin7fPf6dtZt3v8jRR5hrblhqytffXhosIQ07I84TAwA4CHAL/vCO5Y05A4hTeHvdHgQA++hi/jnwGKcRbD+lZeQSWrh6EqF8g==", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=vIfPURsn/iP/rZCGvAwqYyj4KXBeVCSO4w6T5i/4rccRlqPk5tTAaLvXyVQcNElgDmxewcdTweKJjebowwSONsrqCGt1CwC0I9reG1oNslORf0kZmTGMfxsJYti1XtMLGzoL7DVFhZKE20VWcbUdKlqKnOSibxCpW266XH6/pmALE3CJ6Kt1ai6iREZzsoNU1rLryVpwyvlN1JETIDVwPVEc7OT3zIrWpys9nEAsTdb71GyxFADJSaGR/LHuGhPmXcRgIxand7g1nBErnVZpbtOgL9FuMD9Gg4DBpaOCMOKbT+aybq/8D/zFRiymxkNSbKeCVeZC9xjR+MLxwGkhiQ==" ], "ARC-Message-Signature": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766068115; c=relaxed/simple;\n bh=6WuE9TvVWikkUJiefNYz/c09jCxP9uMxktA0y+YYWfE=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID:\n MIME-Version;\n b=YktSVgSbvZhSiaqILzyN7TfTRa2v2aoP6/NCYRkZH0ielPshMbSYgx0a5sa4JpeD2VWFJXaJnKnB9OCEkX+acwD+x8GaLcSG9L0sy/mHdTXIC5+r7hI5FotGgEeOoH5Fg0sNqpT8M6sXRaQEF6+AaTq6PDY8U1+qNyayJYKTF5c=", "i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/CghaLtT8ffXktTkPEzDPrtKXBgreEsKFj3j3K1k0dk=;\n b=gfbbi1LZ3J4V1/pUuvuoPEiAtveDLMY9G4zT+EO6VkwoOFizJR3kjA393bCrWdLcH6kGLumInezDn8k/Tt44MJPWoj9upBe+ZtUjHMRFYcofnb+1/luZpsC/e7RsGN0Um8bleGFLN3pem/bPl7uaR9hA8TVuUwzGdB+jtp96hfsWuxxQJKUGzwZremJEYwWJ74gG4J4PPJG4uzWqeEKbe+TsK+wzyoOPrxhQu/DS3iK1bm2IjBhbwn6Ss4lEJz/FyXPETh1Tz9r3et6hlxKFZYlybqEr/AUXAujKoHcZLF/vqO40rwXN8+rfzIqhGAcSJoI12VztGJDPKxc8s+j4gw==", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/CghaLtT8ffXktTkPEzDPrtKXBgreEsKFj3j3K1k0dk=;\n b=jc3GQBJEUIlcpf9omJaP9lV5xUSMB8HzukxMA5a87kk89+g2xStw/hCIl0aWCXp63B8MH7bMpkclYFmvnUHCmrmUNFBBfdjF7Ltf4hCmDl1rPEnStZ45iajart8Ig0dx+yg42IdLDK8AdYUVbx02IQJV5kJSiYNHbFqIauEIXaoSlBRjVm/4pJPfUlVvlQMwkrtI39qmeY0SDCW+cQiCpfL+X5giXU4AZ82wRv58TY057arjF1pVbFqziggMRKnoKTNhvCJM4CgJRGlHGW54F5RsUcu4ZuOk/U+4xgVbm2kwHfIaQcDdFY/QYUUgrr4qX0GO44g+EsK5IiTuasnXuQ==" ], "ARC-Authentication-Results": [ "i=3; server2.sourceware.org", "i=2; mx.microsoft.com 1; spf=pass (sender ip is\n 4.158.2.129) smtp.rcpttodomain=oss.qualcomm.com smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1\n spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com])", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 172.205.89.229) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/CghaLtT8ffXktTkPEzDPrtKXBgreEsKFj3j3K1k0dk=;\n b=ex2YIRFtzbywMnSSVg1egilFk280yjLQi+pvVxJWt5b7HUG/Pzr/GCvlm6S/I0kYl+QRPYVQ9hY9nId46So83xtkNA3F6dXfvXSLXTBS9pwrJls3/9gQLh9ik70r+v5boWufaWKRm/BbS6s/LcZSTyfnRhZiMytCFCHoR4ATvow=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/CghaLtT8ffXktTkPEzDPrtKXBgreEsKFj3j3K1k0dk=;\n b=ex2YIRFtzbywMnSSVg1egilFk280yjLQi+pvVxJWt5b7HUG/Pzr/GCvlm6S/I0kYl+QRPYVQ9hY9nId46So83xtkNA3F6dXfvXSLXTBS9pwrJls3/9gQLh9ik70r+v5boWufaWKRm/BbS6s/LcZSTyfnRhZiMytCFCHoR4ATvow=" ], "X-MS-Exchange-Authentication-Results": [ "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v4 6/8] aarch64: add Multi-vector 8-bit floating-point\n multiply-add long", "Date": "Thu, 18 Dec 2025 14:26:18 +0000", "Message-ID": "<20251218142621.57402-7-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AMS1EPF00000048:EE_|AS4PR08MB7783:EE_|AM1PEPF000252E1:EE_|AS2PR08MB8381:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5c87fd34-c2be-441e-216f-08de3e41b2b1", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|36860700013|1800799024|82310400026|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n G2dXM2C4lqZRvFN//JXigpIEZzflLe5eRaJEIiB+/H5NjTjXn40d6X/JEm5rgdDzndLy87LcBTFnwDpGI7CuEAVKRwgQQtSAJCnWmGeHVt6+EzC+2z4mRdbVq29ADtEChZCmDTkc7C4LX/HrbyzINJQfta63LD6kMjjlWrxz7TvEkFX4cVQrjvHYWXskCU3QEdXaJXY7OtoS+8s32yhkJn4T3BsGUQTB4IvVuCjXATkzjXgxIXsvMOUNsnnDnphZxVqQZMcXpB5Zldj2wDN4wJKGdRmO7TxSsnVQStWJ1+gOIJSJqGh/hThA6tlcRoWAqt8IbEJ5/+3z0Y3BlnCfqvLszmSG03I1mtuVtyPXjsomu/mDUqjAOQosAnbYUgHZS0L/l+VTN2T21omhlqXN0f8r5YOp1/mIoNFYfO+dicYl7/B4r7PYP/wFqCdkhhUHfa9cnO4tIY/jJJn//LtjUX9EBAyj9dLKzg4YrcBvlegWb/841paBgjRrZUJOTbJT8F2Xs9IiuT/hYtBsNlXMvvHtA+gEtuJ15Y5iXfpr9ps4p/zezdK+/a6LzRePgCn4SVeZbl19Ifio4a9ToeTqoFOG/YUez1zTZ+c+iQlmErxYxTyzrl/eB2PNUl59vHQ5ojhs4bjArvQc7HUtfL9/eLktrg+fx4uMWHZiA7D/1PGy3Cu0DJ08fu+mcF6tL31QHgEerkq1M/mZqYGhC2+ocje6qa7oVPrR5MWnJHJXpvyvUH//a1SDTqGF1+jd3Rb8LUjk/08dPmJLWweJPbO9ao1PZs48q0sYnuuj5kgL/TMVm+HxsdTqs/f62qW8z8TxLOElRTFExd8zY0qiiQ3RDjVDnFra1IO36j/yBQ4yNDWHnktiLiZjrYiy/iHXEl2mvArBcKTQwtW1jrEzQcJofyes5etRISet1bDJZV+j6TjHi/sB+DdgRWZLFKee7901zAm1uVyKs82OXcUz6cANcqhE4SMrhiF18mqmTpkhZcwqBeOXWRNBeD9J6UnAqjaDQeRptoiHiAXaGl93QHhoG48RwDGh1mdAAFbQ7XVELhpTt6AjLm7sgg/qZAyYh1qSb/nIw4COC1Lu/ctUbzw9AigS3YyCSgOrjWwj8R8ozL4LKxZAaZuz7mrRfTX41i3f+TbUk9lbtphtRccj1/H1BumuRLpbmZ8zJCBVv8yOw1rQju+XlmFwFmuo5BSQLcxKRdrCeGs1gJvDYpsDDm2VhZCk2/1UPKrJhGC9+s68QtX7180H/SBUqk3imctGLHgGuBBvgbiD8vp+GlMXp3Dp8YHFgBwZ+rEhHuOLeljiEG71jfuvp1kU2j0zxYRgyFA7YYU8Efx5c0O4hCC8RPBh20SdyrDn0uuZueTd+alg53HfMjoPxrgi1uHyAAZ4oSQ6E1Y9jelOqMLtX4yB5T+PkUyBZswvsyjLLk7IDgoGEb6fOdMWKPyHwHwyz5Yau9JJlBl6xpKRo2urmXO9S2YU/O2CLkYGT0PIuBsJoe5KtSncQZyF4JYx2QADbhBQRY4UoSk+uoXMQ2QwBzTlz7181TENzYOtLX4Hl5H72hHNRRY=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; CTRY:IE; LANG:en;\n SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent;\n CAT:NONE;\n SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(13003099007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [ "AS4PR08MB7783", "AS2PR08MB8381" ], "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n AM1PEPF000252E1.eurprd07.prod.outlook.com", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id-Prvs": "\n dcd0d776-d15f-4b16-eed6-08de3e418437", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|35042699022|82310400026|14060799003|376014|36860700013|1800799024|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n RzQGKv1pAw64bhwOxmC9ngFnqIeaZJL9PuvAAxrQo1f5cNshutlMfixJgK3Pq1Flcj4WaQWdIHNfhvvC9XC6+HRY1g9guSIQFDEC+UCuLuRNG+l10JxWUXzQA8NRig46UrUZL7AafzfV4f3nzdDtJBaUI4aeEDGA/fnKsHSxDGojNIQgs9mIB3cNk7X7sbESjOiNApWvLSSuPng32b69M+B1oCQoXAvmJ1oa7wNUM9ENUe+TjUhIBdvicGbrDYlVgReYqudi5fvCCNId7UmLUyjgAp19VzOYad3ek2eiAwiQ0J0q6PiRmShIMRxlc+VgIoqOKr1VMs6m1iA9EQ0HUdDN+lIyHYlbIUiQIO4L9RgyN8N7g6cdpV/dlJ5lHspp+VnIadsnY84wWAvH2sIVFuQmDoZcGpfTJwdQ3kJHf/xLwlGdnVjcu0AVablPQxvF2abmU3943e4PBshUaQxzEO9/DJzuFnvwY4wweZUzWETKu3EtkgDcon9pt3KbzscDQt4D/r+M7FNs5n9tvAw3iXdpF60v7izka9Qps/7cwv8Wt/rNZQ1UKQZDcczsOvFTvBne91XXoaQ3ZdEwTIt9ZcmTlllcy9dIV2eP/8D5rAJtqjl7KfACEAUkTFXX5dH5x067qYaEtnaBV02TzlK3ZRghczogAcAXGsE04rTKNgWmHoL4zhVO6eN9x8ZSJJ36kUbx5zxM53TyEHOqhU49YUzfrCy/YUAfeLdgfv4t3U52IS0pjTHEBaWieYm143YIsmU4nzvsc39P763sI6fQ6gNSJxGJY17mYhOxDXHmPt5M6PIFMIjZF3i/RYpnCkftQRFH6AdCBQ+7QeN7uzhfe7B8ga8JlQalVu7Bs8kcveS3nmND6dmL8K/sczMkOXLRR5yGTIFpekNlQoOyCpY/k3i1PX8FyCuN1cKwE1K/DS9q1fXYnT8gM1T2NWrmsXFWd0OeIccSd0Doq/GYwjtGqq+u9zBv5Tk3rSn3z3m0p/FAuMR4BUzPMJp053pVeVsPDUcczZQhxPHakJW2XBEWw8/sc9bWR7n3AJoWqWKmicWnn9vobD6Thumd2ZD4lzx3Mmap6s8hYlPokRLIZQtJnn0mST/V/q6pmcQdr/2NMsUXxScdhvedfEu7KjEOo62FmXiCOPxFoIBJwl5ybxvBqxrgOfwqZ/ZPANpkQM7Q/TJQJZ13udF1WITtM63bzRhVkOE8IjZjcjIeV7uk4jId4qk8qdfjYRcmaaKg9hEDNQNPL7WB2eZ6P9Ob9zqehLD+q9X3xDX2yaUrY0j/Fzxiq8kHanu92gaDd0s0yJNAgA/4Sqzi1S7MrNkGQwcBB0i8qn5s9cye6LyeiU65DLsEGjayP+a3uVtDNhL6ZGhnzbx2E/llQRFvAs3n2cICEwdiGsN74aEeLHCbyyTVZ2VJ9iDDw+qkVElK/u/Tzfhi2+2C3ul1q6AtCanVvvCrNqFoFIa8BkigBUV284HeuXY/dWijMOcKTJ84vmMTAiBvmXc/fCS1v5JY85W1DM4SjVsSJoiP2jPNj21WdQxo3f4v0O+6QNE910sTYUREfYbApGI=", "X-Forefront-Antispam-Report": "CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(35042699022)(82310400026)(14060799003)(376014)(36860700013)(1800799024)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 14:28:22.3919 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5c87fd34-c2be-441e-216f-08de3e41b2b1", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM1PEPF000252E1.eurprd07.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for the following intrinsics when sme-f8f16 is enabled:\n\t* svmla_lane_za16[_mf8]_vg2x1_fpm\n\t* svmla_lane_za16[_mf8]_vg2x2_fpm\n\t* svmla_lane_za16[_mf8]_vg2x4_fpm\n\t* svmla_za16[_mf8]_vg2x1_fpm\n\t* svmla[_single]_za16[_mf8]_vg2x2_fpm\n\t* svmla[_single]_za16[_mf8]_vg2x4_fpm\n\t* svmla_za16[_mf8]_vg2x2_fpm\n\t* svmla_za16[_mf8]_vg2x4_fpm\n\nThis patch adds support for the following intrinsics when sme-f8f32 is enabled:\n\t* svmla_lane_za32[_mf8]_vg4x1_fpm\n\t* svmla_lane_za32[_mf8]_vg4x2_fpm\n\t* svmla_lane_za32[_mf8]_vg4x4_fpm\n\t* svmla_za32[_mf8]_vg4x1_fpm\n\t* svmla[_single]_za32[_mf8]_vg4x2_fpm\n\t* svmla[_single]_za32[_mf8]_vg4x4_fpm\n\t* svmla_za32[_mf8]_vg4x2_fpm\n\t* svmla_za32[_mf8]_vg4x4_fpm\n\nAsm tests for the 32 bit versions follow the blueprint set in\nmla_lane_za32_u8_vg4x1.c mla_za32_u8_vg4x1.c and similar.\n16 bit versions follow similar patterns modulo differences in allowed offsets.\n\ngcc:\n\t* config/aarch64/aarch64-sme.md\n\t(@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>): Add\n\tnew define_insn.\n\t(*aarch64_sme_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus,\n\t*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus,\n\t@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>,\n\t*aarch64_sme_<optab><VNx8HI_ONLY:mode><VNx16QI_ONLY:mode>_plus,\n\t*aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx16QI_ONLY:mode>_plus,\n\t@aarch64_sme_single_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>,\n\t*aarch64_sme_single_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus,\n\t*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus,\n\t@aarch64_sme_lane_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x124:mode>,\n\t*aarch64_sme_lane_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x124:mode>,\n\t*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x124:mode>):\n\tLikewise.\n\t* config/aarch64/aarch64-sve-builtins-shapes.cc\n\t(struct binary_za_slice_lane_base): Support fpm argument.\n\t(struct binary_za_slice_opt_single_base): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sme.cc (svmla_za): Extend for fp8.\n\t(svmla_lane_za): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sme.def (svmla_lane): Add new\n\tDEF_SME_ZA_FUNCTION_GS_FPM entries.\n\t(svmla): Likewise.\n\t* config/aarch64/iterators.md (SME_ZA_F8F16_32): Add new mode iterator.\n\t(SME_ZA_FP8_x24, SME_ZA_FP8_x124): Likewise.\n\t(UNSPEC_SME_FMLAL): Add new unspec.\n\t(za16_offset_range): Add new mode_attr.\n\t(za16_32_long): Likewise.\n\t(za16_32_last_offset): Likewise.\n\t(SME_FP8_TERNARY_SLICE): Add new iterator.\n\t(optab): Add entry for UNSPEC_SME_FMLAL.\n\ngcc/testsuite:\n\n\t* gcc.target/aarch64/sme2/acle-asm/test_sme2_acle.h: (TEST_ZA_X1,\n\tTEST_ZA_XN, TEST_ZA_SINGLE, TEST_ZA_SINGLE_Z15, TEST_ZA_LANE,\n\tTEST_ZA_LANE_Z15): Add fpm0 parameter.\n\t* gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c: Add\n\ttests for variants accepting fpm.\n\t* gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c:\n\tLikewise.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c: New test.\n---\n gcc/config/aarch64/aarch64-sme.md | 241 +++++++++++++++\n .../aarch64/aarch64-sve-builtins-shapes.cc | 4 +-\n .../aarch64/aarch64-sve-builtins-sme.cc | 5 +-\n .../aarch64/aarch64-sve-builtins-sme.def | 8 +\n gcc/config/aarch64/iterators.md | 19 ++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c | 167 ++++++++++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c | 136 +++++++++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c | 142 +++++++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c | 169 ++++++++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c | 137 +++++++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c | 143 +++++++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x1.c | 167 ++++++++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x2.c | 285 +++++++++++++++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x4.c | 287 +++++++++++++++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x1.c | 167 ++++++++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x2.c | 277 +++++++++++++++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x4.c | 289 ++++++++++++++++++\n .../aarch64/sme2/acle-asm/test_sme2_acle.h | 12 +-\n .../acle/general-c/binary_za_slice_lane_1.c | 14 +\n .../general-c/binary_za_slice_opt_single_1.c | 16 +\n 20 files changed, 2675 insertions(+), 10 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md\nindex 632ef1e4774..e8301ae72a7 100644\n--- a/gcc/config/aarch64/aarch64-sme.md\n+++ b/gcc/config/aarch64/aarch64-sme.md\n@@ -1999,6 +1999,9 @@ (define_insn \"*aarch64_sme_lane_<optab><mode><mode>\"\n ;; - BFMLSL (SME2)\n ;; - FMLAL (SME2)\n ;; - FMLSL (SME2)\n+;; - FMLAL (multiple and indexed vector, FP8 to FP16 and FP8 to FP32, SME2)\n+;; - FMLAL (multiple and single vector, FP8 to FP16 and FP8 to FP32, SME2)\n+;; - FMLAL (multiple vectors, FP8 to FP16 and FP8 to FP32, SME2)\n ;; -------------------------------------------------------------------------\n \n (define_insn \"@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>\"\n@@ -2129,6 +2132,244 @@ (define_insn \"*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>\"\n }\n )\n \n+;; svmla_za16[_mf8]_vg2x2_fpm, svmla_za16[_mf8]_vg2x4_fpm\n+;; svmla_za32[_mf8]_vg4x2_fpm, svmla_za32[_mf8]_vg4x4_fpm\n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x24 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:SME_ZA_FP8_x24 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab><SME_ZA_F8F16_32:za16_32_long>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0:<SME_ZA_F8F16_32:za16_32_last_offset>, vgx<vector_count>], %1, %2\"\n+)\n+\n+;; svmla_za16[_mf8]_vg2x2_fpm, svmla_za16[_mf8]_vg2x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:VNx8HI_ONLY ZA_REGNUM)\n+\t(unspec:VNx8HI_ONLY\n+\t [(reg:VNx8HI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za16_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:SME_ZA_FP8_x24 3 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 1);\n+ return \"<optab>\\tza.h[%w0, %1:%4, vgx<vector_count>], %2, %3\";\n+ }\n+)\n+\n+;; svmla_za32[_mf8]_vg4x2_fpm, svmla_za32[_mf8]_vg4x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:VNx4SI_ONLY ZA_REGNUM)\n+\t(unspec:VNx4SI_ONLY\n+\t [(reg:VNx4SI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za32_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:SME_ZA_FP8_x24 3 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3);\n+ return \"<optab>l\\tza.s[%w0, %1:%4, vgx<vector_count>], %2, %3\";\n+ }\n+)\n+\n+;; svmla_za16[_mf8]_vg2x1_fpm, svmla_za32[_mf8]_vg4x1_fpm\n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:VNx16QI_ONLY 1 \"register_operand\" \"w\")\n+\t (match_operand:VNx16QI_ONLY 2 \"register_operand\" \"x\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab><SME_ZA_F8F16_32:za16_32_long>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0:<SME_ZA_F8F16_32:za16_32_last_offset><vg_modifier>], %1.b, %2.b\"\n+)\n+\n+;; svmla_za16[_mf8]_vg2x1_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_<optab><VNx8HI_ONLY:mode><VNx16QI_ONLY:mode>_plus\"\n+ [(set (reg:VNx8HI_ONLY ZA_REGNUM)\n+\t(unspec:VNx8HI_ONLY\n+\t [(reg:VNx8HI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<VNx16QI_ONLY:za32_offset_range>_operand\"))\n+\t (match_operand:VNx16QI_ONLY 2 \"register_operand\" \"w\")\n+\t (match_operand:VNx16QI_ONLY 3 \"register_operand\" \"x\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 1);\n+ return \"<optab>\\tza.h[%w0, %1:%4<vg_modifier>], %2.b, %3.b\";\n+ }\n+)\n+\n+;; svmla_za32[_mf8]_vg4x1_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx16QI_ONLY:mode>_plus\"\n+ [(set (reg:VNx4SI_ONLY ZA_REGNUM)\n+\t(unspec:VNx4SI_ONLY\n+\t [(reg:VNx4SI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za32_offset_range>_operand\"))\n+\t (match_operand:VNx16QI_ONLY 2 \"register_operand\" \"w\")\n+\t (match_operand:VNx16QI_ONLY 3 \"register_operand\" \"x\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3);\n+ return \"<optab>l\\tza.s[%w0, %1:%4<vg_modifier>], %2.b, %3.b\";\n+ }\n+)\n+\n+;; svmla[_single]_za16[_mf8]_vg2x2_fpm, svmla[_single]_za16[_mf8]_vg2x4_fpm,\n+;; svmla[_single]_za32[_mf8]_vg4x2_fpm, svmla[_single]_za32[_mf8]_vg4x4_fpm\n+(define_insn \"@aarch64_sme_single_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x24 1 \"register_operand\" \"w\")\n+\t (vec_duplicate:SME_ZA_FP8_x24\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 2 \"register_operand\" \"x\"))\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab><SME_ZA_F8F16_32:za16_32_long>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0:<SME_ZA_F8F16_32:za16_32_last_offset>, vgx<vector_count>], %1, %2.b\"\n+)\n+\n+;; svmla[_single]_za16[_mf8]_vg2x2_fpm, svmla[_single]_za16[_mf8]_vg2x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_single_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:VNx8HI_ONLY ZA_REGNUM)\n+\t(unspec:VNx8HI_ONLY\n+\t [(reg:VNx8HI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za16_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24 2 \"register_operand\" \"w\")\n+\t (vec_duplicate:SME_ZA_FP8_x24\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 3 \"register_operand\" \"x\"))\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 1);\n+ return \"<optab>\\tza.h[%w0, %1:%4, vgx<vector_count>], %2, %3.b\";\n+ }\n+)\n+\n+;; svmla[_single]_za32[_mf8]_vg4x2_fpm, svmla[_single]_za32[_mf8]_vg4x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:VNx4SI_ONLY ZA_REGNUM)\n+\t(unspec:VNx4SI_ONLY\n+\t [(reg:VNx4SI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za32_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24 2 \"register_operand\" \"w\")\n+\t (vec_duplicate:SME_ZA_FP8_x24\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 3 \"register_operand\" \"x\"))\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ {\n+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3);\n+ return \"<optab>l\\tza.s[%w0, %1:%4, vgx<vector_count>], %2, %3.b\";\n+ }\n+)\n+\n+;; svmla_lane_za16[_mf8]_vg2x1_fpm, svmla_lane_za32[_mf8]_vg4x1_fpm,\n+;; svmla_lane_za16[_mf8]_vg2x2_fpm, svmla_lane_za32[_mf8]_vg4x2_fpm,\n+;; svmla_lane_za16[_mf8]_vg2x4_fpm, svmla_lane_za32[_mf8]_vg4x4_fpm\n+(define_insn \"@aarch64_sme_lane_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x124:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x124 1 \"<SME_ZA_FP8_x124:aligned_operand>\" \"<SME_ZA_FP8_x124:aligned_fpr>\")\n+\t (unspec:SME_ZA_FP8_x124\n+\t [(match_operand:<SME_ZA_FP8_x124:VSINGLE> 2 \"register_operand\" \"x\")\n+\t (match_operand:SI 3 \"const_int_operand\")]\n+\t UNSPEC_SVE_LANE_SELECT)\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab><SME_ZA_F8F16_32:za16_32_long>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0:<SME_ZA_F8F16_32:za16_32_last_offset><SME_ZA_FP8_x124:vg_modifier>], %1<SME_ZA_FP8_x124:z_suffix>, %2.b[%3]\"\n+)\n+\n+;; svmla_lane_za16[_mf8]_vg2x1_fpm, svmla_lane_za16[_mf8]_vg2x2_fpm,\n+;; svmla_lane_za16[_mf8]_vg2x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_lane_<optab><VNx8HI_ONLY:mode><SME_ZA_FP8_x124:mode>\"\n+ [(set (reg:VNx8HI_ONLY ZA_REGNUM)\n+\t(unspec:VNx8HI_ONLY\n+\t [(reg:VNx8HI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za16_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x124 2 \"<SME_ZA_FP8_x124:aligned_operand>\" \"<SME_ZA_FP8_x124:aligned_fpr>\")\n+\t (unspec:SME_ZA_FP8_x124\n+\t [(match_operand:<SME_ZA_FP8_x124:VSINGLE> 3 \"register_operand\" \"x\")\n+\t (match_operand:SI 4 \"const_int_operand\")]\n+\t UNSPEC_SVE_LANE_SELECT)\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ {\n+ operands[5] = GEN_INT (INTVAL (operands[1]) + 1);\n+ return \"<optab>\\tza.h[%w0, %1:%5<SME_ZA_FP8_x124:vg_modifier>], %2<SME_ZA_FP8_x124:z_suffix>, %3.b[%4]\";\n+ }\n+)\n+\n+;; svmla_lane_za32[_mf8]_vg4x1_fpm, svmla_lane_za32[_mf8]_vg4x2_fpm,\n+;; svmla_lane_za32[_mf8]_vg4x4_fpm (slice variable + offset)\n+(define_insn \"*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x124:mode>\"\n+ [(set (reg:VNx4SI_ONLY ZA_REGNUM)\n+\t(unspec:VNx4SI_ONLY\n+\t [(reg:VNx4SI_ONLY ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_<za32_offset_range>_operand\"))\n+\t (match_operand:SME_ZA_FP8_x124 2 \"<aligned_operand>\" \"<aligned_fpr>\")\n+\t (unspec:SME_ZA_FP8_x124\n+\t [(match_operand:<VSINGLE> 3 \"register_operand\" \"x\")\n+\t (match_operand:SI 4 \"const_int_operand\")]\n+\t UNSPEC_SVE_LANE_SELECT)\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_TERNARY_SLICE))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ {\n+ operands[5] = GEN_INT (INTVAL (operands[1]) + 3);\n+ return \"<optab>l\\tza.s[%w0, %1:%5<SME_ZA_FP8_x124:vg_modifier>], %2<z_suffix>, %3.b[%4]\";\n+ }\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP] Sum of outer products\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\nindex b315dc91cc7..59f313d08f2 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n@@ -729,7 +729,7 @@ struct binary_za_slice_lane_base : public overloaded_base<1>\n resolve (function_resolver &r) const override\n {\n sve_type type;\n- if (!r.check_num_arguments (4)\n+ if (!r.check_num_arguments (r.fpm_mode == FPM_set ? 5: 4)\n \t|| !r.require_scalar_type (0, \"uint32_t\")\n \t|| !(type = r.infer_tuple_type (1))\n \t|| !r.require_derived_vector_type (2, 1, type, TCLASS)\n@@ -758,7 +758,7 @@ struct binary_za_slice_opt_single_base : public overloaded_base<1>\n resolve (function_resolver &r) const override\n {\n sve_type type;\n- if (!r.check_num_arguments (3)\n+ if (!r.check_num_arguments (r.fpm_mode == FPM_set ? 4: 3)\n \t|| !r.require_scalar_type (0, \"uint32_t\")\n \t|| !(type = r.infer_tuple_type (1)))\n return error_mark_node;\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\nindex 4657e29ad64..43ef05c673a 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n@@ -640,10 +640,11 @@ FUNCTION (svluti2_lane_zt, svluti_lane_zt_impl, (2))\n FUNCTION (svluti4_lane_zt, svluti_lane_zt_impl, (4))\n FUNCTION (svluti4_zt, svluti_zt_impl, (4))\n FUNCTION (svmla_za, sme_2mode_function, (UNSPEC_SME_SMLA, UNSPEC_SME_UMLA,\n-\t\t\t\t\t UNSPEC_SME_FMLA))\n+\t\t\t\t\t UNSPEC_SME_FMLA, UNSPEC_SME_FMLAL))\n FUNCTION (svmla_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SMLA,\n \t\t\t\t\t\t UNSPEC_SME_UMLA,\n-\t\t\t\t\t\t UNSPEC_SME_FMLA))\n+\t\t\t\t\t\t UNSPEC_SME_FMLA,\n+\t\t\t\t\t\t UNSPEC_SME_FMLAL))\n FUNCTION (svmls_za, sme_2mode_function, (UNSPEC_SME_SMLS, UNSPEC_SME_UMLS,\n \t\t\t\t\t UNSPEC_SME_FMLS))\n FUNCTION (svmls_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SMLS,\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\nindex c86d5fa730b..f9ad6837f44 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n@@ -266,9 +266,17 @@ DEF_SME_FUNCTION_GS (svluti4_zt, luti4_zt, b_integer, x4, none)\n #undef REQUIRED_EXTENSIONS\n \n #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F16)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_h_mf8,\n+\t\t\t vg2, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg2, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg1x24, none, set)\n #undef REQUIRED_EXTENSIONS\n \n #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_s_mf8,\n+\t\t\t vg4, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg4, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg1x24, none, set)\n #undef REQUIRED_EXTENSIONS\n \n #undef DEF_SME_ZA_FUNCTION\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex a98f514b8ec..0a093a1b49c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -758,6 +758,13 @@ (define_mode_iterator SME_ZA_BHIx24 [VNx32QI VNx64QI VNx16HI VNx32HI])\n (define_mode_iterator SME_ZA_HFx124 [VNx8BF VNx16BF VNx32BF\n \t\t\t\t VNx8HF VNx16HF VNx32HF])\n \n+(define_mode_iterator SME_ZA_F8F16_32 [(VNx8HI \"TARGET_STREAMING_SME_F8F16\")\n+\t\t\t\t (VNx4SI \"TARGET_STREAMING_SME_F8F32\")])\n+\n+(define_mode_iterator SME_ZA_FP8_x24 [VNx32QI VNx64QI])\n+\n+(define_mode_iterator SME_ZA_FP8_x124 [VNx16QI VNx32QI VNx64QI])\n+\n (define_mode_iterator SME_ZA_HFx24 [VNx16BF VNx32BF VNx16HF VNx32HF])\n \n (define_mode_iterator SME_ZA_HIx124 [VNx8HI VNx16HI VNx32HI])\n@@ -1265,6 +1272,7 @@ (define_c_enum \"unspec\"\n UNSPEC_SME_FDOT\n UNSPEC_SME_FVDOT\n UNSPEC_SME_FMLA\n+ UNSPEC_SME_FMLAL\n UNSPEC_SME_FMLS\n UNSPEC_SME_FMOPA\n UNSPEC_SME_FMOPS\n@@ -2682,6 +2690,10 @@ (define_mode_attr FCMLA_maybe_lane [(V2SF \"<Vtype>\") (V4SF \"<Vetype>[%4]\")\n \t\t\t\t (V4HF \"<Vetype>[%4]\") (V8HF \"<Vetype>[%4]\")\n \t\t\t\t ])\n \n+(define_mode_attr za16_offset_range [(VNx16QI \"0_to_14_step_2\")\n+\t\t\t\t (VNx32QI \"0_to_6_step_2\")\n+\t\t\t\t (VNx64QI \"0_to_6_step_2\")])\n+\n (define_mode_attr za32_offset_range [(VNx16QI \"0_to_12_step_4\")\n \t\t\t\t (VNx8BF \"0_to_14_step_2\")\n \t\t\t\t (VNx8HF \"0_to_14_step_2\")\n@@ -2702,6 +2714,10 @@ (define_mode_attr za64_offset_range [(VNx8HI \"0_to_12_step_4\")\n (define_mode_attr za32_long [(VNx16QI \"ll\") (VNx32QI \"ll\") (VNx64QI \"ll\")\n \t\t\t (VNx8HI \"l\") (VNx16HI \"l\") (VNx32HI \"l\")])\n \n+(define_mode_attr za16_32_long [(VNx4SI \"l\")(VNx8HI \"\")])\n+\n+(define_mode_attr za16_32_last_offset [(VNx4SI \"3\")(VNx8HI \"1\")])\n+\n (define_mode_attr za32_last_offset [(VNx16QI \"3\") (VNx32QI \"3\") (VNx64QI \"3\")\n \t\t\t\t (VNx8HI \"1\") (VNx16HI \"1\") (VNx32HI \"1\")])\n \n@@ -4049,6 +4065,8 @@ (define_int_iterator SME_INT_TERNARY_SLICE [UNSPEC_SME_SMLA UNSPEC_SME_SMLS\n \n (define_int_iterator SME_FP_TERNARY_SLICE [UNSPEC_SME_FMLA UNSPEC_SME_FMLS])\n \n+(define_int_iterator SME_FP8_TERNARY_SLICE [UNSPEC_SME_FMLAL])\n+\n ;; Iterators for atomic operations.\n \n (define_int_iterator ATOMIC_LDOP\n@@ -4198,6 +4216,7 @@ (define_int_attr optab [(UNSPEC_ANDF \"and\")\n \t\t\t(UNSPEC_SME_FDOT \"fdot\")\n \t\t\t(UNSPEC_SME_FVDOT \"fvdot\")\n \t\t\t(UNSPEC_SME_FMLA \"fmla\")\n+\t\t\t(UNSPEC_SME_FMLAL \"fmlal\")\n \t\t\t(UNSPEC_SME_FMLS \"fmls\")\n \t\t\t(UNSPEC_SME_FMOPA \"fmopa\")\n \t\t\t(UNSPEC_SME_FMOPS \"fmops\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c\nnew file mode 100644\nindex 00000000000..0d500c15e56\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c\n@@ -0,0 +1,167 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f16\"\n+\n+/*\n+** mla_lane_0_z0_z0_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z0\\.b\\[0\\]\n+**\tret\n+*/\n+\n+TEST_ZA_X1 (mla_lane_0_z0_z0_0, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (0, z0, z0, 0, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (0, z0, z0, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z3_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w0_z0_z3_1, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w0, z0, z3, 1, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w0, z0, z3, 1, fpm0))\n+\n+/*\n+** mla_lane_w7_z0_z3_2:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w7\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w7_z0_z3_2, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w7, z0, z3, 2, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w7, z0, z3, 2, fpm0))\n+\n+/*\n+** mla_lane_w8_z7_z3_3:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1\\], z7\\.b, z3\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8_z7_z3_3, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8, z7, z3, 3, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8, z7, z3, 3, fpm0))\n+\n+/*\n+** mla_lane_w8_z31_z16_4:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfmlal\tza\\.h\\[w8, 0:1\\], z31\\.b. \\1\\.b\\[4\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8_z31_z16_4, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8, z31, z16, 4, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8, z31, z16, 4, fpm0))\n+\n+/*\n+** mla_lane_w8p1_z0_z0_5:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z0\\.b\\[5\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p1_z0_z0_5, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 1, z0, z0, 5, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 1, z0, z0, 5, fpm0))\n+\n+/*\n+** mla_lane_w8p2_z23_z0_6:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 2:3\\], z23\\.b, z0\\.b\\[6\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p2_z23_z0_6, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 2, z23, z0, 6, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 2, z23, z0, 6, fpm0))\n+\n+/*\n+** mla_lane_w11p6_z23_z0_7:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 6:7\\], z23\\.b, z0\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w11p6_z23_z0_7, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w11 + 6, z23, z0, 7, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w11 + 6, z23, z0, 7, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z7_z7_8:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z7\\.b, z7\\.b\\[8\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p7_z7_z7_8, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 7, z7, z7, 8, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 7, z7, z7, 8, fpm0))\n+\n+/*\n+** mla_lane_w11p12_z23_z0_7:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 12:13\\], z23\\.b, z0\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w11p12_z23_z0_7, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w11 + 12, z23, z0, 7, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w11 + 12, z23, z0, 7, fpm0))\n+\n+/*\n+** mla_lane_w8p14_z23_z0_10:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 14:15\\], z23\\.b, z0\\.b\\[10\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p14_z23_z0_10, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 14, z23, z0, 10, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 14, z23, z0, 10, fpm0))\n+\n+/*\n+** mla_lane_w8p15_z7_z7_11:\n+**\tadd\t(w8|w9|w10|w11), w8, #?15\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z7\\.b, z7\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p15_z7_z7_11, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 15, z7, z7, 11, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 15, z7, z7, 11, fpm0))\n+\n+/*\n+** mla_lane_w8p16_z7_z7_12:\n+**\tadd\t(w8|w9|w10|w11), w8, #?16\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z7\\.b, z7\\.b\\[12\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p16_z7_z7_12, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 + 16, z7, z7, 12, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 + 16, z7, z7, 12, fpm0))\n+\n+/*\n+** mla_lane_w8m1_z16_z0_13:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z16\\.b, z0\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8m1_z16_z0_13, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w8 - 1, z16, z0, 13, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w8 - 1, z16, z0, 13, fpm0))\n+\n+/*\n+** mla_lane_w12_z0_z3_15:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w12\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w12_z0_z3_15, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x1_fpm (w12, z0, z3, 15, fpm0),\n+\t svmla_lane_za16_vg2x1_fpm (w12, z0, z3, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c\nnew file mode 100644\nindex 00000000000..bba907e6dbc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c\n@@ -0,0 +1,136 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme-f8f16\"\n+\n+/*\n+** mla_lane_0_z0_z4_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (0, z0, z4, 0, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z7_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w0, z0, z7, 1, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z4_2:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8, z28, z4, 2, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** mla_lane_w11p2_z0_z4_3:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 2:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w11p2_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w11 + 2, z0, z4, 3, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w11 + 2, z0, z4, 3, fpm0))\n+\n+/*\n+** mla_lane_w8p6_z0_z4_4:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 6:7, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[4\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p6_z0_z4_4, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8 + 6, z0, z4, 4, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8 + 6, z0, z4, 4, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z0_z4_5:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[5\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p7_z0_z4_5, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8 + 7, z0, z4, 5, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8 + 7, z0, z4, 5, fpm0))\n+\n+/*\n+** mla_lane_w8p8_z0_z4_7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p8_z0_z4_7, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8 + 8, z0, z4, 7, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8 + 8, z0, z4, 7, fpm0))\n+\n+/*\n+** mla_lane_w0m1_z0_z4_9:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[9\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0m1_z0_z4_9, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w0 - 1, z0, z4, 9, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w0 - 1, z0, z4, 9, fpm0))\n+\n+/*\n+** mla_lane_w8_z4_z15_10:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z4\\.b - z5\\.b}, z15\\.b\\[10\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (mla_lane_w8_z4_z15_10, svmfloat8x2_t, svmfloat8_t,\n+\t\t svmla_lane_za16_mf8_vg2x2_fpm (w8, z4, z15, 10, fpm0),\n+\t\t svmla_lane_za16_vg2x2_fpm (w8, z4, z15, 10, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z16_11:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z28\\.b - z29\\.b}, \\1\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z16_11, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8, z28, z16, 11, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8, z28, z16, 11, fpm0))\n+\n+/*\n+** mla_lane_w8_z17_z7_13:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], [^\\n]+, z7\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z17_z7_13, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8, z17, z7, 13, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8, z17, z7, 13, fpm0))\n+\n+/*\n+** mla_lane_w8_z22_z4_15:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z22\\.b - z23\\.b}, z4\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z22_z4_15, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x2_fpm (w8, z22, z4, 15, fpm0),\n+\t svmla_lane_za16_vg2x2_fpm (w8, z22, z4, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c\nnew file mode 100644\nindex 00000000000..bdce691bc81\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c\n@@ -0,0 +1,142 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme-f8f16\"\n+\n+/*\n+** mla_lane_0_z0_z4_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_0_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (0, z0, z4, 0, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z7_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0_z0_z7_1, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z4_2:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z4_2, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** mla_lane_w11p2_z0_z4_7:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 2:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w11p2_z0_z4_7, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w11 + 2, z0, z4, 7, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w11 + 2, z0, z4, 7, fpm0))\n+\n+/*\n+** mla_lane_w8p6_z0_z4_8:\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 6:7, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[8\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p6_z0_z4_8, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8 + 6, z0, z4, 8, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8 + 6, z0, z4, 8, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z0_z4_9:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[9\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p7_z0_z4_9, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8 + 7, z0, z4, 9, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8 + 7, z0, z4, 9, fpm0))\n+\n+/*\n+** mla_lane_w8p8_z0_z4_10:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[10\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p8_z0_z4_10, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8 + 8, z0, z4, 10, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8 + 8, z0, z4, 10, fpm0))\n+\n+/*\n+** mla_lane_w0m1_z0_z4_11:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0m1_z0_z4_11, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w0 - 1, z0, z4, 11, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w0 - 1, z0, z4, 11, fpm0))\n+\n+/*\n+** mla_lane_w8_z4_z15_12:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+** \tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z4\\.b - z7\\.b}, z15\\.b\\[12\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (mla_lane_w8_z4_z15_12, svmfloat8x4_t, svmfloat8_t,\n+\t\t svmla_lane_za16_mf8_vg2x4_fpm (w8, z4, z15, 12, fpm0),\n+\t\t svmla_lane_za16_vg2x4_fpm (w8, z4, z15, 12, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z16_13:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z28\\.b - z31\\.b}, \\1\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z16_13, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8, z28, z16, 13, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8, z28, z16, 13, fpm0))\n+\n+/*\n+** mla_lane_w8_z17_z7_14:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], [^\\n]+, z7\\.b\\[14\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z17_z7_14, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8, z17, z7, 14, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8, z17, z7, 14, fpm0))\n+\n+/*\n+** mla_lane_w8_z22_z4_15:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], [^\\n]+, z4\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z22_z4_15, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za16_mf8_vg2x4_fpm (w8, z22, z4, 15, fpm0),\n+\t svmla_lane_za16_vg2x4_fpm (w8, z22, z4, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c\nnew file mode 100644\nindex 00000000000..3dc3ff72110\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c\n@@ -0,0 +1,169 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f32\"\n+\n+/*\n+** mla_lane_0_z0_z0_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z0\\.b\\[0\\]\n+**\tret\n+*/\n+\n+TEST_ZA_X1 (mla_lane_0_z0_z0_0, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (0, z0, z0, 0, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (0, z0, z0, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z3_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w0_z0_z3_1, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w0, z0, z3, 1, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w0, z0, z3, 1, fpm0))\n+\n+/*\n+** mla_lane_w7_z0_z3_2:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w7\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w7_z0_z3_2, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w7, z0, z3, 2, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w7, z0, z3, 2, fpm0))\n+\n+/*\n+** mla_lane_w8_z7_z3_3:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3\\], z7\\.b, z3\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8_z7_z3_3, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8, z7, z3, 3, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8, z7, z3, 3, fpm0))\n+\n+/*\n+** mla_lane_w8_z31_z16_4:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfmlall\tza\\.s\\[w8, 0:3\\], z31\\.b. \\1\\.b\\[4\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8_z31_z16_4, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8, z31, z16, 4, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8, z31, z16, 4, fpm0))\n+\n+/*\n+** mla_lane_w8p1_z0_z0_5:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z0\\.b\\[5\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p1_z0_z0_5, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 1, z0, z0, 5, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 1, z0, z0, 5, fpm0))\n+\n+/*\n+** mla_lane_w8p2_z23_z0_6:\n+**\tadd\t(w8|w9|w10|w11), w8, #?2\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z23\\.b, z0\\.b\\[6\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p2_z23_z0_6, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 2, z23, z0, 6, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 2, z23, z0, 6, fpm0))\n+\n+/*\n+** mla_lane_w11p4_z23_z0_7:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7\\], z23\\.b, z0\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w11p4_z23_z0_7, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w11 + 4, z23, z0, 7, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w11 + 4, z23, z0, 7, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z7_z7_8:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z7\\.b, z7\\.b\\[8\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p7_z7_z7_8, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 7, z7, z7, 8, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 7, z7, z7, 8, fpm0))\n+\n+/*\n+** mla_lane_w11p12_z23_z0_9:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 12:15\\], z23\\.b, z0\\.b\\[9\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w11p12_z23_z0_9, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w11 + 12, z23, z0, 9, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w11 + 12, z23, z0, 9, fpm0))\n+\n+/*\n+** mla_lane_w8p14_z23_z0_10:\n+**\tadd\t(w8|w9|w10|w11), w8, #?14\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3\\], z23\\.b, z0\\.b\\[10\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p14_z23_z0_10, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 14, z23, z0, 10, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 14, z23, z0, 10, fpm0))\n+\n+/*\n+** mla_lane_w8p15_z7_z7_11:\n+**\tadd\t(w8|w9|w10|w11), w8, #?15\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z7\\.b, z7\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p15_z7_z7_11, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 15, z7, z7, 11, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 15, z7, z7, 11, fpm0))\n+\n+/*\n+** mla_lane_w8p16_z7_z7_12:\n+**\tadd\t(w8|w9|w10|w11), w8, #?16\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z7\\.b, z7\\.b\\[12\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8p16_z7_z7_12, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 + 16, z7, z7, 12, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 + 16, z7, z7, 12, fpm0))\n+\n+/*\n+** mla_lane_w8m1_z16_z0_13:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z16\\.b, z0\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w8m1_z16_z0_13, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w8 - 1, z16, z0, 13, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w8 - 1, z16, z0, 13, fpm0))\n+\n+/*\n+** mla_lane_w12_z0_z3_15:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w12\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_lane_w12_z0_z3_15, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x1_fpm (w12, z0, z3, 15, fpm0),\n+\t svmla_lane_za32_vg4x1_fpm (w12, z0, z3, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c\nnew file mode 100644\nindex 00000000000..7717aabfd2a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c\n@@ -0,0 +1,137 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme-f8f32\"\n+\n+/*\n+** mla_lane_0_z0_z4_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (0, z0, z4, 0, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z7_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w0, z0, z7, 1, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z4_2:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8, z28, z4, 2, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** mla_lane_w11p4_z0_z4_3:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w11p4_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w11 + 4, z0, z4, 3, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w11 + 4, z0, z4, 3, fpm0))\n+\n+/*\n+** mla_lane_w8p6_z0_z4_4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?6\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[4\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p6_z0_z4_4, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8 + 6, z0, z4, 4, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8 + 6, z0, z4, 4, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z0_z4_5:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[5\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p7_z0_z4_5, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8 + 7, z0, z4, 5, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8 + 7, z0, z4, 5, fpm0))\n+\n+/*\n+** mla_lane_w8p8_z0_z4_7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p8_z0_z4_7, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8 + 8, z0, z4, 7, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8 + 8, z0, z4, 7, fpm0))\n+\n+/*\n+** mla_lane_w0m1_z0_z4_9:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[9\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0m1_z0_z4_9, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w0 - 1, z0, z4, 9, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w0 - 1, z0, z4, 9, fpm0))\n+\n+/*\n+** mla_lane_w8_z4_z15_10:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z4\\.b - z5\\.b}, z15\\.b\\[10\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (mla_lane_w8_z4_z15_10, svmfloat8x2_t, svmfloat8_t,\n+\t\t svmla_lane_za32_mf8_vg4x2_fpm (w8, z4, z15, 10, fpm0),\n+\t\t svmla_lane_za32_vg4x2_fpm (w8, z4, z15, 10, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z16_11:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z28\\.b - z29\\.b}, \\1\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z16_11, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8, z28, z16, 11, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8, z28, z16, 11, fpm0))\n+\n+/*\n+** mla_lane_w8_z17_z7_13:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], [^\\n]+, z7\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z17_z7_13, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8, z17, z7, 13, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8, z17, z7, 13, fpm0))\n+\n+/*\n+** mla_lane_w8_z22_z4_15:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z22\\.b - z23\\.b}, z4\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z22_z4_15, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x2_fpm (w8, z22, z4, 15, fpm0),\n+\t svmla_lane_za32_vg4x2_fpm (w8, z22, z4, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c\nnew file mode 100644\nindex 00000000000..159b1048c84\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c\n@@ -0,0 +1,143 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme-f8f32\"\n+\n+/*\n+** mla_lane_0_z0_z4_0:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_0_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (0, z0, z4, 0, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** mla_lane_w0_z0_z7_1:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0_z0_z7_1, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z4_2:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z4_2, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** mla_lane_w11p4_z0_z4_7:\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[7\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w11p4_z0_z4_7, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w11 + 4, z0, z4, 7, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w11 + 4, z0, z4, 7, fpm0))\n+\n+/*\n+** mla_lane_w8p6_z0_z4_8:\n+**\tadd\t(w8|w9|w10|w11), w8, #?6\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[8\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p6_z0_z4_8, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8 + 6, z0, z4, 8, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8 + 6, z0, z4, 8, fpm0))\n+\n+/*\n+** mla_lane_w8p7_z0_z4_9:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[9\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p7_z0_z4_9, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8 + 7, z0, z4, 9, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8 + 7, z0, z4, 9, fpm0))\n+\n+/*\n+** mla_lane_w8p8_z0_z4_10:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[10\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8p8_z0_z4_10, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8 + 8, z0, z4, 10, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8 + 8, z0, z4, 10, fpm0))\n+\n+/*\n+** mla_lane_w0m1_z0_z4_11:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[11\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w0m1_z0_z4_11, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w0 - 1, z0, z4, 11, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w0 - 1, z0, z4, 11, fpm0))\n+\n+/*\n+** mla_lane_w8_z4_z15_12:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+** \tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z4\\.b - z7\\.b}, z15\\.b\\[12\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (mla_lane_w8_z4_z15_12, svmfloat8x4_t, svmfloat8_t,\n+\t\t svmla_lane_za32_mf8_vg4x4_fpm (w8, z4, z15, 12, fpm0),\n+\t\t svmla_lane_za32_vg4x4_fpm (w8, z4, z15, 12, fpm0))\n+\n+/*\n+** mla_lane_w8_z28_z16_13:\n+** \tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z28\\.b - z31\\.b}, \\1\\.b\\[13\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z28_z16_13, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8, z28, z16, 13, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8, z28, z16, 13, fpm0))\n+\n+/*\n+** mla_lane_w8_z17_z7_14:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], [^\\n]+, z7\\.b\\[14\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z17_z7_14, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8, z17, z7, 14, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8, z17, z7, 14, fpm0))\n+\n+/*\n+** mla_lane_w8_z22_z4_15:\n+** \tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], [^\\n]+, z4\\.b\\[15\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (mla_lane_w8_z22_z4_15, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_lane_za32_mf8_vg4x4_fpm (w8, z22, z4, 15, fpm0),\n+\t svmla_lane_za32_vg4x4_fpm (w8, z22, z4, 15, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c\nnew file mode 100644\nindex 00000000000..1c67705ab6c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c\n@@ -0,0 +1,167 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f16\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_0_z0_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (0, z0, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w0_z0_z3, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w0, z0, z3, fpm0),\n+\t svmla_za16_vg2x1_fpm (w0, z0, z3, fpm0))\n+\n+/*\n+** mla_w7_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w7\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w7_z0_z3, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w7, z0, z3, fpm0),\n+\t svmla_za16_vg2x1_fpm (w7, z0, z3, fpm0))\n+\n+/*\n+** mla_w8_z7_z3:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1\\], z7\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8_z7_z3, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8, z7, z3, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8, z7, z3, fpm0))\n+\n+/*\n+** mla_w8_z31_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfmlal\tza\\.h\\[w8, 0:1\\], z31\\.b. \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8_z31_z16, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8, z31, z16, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8, z31, z16, fpm0))\n+\n+/*\n+** mla_w8p1_z0_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p1_z0_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8 + 1, z0, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8 + 1, z0, z0, fpm0))\n+\n+/*\n+** mla_w10p4_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w10, 4:5\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w10p4_z23_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w10 + 4, z23, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w10 + 4, z23, z0, fpm0))\n+\n+/*\n+** mla_w11p6_z23_z0:\n+**\tadd\t(w8|w9|w10|w11), w11, #?6\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w11p6_z23_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w11 + 6, z23, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w11 + 6, z23, z0, fpm0))\n+\n+/*\n+** mla_w9p8_z7_z7:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w9, 8:9\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w9p8_z7_z7, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w9 + 8, z7, z7, fpm0),\n+\t svmla_za16_vg2x1_fpm (w9 + 8, z7, z7, fpm0))\n+\n+/*\n+** mla_w11p12_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 12:13\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w11p12_z23_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w11 + 12, z23, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w11 + 12, z23, z0, fpm0))\n+\n+/*\n+** mla_w8p14_z23_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?14\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p14_z23_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8 + 14, z23, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8 + 14, z23, z0, fpm0))\n+\n+/*\n+** mla_w8p15_z7_z7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?15\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p15_z7_z7, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8 + 15, z7, z7, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8 + 15, z7, z7, fpm0))\n+\n+/*\n+** mla_w8p16_z7_z7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?16\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p16_z7_z7, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8 + 16, z7, z7, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8 + 16, z7, z7, fpm0))\n+\n+/*\n+** mla_w8m1_z16_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z16\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8m1_z16_z0, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w8 - 1, z16, z0, fpm0),\n+\t svmla_za16_vg2x1_fpm (w8 - 1, z16, z0, fpm0))\n+\n+/*\n+** mla_w12_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w12\n+**\tfmlal\tza\\.h\\[\\1, 0:1\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w12_z0_z3, svmfloat8_t,\n+\t svmla_za16_mf8_vg2x1_fpm (w12, z0, z3, fpm0),\n+\t svmla_za16_vg2x1_fpm (w12, z0, z3, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c\nnew file mode 100644\nindex 00000000000..8dc613bb3c7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c\n@@ -0,0 +1,285 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f16\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_0_z0_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (0, z0, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w0_z0_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w0, z0, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z0\\.b - z1\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z4, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z0, z4, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** mla_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z4\\.b - z5\\.b}, {z18\\.b - z19\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z4_z18, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z4, z18, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** mla_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z0\\.b - z1\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z23, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z0, z23, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** mla_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], [^\\n]+, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z23_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z23, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** mla_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z18\\.b - z19\\.b}, {z28\\.b - z29\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z18_z28, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z18, z28, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** mla_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z28\\.b - z29\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z28_z4, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8, z28, z4, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** mla_w8p1_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p1_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8 + 1, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 2:3, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p2_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8 + 2, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** mla_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 4:5, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w11p4_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w11 + 4, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** mla_w11p6_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 6:7, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w11p6_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w11 + 6, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w11 + 6, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p7_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p7_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8 + 7, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z4\\.b - z5\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p8_z4_z4, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8 + 8, z4, z4, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** mla_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8m1_z4_z0, svmfloat8x2_t,\n+\t svmla_za16_mf8_vg2x2_fpm (w8 - 1, z4, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 - 1, z4, z0, fpm0))\n+\n+/*\n+** mla_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (0, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w0, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p1_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8 + 1, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 2:3, vgx2\\], {z20\\.b - z21\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p2_z20_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8 + 2, z20, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** mla_single_w11p6_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 6:7, vgx2\\], {z27\\.b - z28\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w11p6_z27_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w11 + 6, z27, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w11 + 6, z27, z0, fpm0))\n+\n+/*\n+** mla_single_w8p7_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p7_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8 + 7, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8 + 8, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0m1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w0 - 1, z1, z0, fpm0),\n+\t svmla_za16_vg2x2_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z0\\.b - z1\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (mla_single_w8_z0_z15, svmfloat8x2_t, svmfloat8_t,\n+\t\t svmla_single_za16_mf8_vg2x2_fpm (w8, z0, z15, fpm0),\n+\t\t svmla_za16_vg2x2_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** mla_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx2\\], {z20\\.b - z21\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z20_z16, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x2_fpm (w8, z20, z16, fpm0),\n+\t svmla_za16_vg2x2_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c\nnew file mode 100644\nindex 00000000000..204231314c4\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c\n@@ -0,0 +1,287 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f16\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_0_z0_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (0, z0, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w0_z0_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w0, z0, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z0\\.b - z3\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z4, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z0, z4, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z0, z4, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** mla_w8_z0_z18:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z18, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z0, z18, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z0, z18, fpm0))\n+\n+/*\n+** mla_w8_z18_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z18_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z18, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z18, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z23, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z0, z23, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** mla_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z23_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z23, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** mla_w8_z4_z28:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z4\\.b - z7\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z4_z28, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z4, z28, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z4, z28, fpm0))\n+\n+/*\n+** mla_w8_z28_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z28\\.b - z31\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z28_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8, z28, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z28, z0, fpm0))\n+\n+/*\n+** mla_w8p1_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p1_z4_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8 + 1, z4, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 2:3, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p2_z4_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8 + 2, z4, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** mla_w11p6_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w11, 6:7, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w11p6_z4_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w11 + 6, z4, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w11 + 6, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p7_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p7_z4_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8 + 7, z4, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z4\\.b - z7\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p8_z4_z4, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8 + 8, z4, z4, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** mla_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8m1_z4_z0, svmfloat8x4_t,\n+\t svmla_za16_mf8_vg2x4_fpm (w8 - 1, z4, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 - 1, z4, z0, fpm0))\n+\n+/*\n+** mla_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (0, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w0, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p1_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8 + 1, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 2:3, vgx4\\], {z20\\.b - z23\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p2_z20_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8 + 2, z20, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** mla_single_w8p6_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 6:7, vgx4\\], {z27\\.b - z30\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p6_z27_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8 + 6, z27, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 6, z27, z0, fpm0))\n+\n+/*\n+** mla_single_w8p7_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p7_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8 + 7, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8 + 8, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[\\1, 0:1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0m1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w0 - 1, z1, z0, fpm0),\n+\t svmla_za16_vg2x4_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z0\\.b - z3\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (mla_single_w8_z0_z15, svmfloat8x4_t, svmfloat8_t,\n+\t\t svmla_single_za16_mf8_vg2x4_fpm (w8, z0, z15, fpm0),\n+\t\t svmla_za16_vg2x4_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** mla_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlal\tza\\.h\\[w8, 0:1, vgx4\\], {z20\\.b - z23\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z20_z16, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za16_mf8_vg2x4_fpm (w8, z20, z16, fpm0),\n+\t svmla_za16_vg2x4_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c\nnew file mode 100644\nindex 00000000000..cb1832b18d9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c\n@@ -0,0 +1,167 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f32\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_0_z0_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (0, z0, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w0_z0_z3, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w0, z0, z3, fpm0),\n+\t svmla_za32_vg4x1_fpm (w0, z0, z3, fpm0))\n+\n+/*\n+** mla_w7_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w7\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w7_z0_z3, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w7, z0, z3, fpm0),\n+\t svmla_za32_vg4x1_fpm (w7, z0, z3, fpm0))\n+\n+/*\n+** mla_w8_z7_z3:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3\\], z7\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8_z7_z3, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8, z7, z3, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8, z7, z3, fpm0))\n+\n+/*\n+** mla_w8_z31_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfmlall\tza\\.s\\[w8, 0:3\\], z31\\.b. \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8_z31_z16, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8, z31, z16, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8, z31, z16, fpm0))\n+\n+/*\n+** mla_w8p1_z0_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p1_z0_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8 + 1, z0, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8 + 1, z0, z0, fpm0))\n+\n+/*\n+** mla_w10p4_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w10, 4:7\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w10p4_z23_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w10 + 4, z23, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w10 + 4, z23, z0, fpm0))\n+\n+/*\n+** mla_w11p6_z23_z0:\n+**\tadd\t(w8|w9|w10|w11), w11, #?6\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w11p6_z23_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w11 + 6, z23, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w11 + 6, z23, z0, fpm0))\n+\n+/*\n+** mla_w9p8_z7_z7:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w9, 8:11\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w9p8_z7_z7, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w9 + 8, z7, z7, fpm0),\n+\t svmla_za32_vg4x1_fpm (w9 + 8, z7, z7, fpm0))\n+\n+/*\n+** mla_w11p12_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 12:15\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w11p12_z23_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w11 + 12, z23, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w11 + 12, z23, z0, fpm0))\n+\n+/*\n+** mla_w8p14_z23_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?14\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z23\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p14_z23_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8 + 14, z23, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8 + 14, z23, z0, fpm0))\n+\n+/*\n+** mla_w8p15_z7_z7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?15\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p15_z7_z7, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8 + 15, z7, z7, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8 + 15, z7, z7, fpm0))\n+\n+/*\n+** mla_w8p16_z7_z7:\n+**\tadd\t(w8|w9|w10|w11), w8, #?16\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z7\\.b, z7\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8p16_z7_z7, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8 + 16, z7, z7, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8 + 16, z7, z7, fpm0))\n+\n+/*\n+** mla_w8m1_z16_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z16\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w8m1_z16_z0, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w8 - 1, z16, z0, fpm0),\n+\t svmla_za32_vg4x1_fpm (w8 - 1, z16, z0, fpm0))\n+\n+/*\n+** mla_w12_z0_z3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w12\n+**\tfmlall\tza\\.s\\[\\1, 0:3\\], z0\\.b, z3\\.b\n+**\tret\n+*/\n+TEST_ZA_X1 (mla_w12_z0_z3, svmfloat8_t,\n+\t svmla_za32_mf8_vg4x1_fpm (w12, z0, z3, fpm0),\n+\t svmla_za32_vg4x1_fpm (w12, z0, z3, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c\nnew file mode 100644\nindex 00000000000..246a492ad3e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c\n@@ -0,0 +1,277 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f32\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_0_z0_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (0, z0, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w0_z0_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w0, z0, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z0\\.b - z1\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z4, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z0, z4, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** mla_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z18\\.b - z19\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z4_z18, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z4, z18, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** mla_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z0\\.b - z1\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z23, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z0, z23, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** mla_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], [^\\n]+, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z23_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z23, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** mla_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z18\\.b - z19\\.b}, {z28\\.b - z29\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z18_z28, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z18, z28, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** mla_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z28\\.b - z29\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z28_z4, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8, z28, z4, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** mla_w8p1_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p1_z4_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8 + 1, z4, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p2_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?2\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p2_z4_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8 + 2, z4, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** mla_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w11p4_z4_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w11 + 4, z4, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p7_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p7_z4_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8 + 7, z4, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p8_z4_z4, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8 + 8, z4, z4, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** mla_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8m1_z4_z0, svmfloat8x2_t,\n+\t svmla_za32_mf8_vg4x2_fpm (w8 - 1, z4, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 - 1, z4, z0, fpm0))\n+\n+/*\n+** mla_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (0, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w0, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p1_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8 + 1, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p2_z20_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?2\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z20\\.b - z21\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p2_z20_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8 + 2, z20, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** mla_single_w11p4_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7, vgx2\\], {z27\\.b - z28\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w11p4_z27_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w11 + 4, z27, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w11 + 4, z27, z0, fpm0))\n+\n+/*\n+** mla_single_w8p7_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p7_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8 + 7, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8 + 8, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0m1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w0 - 1, z1, z0, fpm0),\n+\t svmla_za32_vg4x2_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z0\\.b - z1\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (mla_single_w8_z0_z15, svmfloat8x2_t, svmfloat8_t,\n+\t\t svmla_single_za32_mf8_vg4x2_fpm (w8, z0, z15, fpm0),\n+\t\t svmla_za32_vg4x2_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** mla_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx2\\], {z20\\.b - z21\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z20_z16, svmfloat8x2_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x2_fpm (w8, z20, z16, fpm0),\n+\t svmla_za32_vg4x2_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c\nnew file mode 100644\nindex 00000000000..1b10dc81711\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c\n@@ -0,0 +1,289 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sme+sme-f8f32\"\n+\n+/*\n+** mla_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_0_z0_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (0, z0, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** mla_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w0_z0_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w0, z0, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z0\\.b - z3\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z4, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z0, z4, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z0, z4, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** mla_w8_z0_z18:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z18, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z0, z18, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z0, z18, fpm0))\n+\n+/*\n+** mla_w8_z18_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z18_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z18, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z18, z0, fpm0))\n+\n+/*\n+** mla_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z0_z23, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z0, z23, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** mla_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z23_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z23, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** mla_w8_z4_z28:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z4_z28, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z4, z28, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z4, z28, fpm0))\n+\n+/*\n+** mla_w8_z28_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z28\\.b - z31\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8_z28_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8, z28, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z28, z0, fpm0))\n+\n+/*\n+** mla_w8p1_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p1_z4_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8 + 1, z4, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p2_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?2\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p2_z4_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8 + 2, z4, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** mla_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w11, 4:7, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w11p4_z4_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w11 + 4, z4, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p7_z4_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p7_z4_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8 + 7, z4, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** mla_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8p8_z4_z4, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8 + 8, z4, z4, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** mla_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (mla_w8m1_z4_z0, svmfloat8x4_t,\n+\t svmla_za32_mf8_vg4x4_fpm (w8 - 1, z4, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 - 1, z4, z0, fpm0))\n+\n+/*\n+** mla_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (0, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w0, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p1_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8 + 1, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p4_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 4:7, vgx4\\], {z20\\.b - z23\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p4_z20_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8 + 4, z20, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 4, z20, z0, fpm0))\n+\n+/*\n+** mla_single_w8p6_z27_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?6\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z27\\.b - z30\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p6_z27_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8 + 6, z27, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 6, z27, z0, fpm0))\n+\n+/*\n+** mla_single_w8p7_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?7\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p7_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8 + 7, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8p8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8 + 8, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[\\1, 0:3, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w0m1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w0 - 1, z1, z0, fpm0),\n+\t svmla_za32_vg4x4_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** mla_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z0\\.b - z3\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (mla_single_w8_z0_z15, svmfloat8x4_t, svmfloat8_t,\n+\t\t svmla_single_za32_mf8_vg4x4_fpm (w8, z0, z15, fpm0),\n+\t\t svmla_za32_vg4x4_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** mla_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfmlall\tza\\.s\\[w8, 0:3, vgx4\\], {z20\\.b - z23\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (mla_single_w8_z20_z16, svmfloat8x4_t, svmfloat8_t,\n+\t svmla_single_za32_mf8_vg4x4_fpm (w8, z20, z16, fpm0),\n+\t svmla_za32_vg4x4_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/test_sme2_acle.h b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/test_sme2_acle.h\nindex 8b982caf438..ff237983ad9 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/test_sme2_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/test_sme2_acle.h\n@@ -4,7 +4,7 @@\n #include \"../../sme/acle-asm/test_sme_acle.h\"\n \n #define TEST_ZA_X1(NAME, ZTYPE, CODE1, CODE2)\t\t\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w7 __asm (\"w7\");\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n@@ -26,7 +26,7 @@\n }\n \n #define TEST_ZA_XN(NAME, TTYPE, CODE1, CODE2)\t\t\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w7 __asm (\"w7\");\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n@@ -68,7 +68,7 @@\n }\n \n #define TEST_ZA_SINGLE(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n register int w11 __asm (\"w11\");\t\t\t\t\\\n@@ -84,7 +84,7 @@\n }\n \n #define TEST_ZA_SINGLE_Z15(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n@@ -94,7 +94,7 @@\n }\n \n #define TEST_ZA_LANE(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n register int w11 __asm (\"w11\");\t\t\t\t\\\n@@ -112,7 +112,7 @@\n }\n \n #define TEST_ZA_LANE_Z15(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n- PROTO (NAME, void, (int w0))\t\t\t\t\t\\\n+ PROTO (NAME, void, (int w0, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n register int w8 __asm (\"w8\");\t\t\t\t\\\n register TTYPE z4 __asm (\"z4\");\t\t\t\t\\\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c\nindex 2c60d50c6ed..88552980423 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_lane_1.c\n@@ -71,3 +71,17 @@ f4 (svint16_t s16, svuint16_t u16,\n svmla_lane_za64_vg4x1 (0, s64, s64, 0); /* { dg-error {'svmla_lane_za64_vg4x1' has no form that takes 'svint64_t' arguments} } */\n svmla_lane_za64_vg4x1 (0, u64, u64, 0); /* { dg-error {'svmla_lane_za64_vg4x1' has no form that takes 'svuint64_t' arguments} } */\n }\n+\n+#pragma GCC target (\"+sme-f8f32\")\n+\n+f5 (svmfloat8_t mf8,\n+ svmfloat8x2_t mf8x2,\n+ double d, fpm_t fpm)\n+ __arm_streaming __arm_inout(\"za\")\n+{\n+ svmla_lane_za32_vg4x1_fpm (d, mf8, mf8, 0); /* { dg-error {too few arguments to function 'svmla_lane_za32_vg4x1_fpm'} } */\n+ svmla_lane_za32_vg4x1_fpm (d, mf8, mf8, 0, 0, fpm); /* { dg-error {too many arguments to function 'svmla_lane_za32_vg4x1_fpm'} } */\n+ svmla_lane_za32_vg4x1_fpm (d, mf8, mf8, 0, fpm);\n+ svmla_lane_za32_vg4x1_fpm (d, mf8, mf8, -1, fpm); /* { dg-error {passing -1 to argument 4 of 'svmla_lane_za32_vg4x1_fpm', which expects a value in the range \\[0, 15\\]} } */\n+ svmla_lane_za32_vg4x1_fpm (d, mf8, mf8, 16, fpm); /* { dg-error {passing 16 to argument 4 of 'svmla_lane_za32_vg4x1_fpm', which expects a value in the range \\[0, 15\\]} } */\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c\nindex a361f7f5cb6..b1d9a82916a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_slice_opt_single_1.c\n@@ -74,3 +74,19 @@ f4 (svint32x2_t s32x2, svuint32x2_t u32x2,\n svadd_write_za64_vg1x2 (1, s64x2, s64x2);\n svadd_write_za64_vg1x2 (1, u64x2, u64x2);\n }\n+\n+#pragma GCC target (\"+sme-f8f16\")\n+\n+void\n+f5 (svmfloat8x2_t mf8x2, svmfloat8_t mf8,\n+ svfloat16x2_t f16x2, svfloat16_t f16,\n+ fpm_t fpm)\n+ __arm_streaming __arm_inout(\"za\")\n+{\n+ svmla_single_za16_mf8_vg2x2_fpm (1, mf8x2, mf8); /* { dg-error {too few arguments to function 'svmla_single_za16_mf8_vg2x2_fpm'} } */\n+ svmla_single_za16_mf8_vg2x2_fpm (1, mf8x2, mf8, fpm);\n+ svmla_single_za16_mf8_vg2x2_fpm (1, mf8x2, mf8, fpm, fpm); /* { dg-error {too many arguments to function 'svmla_single_za16_mf8_vg2x2_fpm'} } */\n+ svmla_single_za16_mf8_vg2x2_fpm (1, mf8x2, f16, fpm); /* { dg-error {incompatible type for argument 3 of 'svmla_single_za16_mf8_vg2x2_fpm'} } */\n+ svmla_single_za16_mf8_vg2x2_fpm (1, f16x2, mf8, fpm); /* { dg-error {incompatible type for argument 2 of 'svmla_single_za16_mf8_vg2x2_fpm'} } */\n+ svmla_single_za16_mf8_vg2x2_fpm (1, mf8x2, f16, fpm); /* { dg-error {incompatible type for argument 3 of 'svmla_single_za16_mf8_vg2x2_fpm'} } */\n+}\n", "prefixes": [ "v4", "6/8" ] }