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GET /api/1.0/patches/2175592/?format=api
{ "id": 2175592, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175592/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218142621.57402-8-claudio.bantaloukas@arm.com>", "date": "2025-12-18T14:26:19", "name": "[v4,7/8] aarch64: add 8-bit floating-point sum of outer products and accumulate", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2b1f4ccc8381f7f931c688b7b86b3dfb13716e6a", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-8-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485861, "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api", "date": "2025-12-18T14:26:12", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175592/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=KrSHeTA6;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=KrSHeTA6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v4 7/8] aarch64: add 8-bit floating-point sum of outer\n products and accumulate", "Date": "Thu, 18 Dec 2025 14:26:19 +0000", "Message-ID": "<20251218142621.57402-8-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509E5:EE_|PR3PR08MB5611:EE_|AMS0EPF00000190:EE_|AS1PR08MB7426:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b607cc05-2627-401e-e96b-08de3e41a754", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|36860700013|376014|1800799024|82310400026|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n rRlNdC/MnJVY3960baS2wRGhgOpG+wThn4DY3JqHb6KfekJvAWZUcVB2kDrn2uCSYFN0DwLVg746jGnE0b+jsrG7FNuovVUaA2kFttE5ag6NrZ8zSi0bECpRfWXmPu7raPE+SMmMV4fe3w7j2VrS8f1JHWe6E4ds2u5uJQeV1/IaXUp3Pl+ClGxtLE/k/M6NpTVsW2m5udt2L6knFKZBrXrdw29oDz0kpHWzWacYWZ7TL0JbSpSitSoDeNihCCBLYjN4XEmAwI7lUKoCWUMbuZqxQ/wPo+F8PJzR2JB0pBHwCrxKXncgbSvIMey8mpxLJO8XGmR4TGZyr5LAV7iq+kfxRsFRcIScOsM578Y2QVSJImQEo+kg+JXZ33wewe2PNjYkwg1U6NKFoBxn9jWxmCWQMx1xtN9D/oQdFUbl9I0kCJAnD/ojIbCAWV4XpsDPTi4GTbSSqHvc6mJZAbtpc2ti7G6T4UWlV6EA6E0CF4WK7UWvxhcmUbsPyjCTMUI53LkkWj2WMoP+a/cwKVH6zEafkbUKtNPHeBbVNSzpItp4Msd14qgnV6p67bsP0IUS968laFEIrCdfgF2FHCFnPksNHwIbSRpa5uT1X09wP3pCVwNWHUrZvUZTv5HbVZkIxQbL0lE+QtIm6BzCUSoqIihcXNj5X5g7iWL7Q7aHDLArxCxpQV4kPrcoQjV32AYqUfENKWKKrSGbhJaSVSbuqMLUUy0KMb2n4M4Rz1ZDjupEHSlwOZj8RpJWYHvSpuLE6tDn9Y88+g0BlDebK8wupPgSIys4ZqYWk2qNJ205r95thzptEZo1/fx1Yw89Ohtc/P2PwYSO5AvNDBDkw7C07L/6y02AT0EZP6edclw9W+BmEdmqqWm3gHU1KWS8HkGmLh46b93mm/UsZYhFQZbFlwdlDaJFjwz6FlyTFl/9hCFHgw9OsQUyhOxi+xnCbt9EUy1pwPSq8O3ZUVnUMlPPDtCkoNTDy2RkrGS0IUN9E9r8w+ivxS2j4jM+L0i/ZruMcThF/rwJKG7YTlg2I4w2fSPrUkGwzkTdgtaR8SXtW66BfzBwrwqnt3miP+2vsExssj6jZcLVeRjkthhrM6ohTbU6sZGEsnvJTr4hWFI7+j8gA2AMqeI0b+HXh7lzymUDL2EqvzFRxLdKmuaBrCWJ6h7y+zXcvGyMun1DJsa4XJqFvBQH7Bx05zzdWuqvvKnJE5l+/mgELE8S6val97hpJ0QiGSO7uuGkXzPIkLu+l/9wI6MuFxVhek+ioah0A0Cv0foy+JkxCXlqCGX/Q24mHppvXgd7vkoK1bHzWKFMByaidj/ksQbAp6y448Kbt+mRI3fAJBjoG/nDRqzHuhHxFqeOp6dpdFkP48Jqsc7J4+E2nX0/Mu2i7HHRyhJLRAfOknxqmxfetZ7Xf9FkamocI4schOwkB2J59fAw3UVywoAiXLEYK5vwT/AmW5JNC8p/WuCZB7EZfBckndgPAUrGv2Bt7alU5QioAZwwsNLzFSJn7PR0yyTRu3Z5oEJEikQlTuD1OgvHXmljUdxM8TtkL5pb8dlFog54KjrRKW6sAYWbBp+tQL8qV8viXScJZS8B", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(376014)(82310400026)(14060799003)(1800799024)(36860700013)(35042699022)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 14:28:03.3324 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b607cc05-2627-401e-e96b-08de3e41a754", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AMS0EPF00000190.eurprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for FMOPA (widening, 2-way, FP8 to FP16) when\nsme-f8f16 is enabled using svmopa_za16[_mf8]_m_fpm and for FMOPA (widening,\n4-way) when sme-f8f32 is enabled using svmopa_za32[_mf8]_m_fpm.\n\nAsm tests for the new intrinsics are added, similar to those for existing\nmopa_z16 intrinsics. Tests for the binary_za_m shape are added.\n\ngcc:\n\t* config/aarch64/aarch64-sme.md\n\t(@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>): Add\n\tnew define_insn.\n\t* config/aarch64/aarch64-sve-builtins-shapes.cc\n\t(struct binary_za_m_base): Support fpm argument.\n\t* config/aarch64/aarch64-sve-builtins-sme.cc (svmopa_za): Extend for\n\tfp8.\n\t* config/aarch64/aarch64-sve-builtins-sme.def (svmopa): Add new\n\tDEF_SME_ZA_FUNCTION_GS_FPM entries.\n\ngcc/testsuite:\n\n\t* gcc.target/aarch64/sme/acle-asm/test_sme_acle.h: (TEST_UNIFORM_ZA):\n\tAdd fpm0 parameter.\n\t* gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c: Add tests for\n\tvariants accepting fpm.\n\t* gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c: Likewise.\n---\n gcc/config/aarch64/aarch64-sme.md | 20 +++++++++++\n .../aarch64/aarch64-sve-builtins-shapes.cc | 2 +-\n .../aarch64/aarch64-sve-builtins-sme.cc | 2 +-\n .../aarch64/aarch64-sve-builtins-sme.def | 2 ++\n gcc/config/aarch64/aarch64-sve2.md | 2 +-\n .../aarch64/sme/acle-asm/test_sme_acle.h | 2 +-\n .../aarch64/sme2/acle-asm/mopa_za16_mf8.c | 36 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/mopa_za32_mf8.c | 36 +++++++++++++++++++\n .../sve/acle/general-c/binary_za_m_1.c | 14 ++++++++\n 9 files changed, 112 insertions(+), 4 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md\nindex e8301ae72a7..0e1cdafb6dc 100644\n--- a/gcc/config/aarch64/aarch64-sme.md\n+++ b/gcc/config/aarch64/aarch64-sme.md\n@@ -2378,6 +2378,8 @@ (define_insn \"*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_FP8_x124:mode>\"\n ;; - BFMOPS (SME_B16B16)\n ;; - FMOPA\n ;; - FMOPS\n+;; - FMOPA (SME_F8F16)\n+;; - FMOPA (SME_F8F32)\n ;; -------------------------------------------------------------------------\n \n (define_insn \"@aarch64_sme_<optab><mode><mode>\"\n@@ -2410,6 +2412,24 @@ (define_insn \"@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>\"\n \"<b><optab>\\tza%0.<VNx4SI_ONLY:Vetype>, %1/m, %2/m, %3.<SVE_FULL_HF:Vetype>, %4.<SVE_FULL_HF:Vetype>\"\n )\n \n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><VNx16QI_ONLY:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:DI 0 \"const_int_operand\")\n+\t (match_operand:<SME_ZA_F8F16_32:VPRED> 1 \"register_operand\" \"Upl\")\n+\t (match_operand:<SME_ZA_F8F16_32:VPRED> 2 \"register_operand\" \"Upl\")\n+\t (match_operand:VNx16QI_ONLY 3 \"register_operand\" \"w\")\n+\t (match_operand:VNx16QI_ONLY 4 \"register_operand\" \"w\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP_MOP))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza%0.<SME_ZA_F8F16_32:Vetype>, %1/m, %2/m, %3.b, %4.b\"\n+)\n+\n ;; =========================================================================\n ;; == Table lookup\n ;; =========================================================================\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\nindex 59f313d08f2..ea4be3733c2 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n@@ -692,7 +692,7 @@ struct binary_za_m_base : public overloaded_base<1>\n resolve (function_resolver &r) const override\n {\n type_suffix_index type;\n- if (!r.check_num_arguments (5)\n+ if (!r.check_num_arguments (r.fpm_mode == FPM_set ? 6: 5)\n \t|| !r.require_integer_immediate (0)\n \t|| !r.require_vector_type (1, VECTOR_TYPE_svbool_t)\n \t|| !r.require_vector_type (2, VECTOR_TYPE_svbool_t)\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\nindex 43ef05c673a..20a6ebc4059 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n@@ -651,7 +651,7 @@ FUNCTION (svmls_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SMLS,\n \t\t\t\t\t\t UNSPEC_SME_UMLS,\n \t\t\t\t\t\t UNSPEC_SME_FMLS))\n FUNCTION (svmopa_za, sme_2mode_function, (UNSPEC_SME_SMOPA, UNSPEC_SME_UMOPA,\n-\t\t\t\t\t UNSPEC_SME_FMOPA))\n+\t\t\t\t\t UNSPEC_SME_FMOPA, UNSPEC_SME_FMOPA))\n FUNCTION (svmops_za, sme_2mode_function, (UNSPEC_SME_SMOPS, UNSPEC_SME_UMOPS,\n \t\t\t\t\t UNSPEC_SME_FMOPS))\n FUNCTION (svread_za, svread_za_impl,)\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\nindex f9ad6837f44..6306ee33a14 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n@@ -270,6 +270,7 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_h_mf8,\n \t\t\t vg2, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg2, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_h_mf8, vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_h_mf8, none, za_m, set)\n #undef REQUIRED_EXTENSIONS\n \n #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n@@ -277,6 +278,7 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmla_lane, binary_za_slice_lane, za_s_mf8,\n \t\t\t vg4, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg4, none, set)\n DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_s_mf8, none, za_m, set)\n #undef REQUIRED_EXTENSIONS\n \n #undef DEF_SME_ZA_FUNCTION\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex 11cc53bbb50..407f1698c41 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3666,7 +3666,7 @@ (define_insn \"@aarch64_sve2_fp8_cvtn<mode>\"\n \t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n \t (reg:DI FPM_REGNUM)]\n \t UNSPEC_FP8FCVTN))]\n- \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_STREAMING_SME2\"\n+ \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_SSVE_FP8\"\n \"<b>fcvtn\\t%0.b, %1\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\nindex aaadab2f773..75e3413768e 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h\n@@ -46,7 +46,7 @@\n \n #define TEST_UNIFORM_ZA(NAME, TYPE, CODE1, CODE2)\t\t\\\n PROTO (NAME, void, (TYPE z0, TYPE z1, svbool_t p0,\t\t\\\n-\t\t svbool_t p1))\t\t\t\t\\\n+\t\t svbool_t p1, fpm_t fpm0))\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n INVOKE (CODE1, CODE2);\t\t\t\t\t\\\n }\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\nnew file mode 100644\nindex 00000000000..e88b7a4814c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\n@@ -0,0 +1,36 @@\n+/* { dg-do assemble { target aarch64_asm_sme-f8f16_ok } } */\n+/* { dg-do compile { target { ! aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+sme-f8f16\"\n+/*\n+** mopa_za16_mf8_0_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.h, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_0_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (0, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za16_m_fpm (0, p0, p1, z0, z1, fpm0))\n+\n+/*\n+** mopa_za16_mf8_0_p1_p0_z1_z0:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.h, p1/m, p0/m, z1\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_0_p1_p0_z1_z0, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (0, p1, p0, z1, z0, fpm0),\n+\t\t svmopa_za16_m_fpm (0, p1, p0, z1, z0, fpm0))\n+\n+/*\n+** mopa_za16_mf8_1_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza1\\.h, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za16_mf8_1_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za16_mf8_m_fpm (1, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za16_m_fpm (1, p0, p1, z0, z1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c\nnew file mode 100644\nindex 00000000000..74a665fea6b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c\n@@ -0,0 +1,36 @@\n+/* { dg-do assemble { target aarch64_asm_sme-f8f32_ok } } */\n+/* { dg-do compile { target { ! aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+sme-f8f32\"\n+/*\n+** mopa_za32_mf8_0_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.s, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_0_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (0, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za32_m_fpm (0, p0, p1, z0, z1, fpm0))\n+\n+/*\n+** mopa_za32_mf8_0_p1_p0_z1_z0:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza0\\.s, p1/m, p0/m, z1\\.b, z0\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_0_p1_p0_z1_z0, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (0, p1, p0, z1, z0, fpm0),\n+\t\t svmopa_za32_m_fpm (0, p1, p0, z1, z0, fpm0))\n+\n+/*\n+** mopa_za32_mf8_1_p0_p1_z0_z1:\n+** \tmsr\tfpmr, x0\n+**\tfmopa\tza1\\.s, p0/m, p1/m, z0\\.b, z1\\.b\n+**\tret\n+*/\n+TEST_UNIFORM_ZA (mopa_za32_mf8_1_p0_p1_z0_z1, svmfloat8_t,\n+\t\t svmopa_za32_mf8_m_fpm (1, p0, p1, z0, z1, fpm0),\n+\t\t svmopa_za32_m_fpm (1, p0, p1, z0, z1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\nindex 44c3e48e916..5f013bd4194 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_za_m_1.c\n@@ -46,3 +46,17 @@ f4 (svbool_t pg, svint16_t s16) __arm_streaming __arm_inout(\"za\")\n svmopa_za64_m (-1, pg, pg, s16, s16); /* { dg-error {passing -1 to argument 1 of 'svmopa_za64_m', which expects a value in the range \\[0, 7\\]} } */\n svmopa_za64_m (8, pg, pg, s16, s16); /* { dg-error {passing 8 to argument 1 of 'svmopa_za64_m', which expects a value in the range \\[0, 7\\]} } */\n }\n+\n+#pragma GCC target (\"arch=armv9-a+sme-f8f16+sme-f8f32\")\n+\n+void\n+f5 (svbool_t pg, svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout(\"za\")\n+{\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8); /* { dg-error {too few arguments to function 'svmopa_za16_mf8_m_fpm'} } */\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8, fpm);\n+ svmopa_za16_mf8_m_fpm(0, pg, pg, mf8, mf8, fpm, fpm); /* { dg-error {too many arguments to function 'svmopa_za16_mf8_m_fpm'; expected 6, have 7} } */\n+\n+ svmopa_za16_mf8_m_fpm(-1, pg, pg, mf8, mf8, fpm); /* { dg-error {passing -1 to argument 1 of 'svmopa_za16_mf8_m_fpm', which expects a value in the range \\[0, 1\\]} } */\n+ svmopa_za16_mf8_m_fpm(2, pg, pg, mf8, mf8, fpm); /* { dg-error {passing 2 to argument 1 of 'svmopa_za16_mf8_m_fpm', which expects a value in the range \\[0, 1\\]} } */\n+ svmopa_za32_mf8_m_fpm(4, pg, pg, mf8, mf8, fpm); /* { dg-error {passing 4 to argument 1 of 'svmopa_za32_mf8_m_fpm', which expects a value in the range \\[0, 3\\]} } */\n+}\n", "prefixes": [ "v4", "7/8" ] }