Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175591/?format=api
{ "id": 2175591, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175591/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218142621.57402-4-claudio.bantaloukas@arm.com>", "date": "2025-12-18T14:26:15", "name": "[v4,3/8] aarch64: add narrowing sme2 conversions to fp8", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "01043d620c529f1f055c13c2c037b10f46410070", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-4-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485861, "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api", "date": "2025-12-18T14:26:12", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175591/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=pt485dEd;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=pt485dEd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=pt485dEd;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=pt485dEd", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com", "sourceware.org; spf=pass smtp.mailfrom=arm.com", "server2.sourceware.org;\n arc=pass smtp.remote-ip=52.101.66.66" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXCnz5vknz1y2F\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 01:33:27 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id C5AE64BA2E20\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 14:33:25 +0000 (GMT)", "from DUZPR83CU001.outbound.protection.outlook.com\n (mail-northeuropeazon11012066.outbound.protection.outlook.com [52.101.66.66])\n by sourceware.org (Postfix) with ESMTPS id CD4134BA2E1F\n for <gcc-patches@gcc.gnu.org>; Thu, 18 Dec 2025 14:27:52 +0000 (GMT)", "from DBBPR09CA0030.eurprd09.prod.outlook.com (2603:10a6:10:d4::18)\n by GV1PR08MB8284.eurprd08.prod.outlook.com (2603:10a6:150:a5::15) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 14:27:43 +0000", "from DB1PEPF000509EF.eurprd03.prod.outlook.com\n (2603:10a6:10:d4:cafe::ef) by DBBPR09CA0030.outlook.office365.com\n (2603:10a6:10:d4::18) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.8 via Frontend Transport; Thu,\n 18 Dec 2025 14:27:43 +0000", "from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by\n DB1PEPF000509EF.mail.protection.outlook.com (10.167.242.73) with Microsoft\n SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6\n via Frontend Transport; Thu, 18 Dec 2025 14:27:43 +0000", "from DUZP191CA0016.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:4f9::15)\n by PAWPR08MB10923.eurprd08.prod.outlook.com (2603:10a6:102:470::13) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 14:26:33 +0000", "from DB1PEPF000509E5.eurprd03.prod.outlook.com\n (2603:10a6:10:4f9:cafe::71) by DUZP191CA0016.outlook.office365.com\n (2603:10a6:10:4f9::15) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.8 via Frontend Transport; Thu,\n 18 Dec 2025 14:26:30 +0000", "from nebula.arm.com (172.205.89.229) by\n DB1PEPF000509E5.mail.protection.outlook.com (10.167.242.55) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9412.4 via Frontend Transport; Thu, 18 Dec 2025 14:26:33 +0000", "from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EX04.Arm.com\n (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 14:26:27 +0000", "from e72c20ac6da1.eu-west-1.compute.internal (10.249.56.29) by\n mail.arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29 via Frontend\n Transport; Thu, 18 Dec 2025 14:26:27 +0000" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org C5AE64BA2E20", "OpenDKIM Filter v2.11.0 sourceware.org CD4134BA2E1F" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org CD4134BA2E1F", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org CD4134BA2E1F", "ARC-Seal": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1766068073; cv=pass;\n b=fD79rX1W3R2eCso93AfeMmBC7nD6UXYjfjpy4bKJGGo2j1NKRZGtC4OmDM/nd7s4L6+tHfveSwduVdXY6Zlq6WPAXEPZcQdRz74r+upvMxrpPz6veUPQ7UA7id0EyN1saTmIIZ3ocitVF5Wat3pTSkD6EouTR6Ds//ywGBS7vdQ=", "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=FC6Z0EJszsbp+2GtIBP2+6Jt+woUbgMdLa8fiUwgP2HFTsGzruKPw1dHQDxqx77p/u+Zu1U9dfdsfGGvlxM4kfOzTOqI4BHXqUE+wYhCuTZ7Zfk34HRcQbr/dRtwUm/HSKqaPxDBJoy9g1QFtYpMl781+0xd6sBMFqsa0LVNhtaqF6fsEt9ypnQaS3uQ6Dov9E1Dl/wFIywHXNQmEIzRNB2KVFIu+RXLkYYBAVw2/Z2NskTqZG7TFNUzx0mN1Q4mpZwOgOWulcsEu2NKABl13PvMGwTFGL8RXFj2uKmtm4XKJb3IOneUNGAm/C8hKCqYA17bXnVC2MAszLkalCUpmQ==", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=TCM5dSi3UJSMybK03hjfGqGY8Lk7Ou/M3fyjjZCvYLeknTv8jH/qaknRBO9wtJiZb5NkZyms49y8s346bULnlEzsPdbRfLlQVDVfxar48xAINYMohQTSZRpt36Uwv7GUsi3aeoFUHXMF930SQRLTcr2rcbH9hrOcS7OSSonrEVPX0Q7oqKjtr4z89Rbn9zJ3kgoT7va8fbG5kDfHMqV2ARRrpt8p/kNUqWt7gbPH5/xMojKfCXIV6uwTGDK4OqSZhf+iW5NPPKTCiPbNMxr1iJ9ph012fyp3l9DAW49N72vJR0QZSw9GjpSQbMwMJ80iux5JGrs8A6A1ZGaAdxsSxQ==" ], "ARC-Message-Signature": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766068073; c=relaxed/simple;\n bh=Zi/0O+q50Ntw426QemAFCONgY0HuSgmqfn+La8ZmajY=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID:\n MIME-Version;\n b=B0TbyZ5JV4k6mJt7IbUpROYddBAoGv0wvoKpJ63XH74gUmetjMR80wnT7N/9eSZMv/dAfu0SVUuboQCxZp43mu0WGIZ+DoEYluVPstH1azGZwQbTaqL5Pcl/Sr55b1lhkPN7+uLeq7vJMY9FFydXWZvRprpl6WGNUYVhHOx+3II=", "i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=CaIw5sGZ8WUgEYR8iK6p+XqKNppzEMkPdvR6FULvPwxcPhhFGiqQdmK5+ruxiYnHMhbvw+ngDgktUzS0Iad8AOka3jwqHxWzoL9E5uwBNiWw9sjT11U5/T1xV/0tdUXbQaDkiI05LVNJsHDZG7fywwAb+rJN61c1YpRVjsl3hBqE/YnLr0aPnjV53TcvZ6t0WCyI0U341p/ypyCz4xSW1YMRgulVPtHcqAB0MUl3e2s7cYMgXAeBcAFIZZGu3rHg/RJIavPaRBGGiMK1p4iNA/Ql4WCM2VWUMXjXadLwp2V+SAK4JhOfLwlP441VOmagcE0tVbkN2yfQhX88DhC2nw==", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=KkO0LZupamEsm/jNKjYzVLmRvvcZN34L5JHqU9TaIKu7pQTSHXkQG1d2N1DTjob/ohbg99WKwkU8V4xu5iQ/GS3xtHM1iH+6gdKLd2ABZ3qO3YE9NvomZtz9Qi/dXSCcg7Y9qtGGlZhZscEr0Hj7a2qQpYbO5p/4lkV5GuxHsuj86j8Qld3TNrZIO0/J1dnDK6O5Iec7+FN3U6/CkgY7j4tzzlnyAXqFbzRoxTksiq8XvH9lVUNS8LEHCE6APBEXkKDHRqZKh/HuQiVLqmV4N3BPOd5w30k3rWmc6VADzCm4jJCdE+mEC2IDMZHNVVPGjhoGuAeR2WbzWHsbDNfplA==" ], "ARC-Authentication-Results": [ "i=3; server2.sourceware.org", "i=2; mx.microsoft.com 1; spf=pass (sender ip is\n 4.158.2.129) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass\n (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass\n (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1\n spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com])", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 172.205.89.229) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=pt485dEd+C0UTTZjQB94D28Amo71YnhgEHJo43kUvzOuNw4+vtz+BbY3PbbuigB8MwbLTNpbIF56Qw3aBDbhp/aBcf88d96d6dTDZP0ymxmy1AL2pOkcBSctUoVJt3GFwMrwJtpeklVFDwblVUfSVj5mLtjqYM369dkSIH5sGbg=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=zDLMK62pfKgLvEVcw/R1j0F+AtOYsEsvI0NO81CMhz4=;\n b=pt485dEd+C0UTTZjQB94D28Amo71YnhgEHJo43kUvzOuNw4+vtz+BbY3PbbuigB8MwbLTNpbIF56Qw3aBDbhp/aBcf88d96d6dTDZP0ymxmy1AL2pOkcBSctUoVJt3GFwMrwJtpeklVFDwblVUfSVj5mLtjqYM369dkSIH5sGbg=" ], "X-MS-Exchange-Authentication-Results": [ "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v4 3/8] aarch64: add narrowing sme2 conversions to fp8", "Date": "Thu, 18 Dec 2025 14:26:15 +0000", "Message-ID": "<20251218142621.57402-4-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509E5:EE_|PAWPR08MB10923:EE_|DB1PEPF000509EF:EE_|GV1PR08MB8284:EE_", "X-MS-Office365-Filtering-Correlation-Id": "97dbd61b-3050-44c0-a76e-08de3e419b46", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|82310400026|1800799024|36860700013|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n 8ZprXhhqXDS+4Lf/lQ4VI63nsRk65xnmOaE9mkN4X0JwgjbZlpXZHdj8OHkCIfLvFbmgxEVBeAdjq/cbKi1gHw8d8eO1drBE+DbUmW2s2RRSY4cJO0i5DR1ognxamVOoQU9v/59avTW+fBAIhNpKbcCqkhrFAfQZ8MGkuzRi5anw2NBc9fvyCw+ogonal0IJY2NkwpCSG+TIbP/qeBrZWHnaqXB9ZUjoM6ify0zhZxro1XZ6tV1cfLmJBWXfmXnK79iuLgBAOLP0qt7UJsPZduV2/nYR1/ScqxDw6A/3fBUpUvBQiLnZmviVuGXx9ZRfh+FILskPKlopeqyJakZyNpF9M2k6WV/H0xly/bUhE9Owe/svtd7eBMppP6OXkHXcx1wA2IF/UDPyjzGKPb3t3yGE+Kkvk7C+k4t837LiQ4MJWO4cWkLxC+n9Ra8dPw/gIoCJHdjJt7ZM+3mQdXS7fXydu3EcjvvQGhTci+Vr6kzSsRRDGEvCn9ofBEGAaFqwKKXmF8Fsw6h0qgxppXGpsbrA1jcToZEKkNvYPLioQp5A59XbhKErY7Eudoe6nZHDAgzhKE+ZdwBuDXDVb/lukGK1KiUJPRtk3l1oBNlOSafG/UA8eAlz45cyjC7Ra15FBaOqO6gLo+sbkrbfe30fgIyxyp5iey0IGeHSJv9QZesNRkV2rOGEjYnZ3uKKnP9ObirY7zMKBqg/FWazZfRFB7wmZnRkyir/NhI5IDufuEBJk6DZL59tSVet+utE+XND3HhscOGX7jS9kIGXSGphKJGSvk28OYoOhwBkLnzHH1xEDrdJeOvu/hWnABco8dvVwZfiaQE5Z7kdHq/DBxVRmWmaPt/z3wkmq2O60Pq1OVe2cRbjfsLq19AJrARNHYLx5dbv8Q3EJwjzb8TH6vFGlPjLU6E011kqLyjvDMIYNL5E7k+qjdw89naEd2p7+j4/xk1BfKeGT4Gjcgxapb1gJwp1GL0akPsJOVP1ymm/prE4k82OaIZD8hA4x6YDeDbCUPpLaL3V/JcxG5eu3uBbLjRBvl0k+Y9Q8oF46HPnqtS64xSYSM077hrGO+UWND1fVFDWSM4wiNPNLW0PP9uBHmIvRpnStZ9511/VMbzm37S26QKJNR002Y0IlWVBZvqAob2FBgl7/Fc6ypNFRAYGay+c1lPDOO4khqPcFxqJbmKWWN/8mxuJVJ9FMgE1QM6onRYG+ZtrVMwyKsJTPRnDVYX4sBm2Ebk+4cjr57UIcj7qATFT/IOtCEx4OxRrRVb2xkW0fqDzP5bh4ucTcLRamGElVSy48NpnZSnMlHsPmk4xgdUDLXOznLdtWPnrZFeNwVW2sCebsS76caIhks7TOrgFcEffkN2urNushaand3O1SZsO+cmz7JIVgmivVZbxT8WqtkqHP4reHdBH87YXEbKobRHZlPwfHbHJTeexSaHKsrWq7bEVTI5tMzyKkUQkZ8Gkh5eGHaJ1Ubn+ft2EeIq3bqToXvAaHODXjQus4iYx8ZGKsJgAt2Kuka85R9Kyym151KLjtTD7zUlOU/696nwWEj9wFgksiwv8Uv9iCjdwEHReynYsZaQ/LYWDIVhf", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; CTRY:IE; LANG:en;\n SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent;\n CAT:NONE;\n SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(13003099007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [ "PAWPR08MB10923", "GV1PR08MB8284" ], "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n DB1PEPF000509EF.eurprd03.prod.outlook.com", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id-Prvs": "\n 9f3d63b4-3c1a-4a5d-9327-08de3e4171c7", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|35042699022|36860700013|376014|14060799003|1800799024|82310400026|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n AqEmuEcik+zTPuGnKri80FMf8dTvGwnA23IslRN2VegIxEB6Ow6R4bZFq1lxD7EWvwsfP62dJ/sHCx1NhDatWbOfVC8c8qRAIOQA3smbmkOxeWeGhHSHFR1KOlKLHGyVmk0kn8PyG2G/Qhj7SSiak4JOohqRXS/9jCM5d3qNTM7sOr9c3oVk5Az1j35EYdm1qOhTHcsxwa1/pGJl7zc+b/bjtV66mp0QVm1iHZiunYpGkDLIB9bpy0eh8ouMO7K2Y6ZmAcwkOzssSk6FFN1DZ53txjfrNEQ0nJ5qL3w4tiEtA59wWtdjw/O95C974ZFvnlPqqY1Bbw80amhJxSWhb2AnHJN/xX6mTOxoeYUo1ko3giwkQOsqYj8dMKw3DESA+1rlg3MTeWNuyrpWAZ+dBbWhp/70CRDfB+kbj7gBPfviCkHgVYVq45ZAf7TKmh2PBpB0Nx2RmFJ3r8JRqd172WyKqEsIGgfI3zoknfNrKmmUt20GfKTMkA3FwNFckMJdn1s2XdnJ0M1exLXDj15th87GmOqXluktgjQe5m4HQQvITcrneV0KsGGxlFS7DE07oIw47MnwQtqgHrnMB1a0RWHgZMCjhzAar0nd4ye5SSd3I+mRYwekQeaaUHNvUvdddwAl7RPiauT587QYF/ImwoFWBGoUu7AourZpj45SjxFprqpQcJG7Nva3NJaErXfhEg6NLY7N09ZBz1bMNVqlTL1Kef0U6DP7gHrkkvjKpxQnk8tz3JVHHqLxTlJiHccYlzvkFY7Z88gxUIr5JRvV2J2R7a53oF8C1cLiHffRKHlnyUPf2D71qSbhuPRS9IgFQZVpT/hMU3xFiumpfA+Yq9i5F51KqM7OTQbxeawTf3jzFn5giT88KHuJubxrVjLprS34qhv3/ui6wAWaZZTlrNoXk8YCBaZqGIuKWV5/0WSCKwI17EI1LkDVvVZR6Lmr52gBOpjEGJw1uRdqwiOHWbxPYzp+mzMyerfO3+1zwYBM+/0TwED2GTeo2J3I4WvXA+2BGr+RehFdf98CTlfuiTMXhppJvMmQkKWCvl4bFPAOtpUYY45pHXMHRZSfFeof6jXj1CbIllYiF2iaG5MVV1gTAGyPqryPS7NgwkC/Jq+8b5ZE5OKFynxhWwk/u9zqvCdu2cFbW4mLERyy+QaDOAdSiQIMTTzdmkBeKKI+2QileqBJB3cdc/F0zovxuR3I4c1rwdywNBIWUBj00tHprItYOM2DqyYNtcUz+6jVH5eXiPvQosmOsZwKNPg7L8GB784vbYF8gXaWHirsDQ7OzMiaLmoipsWDMAYjK9Gd5GtD7sr+LXL8vnE49rh7AymWrPKMCQB5Yc06b9AD0a/4X2wAonytdIkytMauwZD86ZkmPpCOFNR1iBRvx7jlNUemh6xrZYjQ6wWciIy5HBSDT7AOP0bAqUFGt8CKw+dPWGRwIdNfMtxr1T8U5CK1C9bAO29Ab6l4Cic+3c5gya/1HxufbOebxLgenX/Dy5UDHZ9yCTjvrt9mktL4uw10qx7bnb/+72pTw3lHBcIARG3eBjLC18Bq9x7gLXObTFFiArFB8ZJQ287SU1a5yxtTRnDD", "X-Forefront-Antispam-Report": "CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(35042699022)(36860700013)(376014)(14060799003)(1800799024)(82310400026)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 14:27:43.0788 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 97dbd61b-3050-44c0-a76e-08de3e419b46", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB1PEPF000509EF.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds the following intrinsics (all __arm_streaming only) along with\nasm tests for them.\n\nBFCVT, FCVT Convert to packed 8-bit floating-point format:\n- svmfloat8_t svcvt_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_bf16_x2]_fpm(svbfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\nFCVTN Convert to interleaved 8-bit floating-point format.\n- svmfloat8_t svcvtn_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\ngcc/\n\t* config/aarch64/aarch64-sve-builtins-base.cc (svcvt_impl): Update to\n\thandle fp8 cases.\n\t* config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtn): Added\n\tDEF_SVE_FUNCTION_GS_FPM instances.\n\t* config/aarch64/aarch64-sve2.md\n\t(@aarch64_sve2_fp8_cvtn<mode>): Updated define_insn for additional case.\n\t(@aarch64_sme2_fp8_cvt<mode>): Added new define_insn.\n\t* config/aarch64/iterators.md (VNx16F_NARROW): Added new iterator to\n\thandle narrowing SVE floating point operations.\n\t(UNSPEC_FCVT): Added new unspec.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c: Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n\t(TEST_X2_NARROW): Added fpm0 argument for intrinsics.\n\t(TEST_X4_NARROW): Likewise.\n---\n .../aarch64/aarch64-sve-builtins-base.cc | 26 ++++---\n .../aarch64/aarch64-sve-builtins-sve2.def | 3 +\n gcc/config/aarch64/aarch64-sve2.md | 14 +++-\n gcc/config/aarch64/iterators.md | 4 ++\n .../aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sve/acle/asm/test_sve_acle.h | 2 +\n 9 files changed, 293 insertions(+), 12 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\nindex ecc06877cac..622485effb3 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n@@ -779,17 +779,23 @@ public:\n {\n \tmachine_mode mode0 = e.result_mode ();\n \tmachine_mode mode1 = GET_MODE (e.args[0]);\n-\tconvert_optab optab;\n-\tif (e.type_suffix (0).integer_p)\n-\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n-\telse if (e.type_suffix (1).integer_p)\n-\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab : sfloat_optab;\n-\telse if (e.type_suffix (0).element_bits\n-\t\t < e.type_suffix (1).element_bits)\n-\t optab = trunc_optab;\n+\tif (e.fpm_mode == aarch64_sve::FPM_set)\n+\t icode = code_for_aarch64_sme2_fp8_cvt (mode1);\n \telse\n-\t optab = sext_optab;\n-\ticode = convert_optab_handler (optab, mode0, mode1);\n+\t {\n+\t convert_optab optab;\n+\t if (e.type_suffix (0).integer_p)\n+\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n+\t else if (e.type_suffix (1).integer_p)\n+\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab\n+\t\t\t\t\t\t : sfloat_optab;\n+\t else if (e.type_suffix (0).element_bits\n+\t\t < e.type_suffix (1).element_bits)\n+\t optab = trunc_optab;\n+\t else\n+\t optab = sext_optab;\n+\t icode = convert_optab_handler (optab, mode0, mode1);\n+\t }\n \tgcc_assert (icode != CODE_FOR_nothing);\n \treturn e.use_exact_insn (icode);\n }\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\nindex c271b97de87..869e006ffde 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n@@ -421,6 +421,9 @@ DEF_SVE_FUNCTION_GS_FPM (svdot_lane, ternary_mfloat8_lane_group_selection, h_flo\n \n #define REQUIRED_EXTENSIONS \\\n streaming_only (AARCH64_FL_SME2 | AARCH64_FL_FP8)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtn_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvtn, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt1, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt2, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvtl1, unary_convert, cvt_mf8, x2, none, set)\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex ab8098d3327..da7a7a3c23c 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3635,10 +3635,10 @@ (define_insn \"@aarch64_sve_cvtn<mode>\"\n (define_insn \"@aarch64_sve2_fp8_cvtn<mode>\"\n [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n \t(unspec:VNx16QI\n-\t [(match_operand:SVE_FULL_HFx2 1 \"aligned_register_operand\" \"Uw2\")\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n \t (reg:DI FPM_REGNUM)]\n \t UNSPEC_FP8FCVTN))]\n- \"TARGET_SSVE_FP8\"\n+ \"<MODE>mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_STREAMING_SME2\"\n \"<b>fcvtn\\t%0.b, %1\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n@@ -3666,6 +3666,16 @@ (define_insn \"@aarch64_sve_cvtnt<mode>\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n \n+(define_insn \"@aarch64_sme2_fp8_cvt<mode>\"\n+ [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n+\t(unspec:VNx16QI\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t UNSPEC_FCVT))]\n+ \"TARGET_SSME2_FP8\"\n+ \"<b>fcvt\\t%0.b, %1\"\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP<-INT] Multi-vector conversions\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 026c3101e38..e6f59d22d0c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -712,6 +712,9 @@ (define_mode_iterator VNx4_WIDE [VNx4SI])\n (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])\n (define_mode_iterator VNx2_WIDE [VNx2DI])\n \n+;; Used for narrowing SVE floating point operations.\n+(define_mode_iterator VNx16F_NARROW [VNx16BF VNx16HF VNx16SF])\n+\n ;; All SVE predicate modes.\n (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])\n \n@@ -1061,6 +1064,7 @@ (define_c_enum \"unspec\"\n UNSPEC_F2CVTL\t; Used in aarch64-sve2.md.\n UNSPEC_F2CVTLT\t; Used in aarch64-sve2.md.\n UNSPEC_FADDP\t; Used in aarch64-sve2.md.\n+ UNSPEC_FCVT\t\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNB\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNT\t; Used in aarch64-sve2.md.\n UNSPEC_FMAXNMP\t; Used in aarch64-sve2.md.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\nnew file mode 100644\nindex 00000000000..bdda0fd36d6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#pragma GCC target \"+fp8+bf16\"\n+#include \"test_sme2_acle.h\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tbfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svbfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_bf16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\nnew file mode 100644\nindex 00000000000..93792e90945\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_f16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..a9ee10de0df\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvt_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvt_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvt_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvt_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvt_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvt_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..2d0bd7eda0e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvtn_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvtn_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvtn_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvtn_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvtn_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvtn_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvtn_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvtn_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\nindex 7c156c4cf2a..8d4ed537c87 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n@@ -733,6 +733,7 @@\n #define TEST_X2_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register ZTYPE z5 __asm (\"z5\");\t\t\t\t\\\n register TTYPE z6 __asm (\"z6\");\t\t\t\t\\\n@@ -749,6 +750,7 @@\n #define TEST_X4_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register TTYPE z4 __asm (\"z4\");\t\t\t\t\\\n register TTYPE z16 __asm (\"z16\");\t\t\t\t\\\n", "prefixes": [ "v4", "3/8" ] }