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GET /api/1.0/patches/2175590/?format=api
{ "id": 2175590, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175590/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218142621.57402-9-claudio.bantaloukas@arm.com>", "date": "2025-12-18T14:26:20", "name": "[v4,8/8] aarch64: add 8-bit floating point dot product", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6d42f6618ad2696275163f45d125e14f1099ef3c", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-9-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485861, "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api", "date": "2025-12-18T14:26:12", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175590/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=pcxh/xtc;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=pcxh/xtc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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(sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Karl Meakin <karl.meakin@arm.com>", "Subject": "[PATCH v4 8/8] aarch64: add 8-bit floating point dot product", "Date": "Thu, 18 Dec 2025 14:26:20 +0000", "Message-ID": "<20251218142621.57402-9-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509E5:EE_|PAVPR08MB9772:EE_|AMS0EPF00000190:EE_|DB4PR08MB7933:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5f0908f6-0c72-4ff0-a9d5-08de3e41ad40", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|82310400026|376014|36860700013|1800799024|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n 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"gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Karl Meakin <karl.meakin@arm.com>\n\nThis patch adds support for the following intrinsics when sme-f8f16 is enabled:\n\t* svdot_za16[_mf8]_vg1x2_fpm\n\t* svdot_za16[_mf8]_vg1x4_fpm\n\t* svdot[_single]_za16[_mf8]_vg1x2_fpm\n\t* svdot[_single]_za16[_mf8]_vg1x4_fpm\n\t* svdot_lane_za16[_mf8]_vg1x2_fpm\n\t* svdot_lane_za16[_mf8]_vg1x4_fpm\n\nThis patch adds support for the following intrinsics when sme-f8f32 is enabled:\n\t* svdot_za32[_mf8]_vg1x2_fpm\n\t* svdot_za32[_mf8]_vg1x4_fpm\n\t* svdot[_single]_za32[_mf8]_vg1x2_fpm\n\t* svdot[_single]_za32[_mf8]_vg1x4_fpm\n\t* svdot_lane_za32[_mf8]_vg1x2_fpm\n\t* svdot_lane_za32[_mf8]_vg1x4_fpm\n\t* svvdot_lane_za32[_mf8]_vg1x2_fpm\n\t* svvdotb_lane_za32[_mf8]_vg1x4_fpm\n\t* svvdott_lane_za32[_mf8]_vg1x4_fpm\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-sme.md\n\t(@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>): New insn.\n\t(@aarch64_fvdot_half<optab>): Likewise.\n\t(@aarch64_fvdot_half<optab>_plus): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-functions.h\n\t(class svvdot_half_impl): New function impl.\n\t* config/aarch64/aarch64-sve-builtins-sme.cc (FUNCTION): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-shapes.cc (struct dot_half_za_slice_lane_def):\n\tNew function shape.\n\t* config/aarch64/aarch64-sve-builtins-shapes.h: Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sme.def (svdot): New function.\n\t(svdot_lane): Likewise.\n\t(svvdot_lane): Likewise.\n\t(svvdotb_lane): Likewise.\n\t(svvdott_lane): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sme.h (svvdotb_lane_za): New function.\n\t(svvdott_lane_za): Likewise.\n\t* config/aarch64/aarch64-sve-builtins.cc (TYPES_za_s_mf8): New types array.\n\t(TYPES_za_hs_mf8): Likewise.\n\t(za_hs_mf8): Likewise.\n\t* config/aarch64/iterators.md (SME_ZA_F8F16): New mode iterator.\n\t(SME_ZA_F8F32): Likewise.\n\t(SME_ZA_FP8_x1): Likewise.\n\t(SME_ZA_FP8_x2): Likewise.\n\t(SME_ZA_FP8_x4): Likewise.\n\t(UNSPEC_SME_FDOT_FP8): New unspec.\n\t(UNSPEC_SME_FVDOT_FP8): Likewise.\n\t(UNSPEC_SME_FVDOTT_FP8): Likewise.\n\t(UNSPEC_SME_FVDOTB_FP8): Likewise.\n\t(SME_FP8_DOTPROD): New int iterator.\n\t(SME_FP8_FVDOT): Likewise.\n\t(SME_FP8_FVDOT_HALF): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/vdot_lane_za32_mf8_vg1x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c: New test.\n\t* gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c: New test.\n\n(cherry picked from commit 1a4aca6e7a2baeac74b84391e5b92913b467f618)\n---\n gcc/config/aarch64/aarch64-sme.md | 310 ++++++++++++++++++\n .../aarch64/aarch64-sve-builtins-functions.h | 18 +\n .../aarch64/aarch64-sve-builtins-shapes.cc | 37 +++\n .../aarch64/aarch64-sve-builtins-shapes.h | 1 +\n .../aarch64/aarch64-sve-builtins-sme.cc | 13 +-\n .../aarch64/aarch64-sve-builtins-sme.def | 27 ++\n gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 +\n gcc/config/aarch64/aarch64-sve-builtins.cc | 9 +\n gcc/config/aarch64/iterators.md | 20 ++\n .../sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c | 119 +++++++\n .../sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c | 125 +++++++\n .../sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c | 119 +++++++\n .../sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c | 125 +++++++\n .../sme2/acle-asm/dot_single_za16_mf8_vg1x2.c | 126 +++++++\n .../sme2/acle-asm/dot_single_za16_mf8_vg1x4.c | 126 +++++++\n .../sme2/acle-asm/dot_single_za32_mf8_vg1x2.c | 126 +++++++\n .../sme2/acle-asm/dot_single_za32_mf8_vg1x4.c | 126 +++++++\n .../sme2/acle-asm/dot_za16_mf8_vg1x2.c | 150 +++++++++\n .../sme2/acle-asm/dot_za16_mf8_vg1x4.c | 166 ++++++++++\n .../sme2/acle-asm/dot_za32_mf8_vg1x2.c | 150 +++++++++\n .../sme2/acle-asm/dot_za32_mf8_vg1x4.c | 166 ++++++++++\n .../sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c | 119 +++++++\n .../sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c | 119 +++++++\n .../sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c | 119 +++++++\n .../general-c/dot_half_za_slice_lane_fpm.c | 106 ++++++\n 25 files changed, 2521 insertions(+), 3 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md\nindex 0e1cdafb6dc..5a2f09c4450 100644\n--- a/gcc/config/aarch64/aarch64-sme.md\n+++ b/gcc/config/aarch64/aarch64-sme.md\n@@ -45,6 +45,7 @@\n ;; ---- [INT] Ternary widening arithmetic on ZA slice\n ;; ---- [INT] Sum of outer products\n ;; ---- [FP] Dot product\n+;; ---- [FP8] Dot product\n ;; ---- [FP] Ternary arithmetic on ZA slice\n ;; ---- [FP] Ternary widening arithmetic on ZA slice\n ;; ---- [FP] Sum of outer products\n@@ -1892,6 +1893,315 @@ (define_insn \"*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plu\n \"<b><optab>\\tza.s[%w0, %1, vgx<vector_count>], %2, %3.h[%4]\"\n )\n \n+;; -------------------------------------------------------------------------\n+;; ---- [FP8] Dot product\n+;; -------------------------------------------------------------------------\n+;; Includes:\n+;; - FDOT (2-way, multiple vectors, FP8 to FP16)\n+;; - 2 ZA single-vectors (svdot_za16_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_za16_mf8_vg1x4_fpm)\n+;; - FDOT (4-way, multiple vectors)\n+;; - 2 ZA single-vectors (svdot_za32_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_za32_mf8_vg1x4_fpm)\n+\n+;; - FDOT (2-way, multiple and single vector, FP8 to FP16)\n+;; - 2 ZA single-vectors (svdot_single_za16_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_single_za16_mf8_vg1x4_fpm)\n+;; - FDOT (4-way, multiple and single vector)\n+;; - 2 ZA single-vectors (svdot_single_za32_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_single_za32_mf8_vg1x4_fpm)\n+\n+;; - FDOT (2-way, multiple and indexed vector, FP8 to FP16)\n+;; - 2 ZA single-vectors (svdot_lane_za16_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_lane_za16_mf8_vg1x4_fpm)\n+;; - FDOT (4-way, multiple and indexed vector)\n+;; - 2 ZA single-vectors (svdot_lane_za32_mf8_vg1x2_fpm)\n+;; - 4 ZA single-vectors (svdot_lane_za32_mf8_vg1x4_fpm)\n+\n+;; - FVDOT (FP8 to FP16)\n+;; - 2 ZA single-vectors (svvdot_lane_za16_mf8_vg1x2_fpm)\n+\n+;; - FVDOTB\n+;; - 2 ZA single-vectors (svvdotb_lane_za32_mf8_vg1x4_fpm)\n+\n+;; - FVDOTT\n+;; - 2 ZA single-vectors (svvdott_lane_za32_mf8_vg1x4_fpm)\n+;; -------------------------------------------------------------------------\n+\n+;; FDOT (2-way, multiple vectors, FP8 to FP16)\n+;; Two ZA single-vectors (svdot_za16_mf8_vg1x2_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm1> must be a multiple of 2\n+;; <Zm2> must be a multiple of 2 + 1\n+;; Four ZA single-vectors (svdot_za16_mf8_vg1x4_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 4\n+;; <Zn4> must be a multiple of 4 + 3\n+;; <Zm1> must be a multiple of 4\n+;; <Zm4> must be a multiple of 4 + 3\n+;; FDOT (4-way, multiple vectors)\n+;; Two ZA single-vectors (svdot_za32_mf8_vg1x2_fpm)\n+;; FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm1> must be a multiple of 2\n+;; <Zm2> must be a multiple of 2 + 1\n+;; Four ZA single-vectors (svdot_za32_mf8_vg1x4_fpm)\n+;; FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 4\n+;; <Zn2> must be a multiple of 4 + 3\n+;; <Zm1> must be a multiple of 4\n+;; <Zm2> must be a multiple of 4 + 3\n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x24 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:SME_ZA_FP8_x24 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0, vgx<vector_count>], %1, %2\"\n+)\n+(define_insn \"@aarch64_sme_<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_0_to_7_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:SME_ZA_FP8_x24 3 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, %1, vgx<vector_count>], %2, %3\"\n+)\n+\n+;; FDOT (2-way, multiple and single vector, FP8 to FP16)\n+;; Two ZA single-vectors (svdot_single_za16_mf8_vg1x2_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> can be any Z register\n+;; <Zn2> must be (<Zn1> + 1) mod 32\n+;; <Zm> must be Z0-Z15\n+;; Four ZA single-vectors (svdot_single_za16_mf8_vg1x4_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> can be any Z register\n+;; <Zn4> must be (<Zn1> + 3) mod 32\n+;; <Zm> must be Z0-Z15\n+;; FDOT (4-way, multiple and single vector)\n+;; Two ZA single-vectors (svdot_single_za32_mf8_vg1x2_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> can be any Z register\n+;; <Zn2> must be (<Zn1> + 1) mod 32\n+;; <Zm> must be Z0-Z15\n+;; Four ZA single-vectors (svdot_single_za32_mf8_vg1x2_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> can be any Z register\n+;; <Zn4> must be (<Zn1> + 3) mod 32\n+;; <Zm> must be Z0-Z15\n+(define_insn \"@aarch64_sme_single<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x24\t 1 \"register_operand\" \"w\")\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 2 \"register_operand\" \"x\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0, vgx<vector_count>], %1, %2.b\"\n+)\n+(define_insn \"@aarch64_sme_single<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_0_to_7_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24\t 2 \"register_operand\" \"w\")\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 3 \"register_operand\" \"x\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, %1, vgx<vector_count>], %2, %3.b\"\n+)\n+\n+;; FDOT (2-way, multiple and indexed vector, FP8 to FP16)\n+;; Two ZA single-vectors (svdot_lane_za16_mf8_vg1x2_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-7\n+;; Four ZA single-vectors (svdot_lane_za16_mf8_vg1x4_fpm)\n+;; FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 4\n+;; <Zn4> must be a multiple of 4 + 3\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-7\n+;; Two ZA single-vectors (svdot_lane_za32_mf8_vg1x2_fpm)\n+;; FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-3\n+;; Four ZA single-vectors (svdot_lane_za32_mf8_vg1x4_fpm)\n+;; FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 4\n+;; <Zn4> must be a multiple of 4 + 3\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-3\n+(define_insn \"@aarch64_sme_lane<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x24\t 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 2 \"register_operand\" \"x\")\n+\t (match_operand:SI 3 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, 0, vgx<vector_count>], %1, %2.b[%3]\"\n+)\n+(define_insn \"@aarch64_sme_lane<optab><SME_ZA_F8F16_32:mode><SME_ZA_FP8_x24:mode>_plus\"\n+ [(set (reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16_32\n+\t [(reg:SME_ZA_F8F16_32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_0_to_7_operand\"))\n+\t (match_operand:SME_ZA_FP8_x24\t 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:<SME_ZA_FP8_x24:VSINGLE> 3 \"register_operand\" \"x\")\n+\t (match_operand:SI 4 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_DOTPROD))]\n+ \"<SME_ZA_F8F16_32:MODE>mode == VNx8HImode\n+ ? TARGET_STREAMING_SME_F8F16\n+ : TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.<SME_ZA_F8F16_32:Vetype>[%w0, %1, vgx<vector_count>], %2, %3.b[%4]\"\n+)\n+\n+;; FVDOT (2-way, multiple and indexed vector, FP8 to FP16)\n+;; Two ZA single-vectors (svvdot_lane_za16_mf8_vg1x2_fpm)\n+;; FVDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-7\n+(define_insn \"@aarch64_sme_lane<optab><SME_ZA_F8F16:mode><SME_ZA_FP8_x2:mode>\"\n+ [(set (reg:SME_ZA_F8F16 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16\n+\t [(reg:SME_ZA_F8F16 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:SME_ZA_FP8_x2\t\t 1 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:<SME_ZA_FP8_x2:VSINGLE> 2 \"register_operand\" \"x\")\n+\t (match_operand:SI 3 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_FVDOT))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ \"<optab>\\tza.h[%w0, 0, vgx<vector_count>], %1, %2.b[%3]\"\n+)\n+(define_insn \"@aarch64_sme_lane<optab><SME_ZA_F8F16:mode><SME_ZA_FP8_x2:mode>_plus\"\n+ [(set (reg:SME_ZA_F8F16 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F16\n+\t [(reg:SME_ZA_F8F16 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_0_to_7_operand\"))\n+\t (match_operand:SME_ZA_FP8_x2\t\t 2 \"aligned_register_operand\" \"Uw<vector_count>\")\n+\t (match_operand:<SME_ZA_FP8_x2:VSINGLE> 3 \"register_operand\" \"x\")\n+\t (match_operand:SI 4 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_FVDOT))]\n+ \"TARGET_STREAMING_SME_F8F16\"\n+ \"<optab>\\tza.h[%w0, %1, vgx<vector_count>], %2, %3.b[%4]\"\n+)\n+\n+;; FVDOTB (svvdotb_lane_za32_mf8_vg1x4_fpm)\n+;; FVDOTT (svvdott_lane_za32_mf8_vg1x4_fpm)\n+;; FVDOTB ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]\n+;; FVDOTT ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]\n+;; <Wv> must be W8-W11\n+;; <offs> must be 0-7\n+;; <Zn1> must be a multiple of 2\n+;; <Zn2> must be a multiple of 2 + 1\n+;; <Zm> must be Z0-Z15\n+;; <index> must be 0-3\n+(define_insn \"@aarch64_fvdot_half<optab>\"\n+ [(set (reg:SME_ZA_F8F32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F32\n+\t [(reg:SME_ZA_F8F32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t (match_operand:VNx32QI 1 \"aligned_register_operand\" \"Uw2\")\n+\t (match_operand:VNx16QI 2 \"register_operand\" \"x\")\n+\t (match_operand:DI 3 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_FVDOT_HALF))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.s[%w0, 0, vgx4], %1, %2.b[%3]\"\n+)\n+(define_insn \"@aarch64_fvdot_half<optab>_plus\"\n+ [(set (reg:SME_ZA_F8F32 ZA_REGNUM)\n+\t(unspec:SME_ZA_F8F32\n+\t [(reg:SME_ZA_F8F32 ZA_REGNUM)\n+\t (reg:DI SME_STATE_REGNUM)\n+\t (plus:SI (match_operand:SI 0 \"register_operand\" \"Uci\")\n+\t\t (match_operand:SI 1 \"const_0_to_7_operand\"))\n+\t (match_operand:VNx32QI 2 \"aligned_register_operand\" \"Uw2\")\n+\t (match_operand:VNx16QI 3 \"register_operand\" \"x\")\n+\t (match_operand:DI 4 \"const_int_operand\")\n+\t (reg:DI FPM_REGNUM)]\n+\t SME_FP8_FVDOT_HALF))]\n+ \"TARGET_STREAMING_SME_F8F32\"\n+ \"<optab>\\tza.s[%w0, %1, vgx4], %2, %3.b[%4]\"\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP] Ternary arithmetic on ZA slice\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h\nindex f5cf6bfb899..67f145b15f9 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h\n@@ -483,6 +483,24 @@ public:\n }\n };\n \n+class svvdot_half_impl : public read_write_za<unspec_based_function_base>\n+{\n+public:\n+ using parent = read_write_za<unspec_based_function_base>;\n+\n+ CONSTEXPR svvdot_half_impl (int unspec_for_sint, int unspec_for_uint,\n+\t\t\t int unspec_for_fp, int unspec_for_mfp8)\n+ : parent (unspec_for_sint, unspec_for_uint, unspec_for_fp, unspec_for_mfp8,\n+\t 1)\n+ {}\n+\n+ rtx expand (function_expander &e) const override\n+ {\n+ insn_code icode = code_for_aarch64_fvdot_half (unspec_for (e));\n+ return e.use_exact_insn (icode);\n+ }\n+};\n+\n using sme_2mode_function\n = sme_2mode_function_t<code_for_aarch64_sme, code_for_aarch64_sme_single>;\n \ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\nindex ea4be3733c2..648f9439518 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc\n@@ -2507,6 +2507,43 @@ struct dot_za_slice_lane_def : public binary_za_slice_lane_base<>\n };\n SHAPE (dot_za_slice_lane)\n \n+/* void svvdott_lane_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x2_t zn,\n+\t\t\t\t\t svmfloat8_t zm, uint64_t imm_idx,\n+\t\t\t\t\t fpm_t fpm) __arm_streaming\n+\t\t\t\t\t\t __arm_inout (\"za\");\n+ void svvdotb_lane_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x2_t zn,\n+\t\t\t\t\t svmfloat8_t zm, uint64_t imm_idx,\n+\t\t\t\t\t fpm_t fpm) __arm_streaming\n+\t\t\t\t\t\t __arm_inout (\"za\"); */\n+struct dot_half_za_slice_lane_def : public binary_za_slice_lane_base<>\n+{\n+\n+ constexpr dot_half_za_slice_lane_def () : binary_za_slice_lane_base<> (0)\n+ {}\n+\n+ void build (function_builder &b,\n+\t const function_group_info &group) const override\n+ {\n+ b.add_overloaded_functions (group, MODE_none);\n+ build_all (b, \"_,su32,T1,v1,su64\", group, MODE_none);\n+ }\n+\n+ tree\n+ resolve (function_resolver &r) const override\n+ {\n+ sve_type type;\n+ if (!r.check_num_arguments (5)\n+\t|| !r.require_scalar_type (0, \"uint32_t\")\n+\t|| !(type = r.infer_vector_or_tuple_type (1, 2))\n+\t|| !r.require_vector_type (2, VECTOR_TYPE_svmfloat8_t)\n+\t|| !r.require_integer_immediate (3))\n+ return error_mark_node;\n+\n+ return r.resolve_to (r.mode_suffix_id, type);\n+ }\n+};\n+SHAPE (dot_half_za_slice_lane)\n+\n /* void svfoo_lane_t0[_t1]_g(uint32_t, sv<t1>x<g>_t, sv<t1:uint>_t, uint64_t)\n \n where the final argument indexes a <t0>-sized group of elements in the\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h\nindex 421cb1e8b85..c215cf9d254 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h\n@@ -126,6 +126,7 @@ namespace aarch64_sve\n extern const function_shape *const count_pred_c;\n extern const function_shape *const count_vector;\n extern const function_shape *const create;\n+ extern const function_shape *const dot_half_za_slice_lane;\n extern const function_shape *const dot_za_slice_int_lane;\n extern const function_shape *const dot_za_slice_lane;\n extern const function_shape *const dot_za_slice_uint_lane;\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\nindex 20a6ebc4059..0e63c68a9cb 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc\n@@ -628,10 +628,12 @@ FUNCTION (svcntsd, svcnts_bhwd_impl, (VNx2DImode))\n FUNCTION (svcntsh, svcnts_bhwd_impl, (VNx8HImode))\n FUNCTION (svcntsw, svcnts_bhwd_impl, (VNx4SImode))\n FUNCTION (svdot_za, sme_2mode_function, (UNSPEC_SME_SDOT, UNSPEC_SME_UDOT,\n-\t\t\t\t\t UNSPEC_SME_FDOT))\n+\t\t\t\t\t UNSPEC_SME_FDOT,\n+\t\t\t\t\t UNSPEC_SME_FDOT_FP8))\n FUNCTION (svdot_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SDOT,\n \t\t\t\t\t\t UNSPEC_SME_UDOT,\n-\t\t\t\t\t\t UNSPEC_SME_FDOT))\n+\t\t\t\t\t\t UNSPEC_SME_FDOT,\n+\t\t\t\t\t\t UNSPEC_SME_FDOT_FP8))\n FUNCTION (svld1_hor_za, svld1_za_impl, (UNSPEC_SME_LD1_HOR))\n FUNCTION (svld1_ver_za, svld1_za_impl, (UNSPEC_SME_LD1_VER))\n FUNCTION (svldr_za, svldr_za_impl, )\n@@ -683,7 +685,12 @@ FUNCTION (svusmopa_za, sme_2mode_function, (-1, UNSPEC_SME_USMOPA, -1))\n FUNCTION (svusmops_za, sme_2mode_function, (-1, UNSPEC_SME_USMOPS, -1))\n FUNCTION (svvdot_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SVDOT,\n \t\t\t\t\t\t UNSPEC_SME_UVDOT,\n-\t\t\t\t\t\t UNSPEC_SME_FVDOT))\n+\t\t\t\t\t\t UNSPEC_SME_FVDOT,\n+\t\t\t\t\t\t UNSPEC_SME_FVDOT_FP8))\n+FUNCTION (svvdotb_lane_za, svvdot_half_impl,\n+\t (-1, -1, -1, UNSPEC_SME_FVDOTB_FP8))\n+FUNCTION (svvdott_lane_za, svvdot_half_impl,\n+\t (-1, -1, -1, UNSPEC_SME_FVDOTT_FP8))\n FUNCTION (svwrite_za, svwrite_za_impl,)\n FUNCTION (svwrite_hor_za, svwrite_za_tile_impl, (UNSPEC_SME_WRITE_HOR))\n FUNCTION (svwrite_ver_za, svwrite_za_tile_impl, (UNSPEC_SME_WRITE_VER))\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\nindex 6306ee33a14..b4d00de63b4 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n@@ -218,6 +218,32 @@ DEF_SME_ZA_FUNCTION_GS (svmls_lane, binary_za_slice_lane, za_d_float,\n DEF_SME_ZA_FUNCTION_GS (svsub, unary_za_slice, za_d_float, vg1x24, none)\n #undef REQUIRED_EXTENSIONS\n \n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F16)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svdot, binary_za_slice_opt_single, za_h_mf8,\n+\t\t\t vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svdot_lane, dot_za_slice_lane, za_h_mf8,\n+\t\t\t vg1x24, none, set)\n+#undef REQUIRED_EXTENSIONS\n+\n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svdot, binary_za_slice_opt_single, za_s_mf8,\n+\t\t\t vg1x24, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svdot_lane, dot_za_slice_lane, za_s_mf8,\n+\t\t\t vg1x24, none, set)\n+#undef REQUIRED_EXTENSIONS\n+\n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F16)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svvdot_lane, dot_za_slice_lane, za_h_mf8,\n+\t\t\t vg1x2, none, set)\n+#undef REQUIRED_EXTENSIONS\n+\n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svvdotb_lane, dot_half_za_slice_lane, za_s_mf8,\n+\t\t\t vg1x4, none, set)\n+DEF_SME_ZA_FUNCTION_GS_FPM (svvdott_lane, dot_half_za_slice_lane, za_s_mf8,\n+\t\t\t vg1x4, none, set)\n+#undef REQUIRED_EXTENSIONS\n+\n #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F16F16)\n DEF_SME_ZA_FUNCTION_GS (svadd, unary_za_slice, za_h_float, vg1x24, none)\n DEF_SME_ZA_FUNCTION_GS (svmla, binary_za_slice_opt_single, za_h_float,\n@@ -283,4 +309,5 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_s_mf8, none, za_m, set)\n \n #undef DEF_SME_ZA_FUNCTION\n #undef DEF_SME_ZA_FUNCTION_GS\n+#undef DEF_SME_ZA_FUNCTION_GS_FPM\n #undef DEF_SME_FUNCTION\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.h b/gcc/config/aarch64/aarch64-sve-builtins-sme.h\nindex 4968f65442b..26761699127 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.h\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.h\n@@ -38,6 +38,8 @@ namespace aarch64_sve\n extern const function_base *const svcntsw;\n extern const function_base *const svdot_za;\n extern const function_base *const svdot_lane_za;\n+ extern const function_base *const svvdotb_lane_za;\n+ extern const function_base *const svvdott_lane_za;\n extern const function_base *const svld1_hor_za;\n extern const function_base *const svld1_ver_za;\n extern const function_base *const svldr_za;\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc\nindex 505a2445d1f..bf025adde89 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc\n@@ -668,6 +668,14 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {\n #define TYPES_za_h_mf8(S, D) \\\n D (za16, mf8)\n \n+/* _za32_mf8. */\n+#define TYPES_za_s_mf8(S, D) \\\n+ D (za32, mf8)\n+\n+/* { _za_16 _za_32 } x _mf8. */\n+#define TYPES_za_hs_mf8(S, D) \\\n+ D (za16, mf8), D (za32, mf8)\n+\n /* _za16_bf16. */\n #define TYPES_za_h_bfloat(S, D) \\\n D (za16, bf16)\n@@ -868,6 +876,7 @@ DEF_SVE_TYPES_ARRAY (za_s_h_data);\n DEF_SVE_TYPES_ARRAY (za_s_unsigned);\n DEF_SVE_TYPES_ARRAY (za_s_integer);\n DEF_SVE_TYPES_ARRAY (za_s_mf8);\n+DEF_SVE_TYPES_ARRAY (za_hs_mf8);\n DEF_SVE_TYPES_ARRAY (za_s_float);\n DEF_SVE_TYPES_ARRAY (za_s_data);\n DEF_SVE_TYPES_ARRAY (za_d_h_integer);\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 0a093a1b49c..1363eeddccd 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -758,12 +758,18 @@ (define_mode_iterator SME_ZA_BHIx24 [VNx32QI VNx64QI VNx16HI VNx32HI])\n (define_mode_iterator SME_ZA_HFx124 [VNx8BF VNx16BF VNx32BF\n \t\t\t\t VNx8HF VNx16HF VNx32HF])\n \n+(define_mode_iterator SME_ZA_F8F16 [(VNx8HI \"TARGET_STREAMING_SME_F8F16\")])\n+(define_mode_iterator SME_ZA_F8F32 [(VNx4SI \"TARGET_STREAMING_SME_F8F32\")])\n+\n (define_mode_iterator SME_ZA_F8F16_32 [(VNx8HI \"TARGET_STREAMING_SME_F8F16\")\n \t\t\t\t (VNx4SI \"TARGET_STREAMING_SME_F8F32\")])\n \n (define_mode_iterator SME_ZA_FP8_x24 [VNx32QI VNx64QI])\n \n (define_mode_iterator SME_ZA_FP8_x124 [VNx16QI VNx32QI VNx64QI])\n+(define_mode_iterator SME_ZA_FP8_x1 [VNx16QI])\n+(define_mode_iterator SME_ZA_FP8_x2 [VNx32QI])\n+(define_mode_iterator SME_ZA_FP8_x4 [VNx64QI])\n \n (define_mode_iterator SME_ZA_HFx24 [VNx16BF VNx32BF VNx16HF VNx32HF])\n \n@@ -1270,7 +1276,11 @@ (define_c_enum \"unspec\"\n UNSPEC_SME_BMOPS\n UNSPEC_SME_FADD\n UNSPEC_SME_FDOT\n+ UNSPEC_SME_FDOT_FP8\n UNSPEC_SME_FVDOT\n+ UNSPEC_SME_FVDOT_FP8\n+ UNSPEC_SME_FVDOTT_FP8\n+ UNSPEC_SME_FVDOTB_FP8\n UNSPEC_SME_FMLA\n UNSPEC_SME_FMLAL\n UNSPEC_SME_FMLS\n@@ -4066,6 +4076,12 @@ (define_int_iterator SME_INT_TERNARY_SLICE [UNSPEC_SME_SMLA UNSPEC_SME_SMLS\n (define_int_iterator SME_FP_TERNARY_SLICE [UNSPEC_SME_FMLA UNSPEC_SME_FMLS])\n \n (define_int_iterator SME_FP8_TERNARY_SLICE [UNSPEC_SME_FMLAL])\n+(define_int_iterator SME_FP8_DOTPROD [UNSPEC_SME_FDOT_FP8])\n+(define_int_iterator SME_FP8_FVDOT [UNSPEC_SME_FVDOT_FP8])\n+(define_int_iterator SME_FP8_FVDOT_HALF [\n+\tUNSPEC_SME_FVDOTB_FP8\n+\tUNSPEC_SME_FVDOTT_FP8\n+])\n \n ;; Iterators for atomic operations.\n \n@@ -4214,7 +4230,11 @@ (define_int_attr optab [(UNSPEC_ANDF \"and\")\n \t\t\t(UNSPEC_SME_BMOPS \"bmops\")\n \t\t\t(UNSPEC_SME_FADD \"fadd\")\n \t\t\t(UNSPEC_SME_FDOT \"fdot\")\n+\t\t\t(UNSPEC_SME_FDOT_FP8 \"fdot\")\n \t\t\t(UNSPEC_SME_FVDOT \"fvdot\")\n+\t\t\t(UNSPEC_SME_FVDOT_FP8 \"fvdot\")\n+\t\t\t(UNSPEC_SME_FVDOTB_FP8 \"fvdotb\")\n+\t\t\t(UNSPEC_SME_FVDOTT_FP8 \"fvdott\")\n \t\t\t(UNSPEC_SME_FMLA \"fmla\")\n \t\t\t(UNSPEC_SME_FMLAL \"fmlal\")\n \t\t\t(UNSPEC_SME_FMLS \"fmls\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..462834e4198\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c\n@@ -0,0 +1,119 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are:\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot_lane_za16[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (0, z0, z4, 0, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w0, z0, z7, 1, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8, z28, z4, 2, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dot_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p7_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dot_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p8_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0m1_z0_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z4\\.b - z5\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dot_lane_w8_z4_z15_2, svmfloat8x2_t, svmfloat8_t,\n+\t\t svdot_lane_za16_mf8_vg1x2_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svdot_lane_za16_vg1x2_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z16_3, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8, z28, z16, 3, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dot_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z17_z7_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8, z17, z7, 0, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dot_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z22\\.b - z23\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z22_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x2_fpm (w8, z22, z4, 1, fpm0),\n+\t svdot_lane_za16_vg1x2_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..b084a8007fc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c\n@@ -0,0 +1,125 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are:\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot_lane_za16[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_0_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (0, z0, z4, 0, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0_z0_z7_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z4_2, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dot_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p7_z0_z4_3, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dot_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p8_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0m1_z0_z4_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z4\\.b - z7\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dot_lane_w8_z4_z15_2, svmfloat8x4_t, svmfloat8_t,\n+\t\t svdot_lane_za16_mf8_vg1x4_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svdot_lane_za16_vg1x4_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z16_3, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8, z28, z16, 3, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dot_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z17_z7_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8, z17, z7, 0, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dot_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z22_z4_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za16_mf8_vg1x4_fpm (w8, z22, z4, 1, fpm0),\n+\t svdot_lane_za16_vg1x4_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..36e53a3d1fb\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c\n@@ -0,0 +1,119 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot_lane_za32[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (0, z0, z4, 0, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w0, z0, z7, 1, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8, z28, z4, 2, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dot_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p7_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dot_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p8_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0m1_z0_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z4\\.b - z5\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dot_lane_w8_z4_z15_2, svmfloat8x2_t, svmfloat8_t,\n+\t\t svdot_lane_za32_mf8_vg1x2_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svdot_lane_za32_vg1x2_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z16_3, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8, z28, z16, 3, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dot_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z17_z7_0, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8, z17, z7, 0, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dot_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z22\\.b - z23\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z22_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x2_fpm (w8, z22, z4, 1, fpm0),\n+\t svdot_lane_za32_vg1x2_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..97c0070b06b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c\n@@ -0,0 +1,125 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot_lane_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_0_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (0, z0, z4, 0, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0_z0_z7_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z4_2, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dot_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p7_z0_z4_3, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dot_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p8_z0_z4_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0m1_z0_z4_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z4\\.b - z7\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dot_lane_w8_z4_z15_2, svmfloat8x4_t, svmfloat8_t,\n+\t\t svdot_lane_za32_mf8_vg1x4_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svdot_lane_za32_vg1x4_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z16_3, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8, z28, z16, 3, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dot_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z17_z7_0, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8, z17, z7, 0, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dot_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z22_z4_1, svmfloat8x4_t, svmfloat8_t,\n+\t svdot_lane_za32_mf8_vg1x4_fpm (w8, z22, z4, 1, fpm0),\n+\t svdot_lane_za32_vg1x4_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..f7270551dcb\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c\n@@ -0,0 +1,126 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are:\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot[_single]_za16[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+/*\n+** dot_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (0, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w0, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p1_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8 + 1, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 2, vgx2\\], {z20\\.b - z21\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p2_z20_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8 + 2, z20, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** dot_single_w11p4_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w11, 4, vgx2\\], {z27\\.b - z28\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w11p4_z27_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w11 + 4, z27, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w11 + 4, z27, z0, fpm0))\n+\n+/*\n+** dot_single_w8p7_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p7_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8 + 7, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8 + 8, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0m1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w0 - 1, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (dot_single_w8_z0_z15, svmfloat8x2_t, svmfloat8_t,\n+\t\t svdot_single_za16_mf8_vg1x2_fpm (w8, z0, z15, fpm0),\n+\t\t svdot_za16_vg1x2_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** dot_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z20\\.b - z21\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z20_z16, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x2_fpm (w8, z20, z16, fpm0),\n+\t\tsvdot_za16_vg1x2_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..1976c5c686d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c\n@@ -0,0 +1,126 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are:\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot[_single]_za16[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+/*\n+** dot_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (0, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w0, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p1_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8 + 1, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 2, vgx4\\], {z20\\.b - z23\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p2_z20_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8 + 2, z20, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** dot_single_w11p4_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w11, 4, vgx4\\], {z27\\.b - z30\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w11p4_z27_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w11 + 4, z27, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w11 + 4, z27, z0, fpm0))\n+\n+/*\n+** dot_single_w8p7_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p7_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8 + 7, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8 + 8, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0m1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w0 - 1, z1, z0, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (dot_single_w8_z0_z15, svmfloat8x4_t, svmfloat8_t,\n+\t\t svdot_single_za16_mf8_vg1x4_fpm (w8, z0, z15, fpm0),\n+\t\t svdot_za16_vg1x4_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** dot_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z20\\.b - z23\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z20_z16, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za16_mf8_vg1x4_fpm (w8, z20, z16, fpm0),\n+\t\tsvdot_za16_vg1x4_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..d60c4580530\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c\n@@ -0,0 +1,126 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot[_single]_za32[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+/*\n+** dot_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (0, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w0, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p1_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 1, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8 + 1, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 2, vgx2\\], {z20\\.b - z21\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p2_z20_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8 + 2, z20, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** dot_single_w11p4_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w11, 4, vgx2\\], {z27\\.b - z28\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w11p4_z27_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w11 + 4, z27, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w11 + 4, z27, z0, fpm0))\n+\n+/*\n+** dot_single_w8p7_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p7_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8 + 7, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p8_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8 + 8, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z1\\.b - z2\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0m1_z1_z0, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w0 - 1, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (dot_single_w8_z0_z15, svmfloat8x2_t, svmfloat8_t,\n+\t\t svdot_single_za32_mf8_vg1x2_fpm (w8, z0, z15, fpm0),\n+\t\t svdot_za32_vg1x2_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** dot_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z20\\.b - z21\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z20_z16, svmfloat8x2_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x2_fpm (w8, z20, z16, fpm0),\n+\t\tsvdot_za32_vg1x2_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..ab1c1087f82\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c\n@@ -0,0 +1,126 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot[_single]_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+/*\n+** dot_single_0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (0, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w0, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w0, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p1_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 1, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8 + 1, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8 + 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p2_z20_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 2, vgx4\\], {z20\\.b - z23\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p2_z20_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8 + 2, z20, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8 + 2, z20, z0, fpm0))\n+\n+/*\n+** dot_single_w11p4_z27_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w11, 4, vgx4\\], {z27\\.b - z30\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w11p4_z27_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w11 + 4, z27, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w11 + 4, z27, z0, fpm0))\n+\n+/*\n+** dot_single_w8p7_z1_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p7_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8 + 7, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8 + 7, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8p8_z1_z0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8p8_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8 + 8, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8 + 8, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w0m1_z1_z0:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z1\\.b - z4\\.b}, z0\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w0m1_z1_z0, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w0 - 1, z1, z0, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w0 - 1, z1, z0, fpm0))\n+\n+/*\n+** dot_single_w8_z0_z15:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, z15\\.b\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_SINGLE_Z15 (dot_single_w8_z0_z15, svmfloat8x4_t, svmfloat8_t,\n+\t\t svdot_single_za32_mf8_vg1x4_fpm (w8, z0, z15, fpm0),\n+\t\t svdot_za32_vg1x4_fpm (w8, z0, z15, fpm0))\n+\n+/*\n+** dot_single_w8_z20_z16:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z20\\.b - z23\\.b}, \\1\\.b\n+**\tret\n+*/\n+TEST_ZA_SINGLE (dot_single_w8_z20_z16, svmfloat8x4_t, svmfloat8_t,\n+\t\tsvdot_single_za32_mf8_vg1x4_fpm (w8, z20, z16, fpm0),\n+\t\tsvdot_za32_vg1x4_fpm (w8, z20, z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..117d352061f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c\n@@ -0,0 +1,150 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot_za16[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8x2_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_0_z0_z0, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (0, z0, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** dot_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w0_z0_z0, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w0, z0, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** dot_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z4, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z0, z4, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** dot_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z4\\.b - z5\\.b}, {z18\\.b - z19\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z4_z18, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z4, z18, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** dot_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z23, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z0, z23, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** dot_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], [^\\n]+, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z23_z0, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z23, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** dot_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z18\\.b - z19\\.b}, {z28\\.b - z29\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z18_z28, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z18, z28, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** dot_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z28_z4, svmfloat8x2_t, svdot_za16_mf8_vg1x2_fpm (w8, z28, z4, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** dot_w8p1_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 1, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p1_z4_z0, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w8 + 1, z4, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 2, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p2_z4_z0, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w8 + 2, z4, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** dot_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w11, 4, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w11p4_z4_z0, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w11 + 4, z4, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p7_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p7_z4_z0, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w8 + 7, z4, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z4\\.b - z5\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p8_z4_z4, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w8 + 8, z4, z4, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** dot_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8m1_z4_z0, svmfloat8x2_t,\n+\t svdot_za16_mf8_vg1x2_fpm (w8 - 1, z4, z0, fpm0),\n+\t svdot_za16_vg1x2_fpm (w8 - 1, z4, z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..d28bc48db0f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c\n@@ -0,0 +1,166 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svdot_za16[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8x4_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_0_z0_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (0, z0, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** dot_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w0_z0_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w0, z0, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** dot_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z4, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z0, z4, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** dot_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z4\\.b - z7\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z4_z18, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z4, z18, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** dot_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z23, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z0, z23, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** dot_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z23_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z23, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** dot_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z24\\.b - z27\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z18_z28, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z18, z28, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** dot_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z28_z4, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8, z28, z4, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** dot_w8p1_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 1, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p1_z4_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8 + 1, z4, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 2, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p2_z4_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8 + 2, z4, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** dot_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w11, 4, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w11p4_z4_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w11 + 4, z4, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p7_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[w8, 7, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p7_z4_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8 + 7, z4, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z4\\.b - z7\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p8_z4_z4, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8 + 8, z4, z4, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** dot_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.h\\[\\1, 0, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8m1_z4_z0, svmfloat8x4_t,\n+\t svdot_za16_mf8_vg1x4_fpm (w8 - 1, z4, z0, fpm0),\n+\t svdot_za16_vg1x4_fpm (w8 - 1, z4, z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..225e18ac05d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c\n@@ -0,0 +1,150 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot_za32[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8x2_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_0_z0_z0, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (0, z0, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** dot_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w0_z0_z0, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w0, z0, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** dot_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z4, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z0, z4, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** dot_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z4\\.b - z5\\.b}, {z18\\.b - z19\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z4_z18, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z4, z18, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** dot_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z0\\.b - z1\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z23, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z0, z23, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** dot_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], [^\\n]+, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z23_z0, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z23, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** dot_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z18\\.b - z19\\.b}, {z28\\.b - z29\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z18_z28, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z18, z28, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** dot_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z28_z4, svmfloat8x2_t, svdot_za32_mf8_vg1x2_fpm (w8, z28, z4, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** dot_w8p1_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 1, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p1_z4_z0, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w8 + 1, z4, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 2, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p2_z4_z0, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w8 + 2, z4, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** dot_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w11, 4, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w11p4_z4_z0, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w11 + 4, z4, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p7_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p7_z4_z0, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w8 + 7, z4, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z4\\.b - z5\\.b}, {z4\\.b - z5\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p8_z4_z4, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w8 + 8, z4, z4, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** dot_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx2\\], {z4\\.b - z5\\.b}, {z0\\.b - z1\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8m1_z4_z0, svmfloat8x2_t,\n+\t svdot_za32_mf8_vg1x2_fpm (w8 - 1, z4, z0, fpm0),\n+\t svdot_za32_vg1x2_fpm (w8 - 1, z4, z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..667ba3238dd\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c\n@@ -0,0 +1,166 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svdot_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x4_t zn, svmfloat8x4_t zm, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_0_z0_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (0, z0, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (0, z0, z0, fpm0))\n+\n+/*\n+** dot_w0_z0_z0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z3\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w0_z0_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w0, z0, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w0, z0, z0, fpm0))\n+\n+/*\n+** dot_w8_z0_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z4, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z0, z4, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z0, z4, fpm0))\n+\n+/*\n+** dot_w8_z4_z18:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z4\\.b - z7\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z4_z18, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z4, z18, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z4, z18, fpm0))\n+\n+/* Leave the assembler to check for correctness for misaligned registers. */\n+\n+/*\n+** dot_w8_z0_z23:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z0\\.b - z3\\.b}, [^\\n]+\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z0_z23, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z0, z23, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z0, z23, fpm0))\n+\n+/*\n+** dot_w8_z23_z0:\n+**\tmsr\tfpmr, x1\n+**\t...\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], [^\\n]+, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z23_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z23, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z23, z0, fpm0))\n+\n+/*\n+** dot_w8_z18_z28:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z24\\.b - z27\\.b}, {z28\\.b - z31\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z18_z28, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z18, z28, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z18, z28, fpm0))\n+\n+/*\n+** dot_w8_z28_z4:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z31\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8_z28_z4, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8, z28, z4, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8, z28, z4, fpm0))\n+\n+/*\n+** dot_w8p1_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 1, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p1_z4_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8 + 1, z4, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8 + 1, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p2_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 2, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p2_z4_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8 + 2, z4, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8 + 2, z4, z0, fpm0))\n+\n+/*\n+** dot_w11p4_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w11, 4, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w11p4_z4_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w11 + 4, z4, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w11 + 4, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p7_z4_z0:\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[w8, 7, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p7_z4_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8 + 7, z4, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8 + 7, z4, z0, fpm0))\n+\n+/*\n+** dot_w8p8_z4_z4:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z4\\.b - z7\\.b}, {z4\\.b - z7\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8p8_z4_z4, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8 + 8, z4, z4, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8 + 8, z4, z4, fpm0))\n+\n+/*\n+** dot_w8m1_z4_z0:\n+**\tsub\t(w8|w9|w10|w11), w8, #?1\n+**\tmsr\tfpmr, x1\n+**\tfdot\tza\\.s\\[\\1, 0, vgx4\\], {z4\\.b - z7\\.b}, {z0\\.b - z3\\.b}\n+**\tret\n+*/\n+TEST_ZA_XN (dot_w8m1_z4_z0, svmfloat8x4_t,\n+\t svdot_za32_mf8_vg1x4_fpm (w8 - 1, z4, z0, fpm0),\n+\t svdot_za32_vg1x4_fpm (w8 - 1, z4, z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c\nnew file mode 100644\nindex 00000000000..a25c64be59d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c\n@@ -0,0 +1,119 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f16_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f16_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f16\"\n+\n+/* Available variants are:\n+ _za16 if __ARM_FEATURE_SME_F8F16 != 0\n+ void svvdot_lane_za16[_mf8]_vg1x2_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dot_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfvdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (0, z0, z4, 0, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfvdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w0, z0, z7, 1, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8, z28, z4, 2, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dot_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[w8, 7, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p7_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dot_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8p8_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dot_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[\\1, 0, vgx2\\], {z0\\.b - z1\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w0m1_z0_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dot_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[w8, 0, vgx2\\], {z4\\.b - z5\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dot_lane_w8_z4_z15_2, svmfloat8x2_t, svmfloat8_t,\n+\t\t svvdot_lane_za16_mf8_vg1x2_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svvdot_lane_za16_vg1x2_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dot_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfvdot\tza\\.h\\[w8, 0, vgx2\\], {z28\\.b - z29\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z28_z16_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8, z28, z16, 3, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dot_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfvdot\tza\\.h\\[w8, 0, vgx2\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z17_z7_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8, z17, z7, 0, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dot_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tfvdot\tza\\.h\\[w8, 0, vgx2\\], {z22\\.b - z23\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dot_lane_w8_z22_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdot_lane_za16_mf8_vg1x2_fpm (w8, z22, z4, 1, fpm0),\n+\t svvdot_lane_za16_vg1x2_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..8b2987f91a1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c\n@@ -0,0 +1,119 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svvdotb_lane_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dotb_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfvdotb\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (0, z0, z4, 0, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dotb_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfvdotb\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dotb_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dotb_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[w8, 7, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8p7_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dotb_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8p8_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dotb_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w0m1_z0_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dotb_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[w8, 0, vgx4\\], {z4\\.b - z5\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dotb_lane_w8_z4_z15_2, svmfloat8x2_t, svmfloat8_t,\n+\t\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svvdotb_lane_za32_vg1x4_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dotb_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfvdotb\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z29\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8_z28_z16_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8, z28, z16, 3, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dotb_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfvdotb\tza\\.s\\[w8, 0, vgx4\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8_z17_z7_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8, z17, z7, 0, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dotb_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tfvdotb\tza\\.s\\[w8, 0, vgx4\\], {z22\\.b - z23\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dotb_lane_w8_z22_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdotb_lane_za32_mf8_vg1x4_fpm (w8, z22, z4, 1, fpm0),\n+\t svvdotb_lane_za32_vg1x4_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c\nnew file mode 100644\nindex 00000000000..4d9a8e4078f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c\n@@ -0,0 +1,119 @@\n+/* { dg-do assemble { target { aarch64_asm_sme-f8f32_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_sme-f8f32_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svvdott_lane_za32[_mf8]_vg1x4_fpm (uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+/*\n+** dott_lane_0_z0_z4_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), #?0\n+**\tfvdott\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_0_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (0, z0, z4, 0, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (0, z0, z4, 0, fpm0))\n+\n+/*\n+** dott_lane_w0_z0_z7_1:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(w8|w9|w10|w11), w0\n+**\tfvdott\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z7\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w0_z0_z7_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w0, z0, z7, 1, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w0, z0, z7, 1, fpm0))\n+\n+/*\n+** dott_lane_w8_z28_z4_2:\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z29\\.b}, z4\\.b\\[2\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8_z28_z4_2, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8, z28, z4, 2, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8, z28, z4, 2, fpm0))\n+\n+/*\n+** dott_lane_w8p7_z0_z4_3:\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[w8, 7, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8p7_z0_z4_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8 + 7, z0, z4, 3, fpm0))\n+\n+/*\n+** dott_lane_w8p8_z0_z4_0:\n+**\tadd\t(w8|w9|w10|w11), w8, #?8\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8p8_z0_z4_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8 + 8, z0, z4, 0, fpm0))\n+\n+/*\n+** dott_lane_w0m1_z0_z4_1:\n+**\tsub\t(w8|w9|w10|w11), w0, #?1\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[\\1, 0, vgx4\\], {z0\\.b - z1\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w0m1_z0_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w0 - 1, z0, z4, 1, fpm0))\n+\n+/*\n+** dott_lane_w8_z4_z15_2:\n+**\tstr\td15, \\[sp, #?-16\\]!\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[w8, 0, vgx4\\], {z4\\.b - z5\\.b}, z15\\.b\\[2\\]\n+**\tldr\td15, \\[sp\\], #?16\n+**\tret\n+*/\n+TEST_ZA_LANE_Z15 (dott_lane_w8_z4_z15_2, svmfloat8x2_t, svmfloat8_t,\n+\t\t svvdott_lane_za32_mf8_vg1x4_fpm (w8, z4, z15, 2, fpm0),\n+\t\t svvdott_lane_za32_vg1x4_fpm (w8, z4, z15, 2, fpm0))\n+\n+/*\n+** dott_lane_w8_z28_z16_3:\n+**\tmsr\tfpmr, x1\n+**\tmov\t(z[0-7]).d, z16.d\n+**\tfvdott\tza\\.s\\[w8, 0, vgx4\\], {z28\\.b - z29\\.b}, \\1\\.b\\[3\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8_z28_z16_3, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8, z28, z16, 3, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8, z28, z16, 3, fpm0))\n+\n+/*\n+** dott_lane_w8_z17_z7_0:\n+**\tmsr\tfpmr, x1\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfvdott\tza\\.s\\[w8, 0, vgx4\\], [^\\n]+, z7\\.b\\[0\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8_z17_z7_0, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8, z17, z7, 0, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8, z17, z7, 0, fpm0))\n+\n+/*\n+** dott_lane_w8_z22_z4_1:\n+**\tmsr\tfpmr, x1\n+**\tfvdott\tza\\.s\\[w8, 0, vgx4\\], {z22\\.b - z23\\.b}, z4\\.b\\[1\\]\n+**\tret\n+*/\n+TEST_ZA_LANE (dott_lane_w8_z22_z4_1, svmfloat8x2_t, svmfloat8_t,\n+\t svvdott_lane_za32_mf8_vg1x4_fpm (w8, z22, z4, 1, fpm0),\n+\t svvdott_lane_za32_vg1x4_fpm (w8, z22, z4, 1, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c\nnew file mode 100644\nindex 00000000000..69ba85b6398\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c\n@@ -0,0 +1,106 @@\n+// { dg-options \"-std=c23 -fsyntax-only\" }\n+// { dg-do compile }\n+\n+#pragma GCC target \"+sve2,+sme-f8f32\"\n+static_assert (__ARM_FEATURE_SME_F8F32 == 1);\n+#include <arm_sme.h>\n+\n+/* Available variants are:\n+ _za32 if __ARM_FEATURE_SME_F8F32 != 0\n+ void svvdotb_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\");\n+ void svvdott_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout(\"za\"); */\n+\n+void\n+svvdotb_lane_ok (uint32_t slice, svmfloat8x2_t zn_f8x2, svmfloat8_t zm_f8,\n+\t\t fpm_t fpm) __arm_streaming __arm_inout (\"za\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm);\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm);\n+}\n+\n+void\n+svvdotb_lane_error_not_streaming (uint32_t slice, svmfloat8x2_t zn_f8x2,\n+\t\t\t\t svmfloat8_t zm_f8,\n+\t\t\t\t fpm_t fpm) __arm_inout (\"za\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called when SME streaming mode is enabled} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called when SME streaming mode is enabled} }\n+}\n+\n+void\n+svvdotb_lane_error_streaming_compatible (uint32_t slice, svmfloat8x2_t zn_f8x2,\n+\t\t\t\t\t svmfloat8_t zm_f8,\n+\t\t\t\t\t fpm_t fpm) __arm_streaming_compatible\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called when SME streaming mode is enabled} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called when SME streaming mode is enabled} }\n+}\n+\n+void\n+svvdotb_lane_error_not_inout (uint32_t slice, svmfloat8x2_t zn_f8x2,\n+\t\t\t svmfloat8_t zm_f8, fpm_t fpm) __arm_streaming\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called from a function that has 'za' state} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' can only be called from a function that has 'za' state} }\n+}\n+\n+void\n+svvdotb_lane_error_arg_count_mismatch (\n+ uint32_t slice, svmfloat8x2_t zn_f8x2, svmfloat8_t zm_f8,\n+ fpm_t fpm) __arm_streaming __arm_inout (\"za\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (); // { dg-error {too few arguments to function 'svvdotb_lane_za32_mf8_vg1x4_fpm'; expected 5, have 0} }\n+ svvdotb_lane_za32_vg1x4_fpm (); // { dg-error {too few arguments to function 'svvdotb_lane_za32_vg1x4_fpm'} }\n+\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm, 0); // { dg-error {too many arguments to function 'svvdotb_lane_za32_mf8_vg1x4_fpm'; expected 5, have 6} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm, 0); // { dg-error {too many arguments to function 'svvdotb_lane_za32_vg1x4_fpm'} }\n+}\n+\n+void\n+svvdotb_lane_error_arg_type_mismatch (\n+ uint32_t slice, svmfloat8x2_t zn_f8x2, svmfloat8x4_t zn_f8x4,\n+ svmfloat8_t zm_f8, fpm_t fpm) __arm_streaming __arm_inout (\"za\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (zm_f8, zn_f8x2, zm_f8, 0, fpm); // { dg-error {incompatible type for argument 1 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+ svvdotb_lane_za32_vg1x4_fpm (zm_f8, zn_f8x2, zm_f8, 0, fpm); // { dg-error {passing 'svmfloat8_t' to argument 1 of 'svvdotb_lane_za32_vg1x4_fpm', which expects 'uint32_t'} }\n+\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x4, zm_f8, 0, fpm); // { dg-error {incompatible type for argument 2 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x4, zm_f8, 0, fpm); // { dg-error {passing 'svmfloat8x4_t' to argument 2 of 'svvdotb_lane_za32_vg1x4_fpm', which expects a tuple of 2 vectors} }\n+\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zn_f8x2, 0, fpm); // { dg-error {incompatible type for argument 3 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zn_f8x2, 0, fpm); // { dg-error {passing 'svmfloat8x2_t' to argument 3 of 'svvdotb_lane_za32_vg1x4_fpm', which expects 'svmfloat8_t'} }\n+\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, zm_f8, fpm); // { dg-error {incompatible type for argument 4 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, zm_f8, fpm); // { dg-error {argument 4 of 'svvdotb_lane_za32_vg1x4_fpm' must be an integer constant expression} }\n+\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, zm_f8); // { dg-error {incompatible type for argument 5 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, zm_f8); // { dg-error {incompatible type for argument 5 of 'svvdotb_lane_za32_mf8_vg1x4_fpm'} }\n+}\n+\n+void\n+svvdotb_lane_error_imm_idx_not_immediate (\n+ uint32_t slice, svmfloat8x2_t zn_f8x2, svmfloat8_t zm_f8, uint64_t imm_idx,\n+ fpm_t fpm) __arm_streaming __arm_in (\"zt0\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, imm_idx, fpm); // { dg-error {argument 4 of 'svvdotb_lane_za32_mf8_vg1x4_fpm' must be an integer constant expression} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, imm_idx, fpm); // { dg-error {argument 4 of 'svvdotb_lane_za32_vg1x4_fpm' must be an integer constant expression} }\n+}\n+\n+void\n+svvdotb_lane_error_imm_idx_not_in_range (\n+ uint32_t slice, svmfloat8x2_t zn_f8x2, svmfloat8_t zm_f8,\n+ fpm_t fpm) __arm_streaming __arm_in (\"zt0\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, -1, fpm); // { dg-error {passing -1 to argument 4 of 'svvdotb_lane_za32_mf8_vg1x4_fpm', which expects a value in the range \\[0, 3\\]} }\n+ svvdotb_lane_za32_vg1x4_fpm (slice, zn_f8x2, zm_f8, -1, fpm); // { dg-error {passing -1 to argument 4 of 'svvdotb_lane_za32_vg1x4_fpm', which expects a value in the range \\[0, 3\\]} }\n+}\n+\n+#pragma GCC reset_options\n+#pragma GCC target(\"+sve2,+sme2\")\n+void\n+svvdotb_lane_feature_not_enabled (uint32_t slice, svmfloat8x2_t zn_f8x2,\n+\t\t\t\t svmfloat8_t zm_f8,\n+\t\t\t\t fpm_t fpm) __arm_streaming __arm_inout (\"za\")\n+{\n+ svvdotb_lane_za32_mf8_vg1x4_fpm (slice, zn_f8x2, zm_f8, 0, fpm); // { dg-error {ACLE function 'svvdotb_lane_za32_mf8_vg1x4_fpm' requires ISA extension 'sme-f8f32'} }\n+}\n", "prefixes": [ "v4", "8/8" ] }