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{
    "id": 2175588,
    "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175588/?format=api",
    "project": {
        "id": 17,
        "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api",
        "name": "GNU Compiler Collection",
        "link_name": "gcc",
        "list_id": "gcc-patches.gcc.gnu.org",
        "list_email": "gcc-patches@gcc.gnu.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20251218142621.57402-5-claudio.bantaloukas@arm.com>",
    "date": "2025-12-18T14:26:16",
    "name": "[v4,4/8] aarch64: add multi-vector floating-point adjust exponent intrinsics",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "efa6e702edd0dc551106f7f49d7e09d2457d6334",
    "submitter": {
        "id": 88972,
        "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api",
        "name": "Claudio Bantaloukas",
        "email": "claudio.bantaloukas@arm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-5-claudio.bantaloukas@arm.com/mbox/",
    "series": [
        {
            "id": 485861,
            "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api",
            "date": "2025-12-18T14:26:12",
            "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4",
            "version": 4,
            "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/"
        }
    ],
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2175588/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>",
        "X-Original-To": [
            "incoming@patchwork.ozlabs.org",
            "gcc-patches@gcc.gnu.org"
        ],
        "Delivered-To": [
            "patchwork-incoming@legolas.ozlabs.org",
            "gcc-patches@gcc.gnu.org"
        ],
        "Authentication-Results": [
            "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=MnN8nV5w;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=MnN8nV5w;\n\tdkim-atps=neutral",
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        ],
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        "DKIM-Filter": [
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        ],
        "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 7AF1B4BA2E36",
        "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 7AF1B4BA2E36",
        "ARC-Seal": [
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            "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=S5Ljn400srEOVxCn70dGdJ5d9T5TOoobJT3vRctRJnpq7xJKat8hpwX6vcckq47P/CLB5nyV25G6cj++b44YICYDh1RMdrg+hL/4nxBVyidW9NbRRApTpeSz9Re0BC3cwq4o4YEVCA+EnIx5yTdQlWdL9Ljk7pA04khzJ0innki83PvpLQZzwiQevdBF5eh1qXmCypcIn3WWi4zGMvGxRjauOiABKMEdUl0Nv/z5S+X+ASm01DCqGZead4pkMK2Dxh58nAwrJpY6b86ffXBzRLoSSrBR2zCeJk3ICYp7ndUztIygFNq8uRz1+MOgEm6u8kiX/qMEfLjh7CcYAPgJ8Q==",
            "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=HiYfw0AVqcjL2Vwpo0VRIhuEidoo6PUjeLgs+QyUgXnCdH4nub1Zw0bVFEtfyKt496ywcLjVUZ9aT1e0lGGLx+Pz7AE5FnkB5oaEOoT5/Kk23fXQOqdkUzluS5P2s0hcqSBtgE3PUA+iop8AwpXat7RBIfzzDkjEGyMuDTTMWgLEHoQYHUhH0m5cmCCvZTkoqRytVCSgwG+Wnhl85bJ77SFvsdc9XWMfOPeWDYbYjna0BBDxBl7nioX/KcL8SIvmJollfI5zh0cNqFuJl1nkkFkeyto1lXqhU+izRMDdFF+ie2005iIYiM7LWnMOSvaoyQSR2ujLZvOwcT0e6Aen+Q=="
        ],
        "ARC-Message-Signature": [
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        ],
        "ARC-Authentication-Results": [
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        "DKIM-Signature": [
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        ],
        "X-MS-Exchange-Authentication-Results": [
            "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;",
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        ],
        "Received-SPF": [
            "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C",
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        ],
        "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>",
        "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>",
        "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>",
        "Subject": "[PATCH v4 4/8] aarch64: add multi-vector floating-point adjust\n exponent intrinsics",
        "Date": "Thu, 18 Dec 2025 14:26:16 +0000",
        "Message-ID": "<20251218142621.57402-5-claudio.bantaloukas@arm.com>",
        "X-Mailer": "git-send-email 2.51.0",
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        "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-EOPAttributedMessage": "1",
        "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509E5:EE_|AS4PR08MB7712:EE_|DB1PEPF00039233:EE_|PA4PR08MB6127:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "a16097a7-adb6-4b0a-0735-08de3e41a09e",
        "x-checkrecipientrouted": "true",
        "NoDisclaimer": "true",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
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        "X-Microsoft-Antispam-Message-Info-Original": "\n SZyeuLBHlztv40t/X+oL/3r/J9CtWRkTUjbarUOKmvbrMszKyeyd7M+dKtofcUVDXM0jqJOjho5AmJxqQDY7AgGXu99z8yPe2SpZ92+/kSgZuz8UdFcb3OJqcDHgDiv1wknCmmmi7kcA0YlXKSTvAfoE317VWpbodt5Wh0dZ1DfQVZN+1wg+1xvoc2PLkPy+U8gA7+jKOL3DJYGIE1YYTMfcf6HDz/kM14wIeppLaTAtZz3Gz7qgav8weUojb5lUwgqBCOiWuSzlhXxaoSzfYkI0fLOTrZLOc8OvqvWt8hm0sNg9cO8XQoUQA5DTfuj/yDaOi1tTmISqOlFKyaMuad0hSN3dzgcYF6KaYK+Uj993GTV4GFdj12/c3GLrRkq7/etJwhS7Kx7/WkiCBxrmFfSmn5MKCmtI/SFPr9bAizR/jQVXNYYoTp7iICwbchU/U0NXqGnKwHVbjk2ydXeub/gqMNc+BefZVyY+Vlm4i5Y1ptAuatV919wdW+x62D7ULUfvNwO3vmfRNy/pXj8+l+89EhC+x0/T4rYtCwRXbfrPLnKl7abAJT2dmVhQo4ayL6WcJ1sKbA30+7n3n623PwihBtq3PA1uejZ0UU0/8y9asMvFvn+qHst3r2a72BM/wxDc3hmfJbXYIyoVrHkk9VfEG+FUUsCura68QM4Yrpxb3Flx7P3tB/7oHqua/gZAkwH8yMyrGjdsRW0ORLI8xg6xclW3rE2Qae402VGwKnIfUU+qJaMXg4Khctew4b5F6XDF1EI5+Vr+pQEF4w0/ogP1yO6QVilH098JLkn/3mqn0+40QXYclBz2jeMEA+IXdySnAEV8PyyJWhuu6jm4mlihdcEndPE6NcX6eXOQp3ZpMnh8HR+le4iAn+78Mu+PPTQAte147b87l4/zZ09L7OK5aHl3kkcIM72Jp9wYhXhqsN/X1yBpIiiJMr5K1jOioOuUBrqv0UgHBVe7bXWJ1RAEQiRUuQ1TUhGz73eDUV85JzJUjtXsWEgjp+b4rkNBGKGCzI0Gub57pIjqH+paz0IEkmwCsrVv3zbpahUNc0iSsx+maDqx33bWxW/uTeaPFunePoeHSBBMjRAJaebVVPOKUfFJpl8hU433krF/yIah69XzordslT0sLKDYJm70SUiXrmMQ75ULUT/QwAtERlbf15S+nbFcwmIJ4oyvhtu6GttAU9mm4cEN1woGC/oi4a8sEE3YUvO2VVMCbNFh4vPtRvi/+cpflH+c7Xg6HAuVB4wxJKuvT5iBtgPE/PROsbdcgNlwUIhKmj9pbLrhyLtPnt2xI0hn7EiwuLp8D47oYU0ZKP/TDjRWapucUwXnc1x5XwIpu8AoP0Bl1eqAWhLe5apRvO3yNLPRL1et0FTiF5sXmkQq+3iQuGyHeaYyWuPseP4fC1kQETrYw9UOjGBRO07tGICygsUCsXAkJ61y24i3WTeMOu53XBIhI0NV3N0QgsM5q94pxlqSTS6q5UfjXnBUcDcPEQoL8P5h6qQv7UM23h44y/Ti/u935zZ2pMSfd1odADP2PZzSABofh8RsO0kB/sTRaXbRHCkEOn387yf19HVW+1NSo2C21ZnL",
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        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [
            "AS4PR08MB7712",
            "PA4PR08MB6127"
        ],
        "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n DB1PEPF00039233.eurprd03.prod.outlook.com",
        "X-MS-PublicTrafficType": "Email",
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    "content": "This patch adds the following intrinsics (all __arm_streaming only) along with\nasm tests for them.\n\n- FSCALE (multiple and single vector)\n\t- svfloat16x2_t svscale[_single_f16_x2](svfloat16x2_t zd, svint16_t zm)\n\t- svfloat32x2_t svscale[_single_f32_x2](svfloat32x2_t zd, svint32_t zm)\n\t- svfloat64x2_t svscale[_single_f64_x2](svfloat64x2_t zd, svint64_t zm)\n\t- svfloat16x4_t svscale[_single_f16_x4](svfloat16x4_t zd, svint16_t zm)\n\t- svfloat32x4_t svscale[_single_f32_x4](svfloat32x4_t zd, svint32_t zm)\n\t- svfloat64x4_t svscale[_single_f64_x4](svfloat64x4_t zd, svint64_t zm)\n\n- FSCALE (multiple vectors)\n\t- svfloat16x2_t svscale[_f16_x2](svfloat16x2_t zd, svint16x2_t zm)\n\t- svfloat32x2_t svscale[_f32_x2](svfloat32x2_t zd, svint32x2_t zm)\n\t- svfloat64x2_t svscale[_f64_x2](svfloat64x2_t zd, svint64x2_t zm)\n\t- svfloat16x4_t svscale[_f16_x4](svfloat16x4_t zd, svint16x4_t zm)\n\t- svfloat32x4_t svscale[_f32_x4](svfloat32x4_t zd, svint32x4_t zm)\n\t- svfloat64x4_t svscale[_f64_x4](svfloat64x4_t zd, svint64x4_t zm)\n\nTest structure is based on the urshl ones that have a similar structure in how\nthey treat arguments.\n\ngcc/\n\t* config/aarch64/aarch64-sve-builtins-base.cc (svscale_impl): Added new\n\tclass for dealing with all svscale functions (including sve)\n\t(svscale): updated FUNCTION macro call to make use of new class.\n\t* src/gcc/gcc/config/aarch64/aarch64-sve-builtins-sve2.def: (svscale):\n\tAdded new DEF_SVE_FUNCTION_GS call to enable recognition of new variant.\n\t* config/aarch64/aarch64-sve2.md (@aarch64_sve_fscale<mode>): Added\n\tnew define_insn. (@aarch64_sve_single_fscale<mode>): Likewise.\n\t* config/aarch64/iterators.md: (SVE_Fx24_NOBF): Added new iterator,\n\tsimilar to SVE_Fx24 but without brainfloat.\n\t(SVE_Fx24): Updated to make use of SVE_Fx24_NOBF.\n\t(SVSCALE_SINGLE_INTARG): Added new mode_attr.\n\t(SVSCALE_INTARG): Likewise.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c: : Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c: : Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c: : Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c: : Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c: : Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c: : Likewise.\n---\n .../aarch64/aarch64-sve-builtins-base.cc      |  21 +-\n .../aarch64/aarch64-sve-builtins-sve2.def     |   1 +\n gcc/config/aarch64/aarch64-sve2.md            |  28 +++\n gcc/config/aarch64/iterators.md               |  24 +-\n .../aarch64/sme2/acle-asm/scale_f16_x2.c      | 192 +++++++++++++++\n .../aarch64/sme2/acle-asm/scale_f16_x4.c      | 229 ++++++++++++++++++\n .../aarch64/sme2/acle-asm/scale_f32_x2.c      | 208 ++++++++++++++++\n .../aarch64/sme2/acle-asm/scale_f32_x4.c      | 229 ++++++++++++++++++\n .../aarch64/sme2/acle-asm/scale_f64_x2.c      | 208 ++++++++++++++++\n .../aarch64/sme2/acle-asm/scale_f64_x4.c      | 229 ++++++++++++++++++\n 10 files changed, 1366 insertions(+), 3 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c",
    "diff": "diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\nindex 622485effb3..ca6e16578e8 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n@@ -3465,6 +3465,25 @@ public:\n   unsigned int m_base;\n };\n \n+class svscale_impl : public function_base\n+{\n+public:\n+  rtx\n+  expand (function_expander &e) const override\n+  {\n+    if (vectors_per_tuple (e) == 1)\n+      return e.map_to_unspecs (-1, -1, UNSPEC_COND_FSCALE);\n+    else\n+      {\n+\tmachine_mode mode = GET_MODE (e.args[0]);\n+\tinsn_code code = (e.mode_suffix_id == MODE_single\n+\t  ? code_for_aarch64_sve_single_fscale (mode)\n+\t  : code_for_aarch64_sve_fscale (mode));\n+\treturn e.use_exact_insn (code);\n+      }\n+  }\n+};\n+\n } /* end anonymous namespace */\n \n namespace aarch64_sve {\n@@ -3706,7 +3725,7 @@ FUNCTION (svrintx, svrint_impl, (rint_optab, UNSPEC_COND_FRINTX))\n FUNCTION (svrintz, svrint_impl, (btrunc_optab, UNSPEC_COND_FRINTZ))\n FUNCTION (svrsqrte, unspec_based_function, (-1, UNSPEC_RSQRTE, UNSPEC_RSQRTE))\n FUNCTION (svrsqrts, unspec_based_function, (-1, -1, UNSPEC_RSQRTS))\n-FUNCTION (svscale, unspec_based_function, (-1, -1, UNSPEC_COND_FSCALE))\n+FUNCTION (svscale, svscale_impl,)\n FUNCTION (svsel, svsel_impl,)\n FUNCTION (svset2, svset_impl, (2))\n FUNCTION (svset3, svset_impl, (3))\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\nindex 869e006ffde..bbee4234388 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n@@ -428,4 +428,5 @@ DEF_SVE_FUNCTION_GS_FPM (svcvt1, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt2, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvtl1, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvtl2, unary_convert, cvt_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS (svscale, binary_int_opt_single_n, all_float, x24, none)\n #undef REQUIRED_EXTENSIONS\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex da7a7a3c23c..11cc53bbb50 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -58,6 +58,7 @@\n ;; ---- [INT] Saturating left shifts\n ;; ---- [FP] Non-widening bfloat16 arithmetic\n ;; ---- [FP] Clamp to minimum/maximum\n+;; ---- [FP] Scaling by powers of two\n ;;\n ;; == Uniform ternary arithmnetic\n ;; ---- [INT] General ternary arithmetic that maps to unspecs\n@@ -1481,6 +1482,33 @@ (define_insn \"@aarch64_sve_fclamp_single<mode>\"\n   [(set_attr \"sve_type\" \"sve_fp_arith\")]\n )\n \n+;; -------------------------------------------------------------------------\n+;; ---- [FP] Scaling by powers of two\n+;; -------------------------------------------------------------------------\n+;; Includes the multiple and single vector and multiple vectors forms of\n+;; - FSCALE\n+;; -------------------------------------------------------------------------\n+\n+(define_insn \"@aarch64_sve_fscale<mode>\"\n+  [(set (match_operand:SVE_Fx24_NOBF 0 \"register_operand\" \"=Uw<vector_count>\")\n+\t(unspec:SVE_Fx24_NOBF\n+\t  [(match_operand:SVE_Fx24_NOBF 1 \"register_operand\" \"0\")\n+\t   (match_operand:<SVSCALE_INTARG> 2 \"register_operand\" \"Uw<vector_count>\")]\n+\t  UNSPEC_FSCALE))]\n+  \"TARGET_STREAMING_SME2 && TARGET_FP8\"\n+  \"fscale\\t%0, %1, %2\"\n+)\n+\n+(define_insn \"@aarch64_sve_single_fscale<mode>\"\n+  [(set (match_operand:SVE_Fx24_NOBF 0 \"register_operand\" \"=Uw<vector_count>\")\n+\t(unspec:SVE_Fx24_NOBF\n+\t  [(match_operand:SVE_Fx24_NOBF 1 \"register_operand\" \"0\")\n+\t   (match_operand:<SVSCALE_SINGLE_INTARG> 2 \"register_operand\" \"x\")]\n+\t  UNSPEC_FSCALE))]\n+  \"TARGET_STREAMING_SME2 && TARGET_FP8\"\n+  \"fscale\\t%0, %1, %2.<Vetype>\"\n+)\n+\n ;; =========================================================================\n ;; == Uniform ternary arithmnetic\n ;; =========================================================================\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex e6f59d22d0c..a98f514b8ec 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -735,10 +735,12 @@ (define_mode_iterator SVE_BHSx24 [VNx32QI VNx16HI VNx8SI\n (define_mode_iterator SVE_Ix24 [VNx32QI VNx16HI VNx8SI VNx4DI\n \t\t\t\tVNx64QI VNx32HI VNx16SI VNx8DI])\n \n+(define_mode_iterator SVE_Fx24_NOBF [VNx16HF VNx8SF VNx4DF\n+\t\t\t\t     VNx32HF VNx16SF VNx8DF])\n+\n (define_mode_iterator SVE_Fx24 [(VNx16BF \"TARGET_SSVE_B16B16\")\n \t\t\t\t(VNx32BF \"TARGET_SSVE_B16B16\")\n-\t\t\t\tVNx16HF VNx8SF VNx4DF\n-\t\t\t\tVNx32HF VNx16SF VNx8DF])\n+\t\t\t\tSVE_Fx24_NOBF])\n \n (define_mode_iterator SVE_SFx24 [VNx8SF VNx16SF])\n \n@@ -2790,6 +2792,24 @@ (define_mode_attr aligned_fpr [(VNx16QI \"w\") (VNx8HI \"w\")\n (define_mode_attr LD1_EXTENDQ_MEM [(VNx4SI \"VNx1SI\") (VNx4SF \"VNx1SI\")\n \t\t\t\t   (VNx2DI \"VNx1DI\") (VNx2DF \"VNx1DI\")])\n \n+;; Maps the output type of svscale to the corresponding int vector type in the\n+;; second argument.\n+(define_mode_attr SVSCALE_SINGLE_INTARG [(VNx16HF \"VNx8HI\") ;; f16_x2 -> s16\n+\t\t\t\t\t (VNx32HF \"VNx8HI\") ;; f16_x4 -> s16\n+\t\t\t\t\t (VNx8SF \"VNx4SI\") ;; f32_x2 -> s32\n+\t\t\t\t\t (VNx16SF \"VNx4SI\") ;; f32_x4 -> s32\n+\t\t\t\t\t (VNx4DF \"VNx2DI\") ;; f64_x2 -> s64\n+\t\t\t\t\t (VNx8DF \"VNx2DI\") ;; f64_x4 -> s64\n+])\n+\n+(define_mode_attr SVSCALE_INTARG [(VNx16HF \"VNx16HI\") ;; f16_x2 -> s16x2\n+\t\t\t\t  (VNx32HF \"VNx32HI\") ;; f16_x4 -> s16x4\n+\t\t\t\t  (VNx8SF \"VNx8SI\") ;; f32_x2 -> s32_x2\n+\t\t\t\t  (VNx16SF \"VNx16SI\") ;; f32_x4 -> s32_x4\n+\t\t\t\t  (VNx4DF \"VNx4DI\") ;; f64_x2 -> s64_x2\n+\t\t\t\t  (VNx8DF \"VNx8DI\") ;; f64_x4 -> s64_x4\n+])\n+\n ;; -------------------------------------------------------------------\n ;; Code Iterators\n ;; -------------------------------------------------------------------\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c\nnew file mode 100644\nindex 00000000000..4535a94c1bf\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c\n@@ -0,0 +1,192 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** scale_z0_z0_z4:\n+**\tfscale\t{z0\\.h - z1\\.h}, {z0\\.h - z1\\.h}, {z4\\.h - z5\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z0_z0_z4, svfloat16x2_t, svint16x2_t, z0,\n+\t svscale_f16_x2 (z0, z4),\n+\t svscale (z0, z4))\n+\n+/*\n+** scale_z4_z4_z0:\n+**\tfscale\t{z4\\.h - z5\\.h}, {z4\\.h - z5\\.h}, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z4_z4_z0, svint16x2_t, svfloat16x2_t, z4,\n+\t svscale_f16_x2 (z4, z0),\n+\t svscale (z4, z0))\n+\n+/*\n+** scale_z18_z18_z4:\n+**\tfscale\t{z18\\.h - z19\\.h}, {z18\\.h - z19\\.h}, {z4\\.h - z5\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z18_z18_z4, svfloat16x2_t, svint16x2_t, z18,\n+\t svscale_f16_x2 (z18, z4),\n+\t svscale (z18, z4))\n+\n+/*\n+** scale_z23_z23_z18:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z18\\.h - z19\\.h}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z23_z23_z18, svint16x2_t, svfloat16x2_t, z23,\n+\t svscale_f16_x2 (z23, z18),\n+\t svscale (z23, z18))\n+\n+\n+/*\n+** scale_z28_z28_z4:\n+**\tfscale\t{z28\\.h - z29\\.h}, {z28\\.h - z29\\.h}, {z4\\.h - z5\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z28_z28_z4, svfloat16x2_t, svint16x2_t, z28,\n+\t svscale_f16_x2 (z28, z4),\n+\t svscale (z28, z4))\n+\n+/*\n+** scale_z4_z4_z18:\n+**\tfscale\t{z4\\.h - z5\\.h}, {z4\\.h - z5\\.h}, {z18\\.h - z19\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z4_z4_z18, svint16x2_t, svfloat16x2_t, z4,\n+\t svscale_f16_x2 (z4, z18),\n+\t svscale (z4, z18))\n+\n+/*\n+** scale_z28_28_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z28\\.h - z29\\.h}, {z28\\.h - z29\\.h}, [^\\n]+\n+** |\n+**\tfscale\t{z28\\.h - z29\\.h}, {z28\\.h - z29\\.h}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (scale_z28_28_z23, svfloat16x2_t, svint16x2_t, z28,\n+\t svscale_f16_x2 (z28, z23),\n+\t svscale (z28, z23))\n+\n+/*\n+** scale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.h - z25\\.h}, {z24\\.h - z25\\.h}, z0\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z24_z24_z0, svfloat16x2_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** scale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.h - z25\\.h}, {z24\\.h - z25\\.h}, z0\\.h\n+** |\n+**\tfscale\t{z28\\.h - z29\\.h}, {z28\\.h - z29\\.h}, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z24_z28_z0, svfloat16x2_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x2 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** scale_single_z24_z1_z0:\n+** (\n+**\tmov\tz24\\.d, z1\\.d\n+**\tmov\tz25\\.d, z2\\.d\n+** |\n+**\tmov\tz25\\.d, z2\\.d\n+**\tmov\tz24\\.d, z1\\.d\n+** )\n+**\tfscale\t{z24\\.h - z25\\.h}, {z24\\.h - z25\\.h}, z0\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z24_z1_z0, svfloat16x2_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** scale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.h - z25\\.h}, {z24\\.h - z25\\.h}, z0\\.h\n+** (\n+**\tmov\tz1\\.d, z24\\.d\n+**\tmov\tz2\\.d, z25\\.d\n+** |\n+**\tmov\tz2\\.d, z25\\.d\n+**\tmov\tz1\\.d, z24\\.d\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z1_z24_z0, svfloat16x2_t, svint16_t, z1,\n+\t\tsvscale_single_f16_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** scale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.h - z[0-9]+\\.h}), \\1, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z1_z1_z0, svfloat16x2_t, svint16_t, z1,\n+\t\tsvscale_single_f16_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** scale_single_z18_z18_z0:\n+**\tfscale\t{z18\\.h - z19\\.h}, {z18\\.h - z19\\.h}, z0\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z18_z18_z0, svfloat16x2_t, svint16_t, z18,\n+\t\tsvscale_single_f16_x2 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** scale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.h - z[0-9]+\\.h}), \\1, z[0-9]+\\.h\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (scale_single_awkward, svfloat16x2_t, svint16_t,\n+\t\t\tz0_res = svscale_single_f16_x2 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** scale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.h - z1\\.h}, {z0\\.h - z1\\.h}, z15\\.h\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (scale_single_z0_z0_z15, svfloat16x2_t, svint16_t,\n+\t\t    z0 = svscale_single_f16_x2 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** scale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.h - z25\\.h}, {z24\\.h - z25\\.h}, \\1\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (scale_single_z24_z24_z16, svfloat16x2_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x2 (z24, z16),\n+\t\tsvscale (z24, z16))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c\nnew file mode 100644\nindex 00000000000..b3c5a482052\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c\n@@ -0,0 +1,229 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** fscale_z0_z0_z4:\n+**\tfscale\t{z0\\.h - z3\\.h}, {z0\\.h - z3\\.h}, {z4\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z0_z0_z4, svfloat16x4_t, svint16x4_t, z0,\n+\t      svscale_f16_x4 (z0, z4),\n+\t      svscale (z0, z4))\n+\n+/*\n+** fscale_z4_z4_z0:\n+**\tfscale\t{z4\\.h - z7\\.h}, {z4\\.h - z7\\.h}, {z0\\.h - z3\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z4_z4_z0, svint16x4_t, svfloat16x4_t, z4,\n+\t      svscale_f16_x4 (z4, z0),\n+\t      svscale (z4, z0))\n+\n+/*\n+** fscale_z18_z18_z4:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z4\\.h - z7\\.h}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z18_z18_z4, svfloat16x4_t, svint16x4_t, z18,\n+\t      svscale_f16_x4 (z18, z4),\n+\t      svscale (z18, z4))\n+\n+/*\n+** fscale_z23_z23_z28:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z28\\.h - z31\\.h}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z23_z23_z28, svint16x4_t, svfloat16x4_t, z23,\n+\t      svscale_f16_x4 (z23, z28),\n+\t      svscale (z23, z28))\n+\n+/*\n+** fscale_z28_z28_z4:\n+**\tfscale\t{z28\\.h - z31\\.h}, {z28\\.h - z31\\.h}, {z4\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z28_z28_z4, svfloat16x4_t, svint16x4_t, z28,\n+\t      svscale_f16_x4 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** fscale_z4_z4_z18:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z4\\.h - z7\\.h}, {z4\\.h - z7\\.h}, [^\\n]+\n+** |\n+**\tfscale\t{z4\\.h - z7\\.h}, {z4\\.h - z7\\.h}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z4_z4_z18, svint16x4_t, svfloat16x4_t, z4,\n+\t      svscale_f16_x4 (z4, z18),\n+\t      svscale (z4, z18))\n+\n+/*\n+** fscale_z0_z0_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z0\\.h - z3\\.h}, {z0\\.h - z3\\.h}, [^\\n]+\n+** |\n+**\tfscale\t{z0\\.h - z3\\.h}, {z0\\.h - z3\\.h}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (fscale_z0_z0_z23, svfloat16x4_t, svint16x4_t, z0,\n+\t      svscale_f16_x4 (z0, z23),\n+\t      svscale (z0, z23))\n+\n+/*\n+** fscale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.h - z27\\.h}, {z24\\.h - z27\\.h}, z0\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z24_z24_z0, svfloat16x4_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** fscale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.h - z27\\.h}, {z24\\.h - z27\\.h}, z0\\.h\n+** |\n+**\tfscale\t{z28\\.h - z31\\.h}, {z28\\.h - z31\\.h}, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z24_z28_z0, svfloat16x4_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x4 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** fscale_single_z24_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.h - z27\\.h}, {z24\\.h - z27\\.h}, z0\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z24_z1_z0, svfloat16x4_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** fscale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.h - z27\\.h}, {z24\\.h - z27\\.h}, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z1_z24_z0, svfloat16x4_t, svint16_t, z1,\n+\t\tsvscale_single_f16_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** fscale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.h - z[0-9]+\\.h}), \\1, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z1_z1_z0, svfloat16x4_t, svint16_t, z1,\n+\t\tsvscale_single_f16_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** fscale_single_z18_z18_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, z0\\.h\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z18_z18_z0, svfloat16x4_t, svint16_t, z18,\n+\t\tsvscale_single_f16_x4 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** fscale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.h - z[0-9]+\\.h}), \\1, z[0-9]+\\.h\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (fscale_single_awkward, svfloat16x4_t, svint16_t,\n+\t\t\tz0_res = svscale_single_f16_x4 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** fscale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.h - z3\\.h}, {z0\\.h - z3\\.h}, z15\\.h\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (fscale_single_z0_z0_z15, svfloat16x4_t, svint16_t,\n+\t\t    z0 = svscale_single_f16_x4 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** fscale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.h - z27\\.h}, {z24\\.h - z27\\.h}, \\1\\.h\n+**\tret\n+*/\n+TEST_XN_SINGLE (fscale_single_z24_z24_z16, svfloat16x4_t, svint16_t, z24,\n+\t\tsvscale_single_f16_x4 (z24, z16),\n+\t\tsvscale (z24, z16))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c\nnew file mode 100644\nindex 00000000000..2375ea60596\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c\n@@ -0,0 +1,208 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** svscale_z0_z0_z4:\n+**\tfscale\t{z0\\.s - z1\\.s}, {z0\\.s - z1\\.s}, {z4\\.s - z5\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z4, svfloat32x2_t, svint32x2_t, z0,\n+\t      svscale_f32_x2 (z0, z4),\n+\t      svscale (z0, z4))\n+\n+/*\n+** svscale_z4_z4_z0:\n+**\tfscale\t{z4\\.s - z5\\.s}, {z4\\.s - z5\\.s}, {z0\\.s - z1\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z0, svint32x2_t, svfloat32x2_t, z4,\n+\t      svscale_f32_x2 (z4, z0),\n+\t      svscale (z4, z0))\n+\n+/*\n+** svscale_z0_z28_z4:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z4\\.s - z5\\.s}\n+** |\n+**\tfscale\t[^\\n]+, {z4\\.s - z5\\.s}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z28_z4, svfloat32x2_t, svint32x2_t, z0,\n+\t      svscale_f32_x2 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z18_z18_z4:\n+**\tfscale\t{z18\\.s - z19\\.s}, {z18\\.s - z19\\.s}, {z4\\.s - z5\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z18_z18_z4, svfloat32x2_t, svint32x2_t, z18,\n+\t      svscale_f32_x2 (z18, z4),\n+\t      svscale (z18, z4))\n+\n+/*\n+** svscale_z23_z23_z18:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z18\\.s - z19\\.s}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z23_z23_z18, svint32x2_t, svfloat32x2_t, z23,\n+\t      svscale_f32_x2 (z23, z18),\n+\t      svscale (z23, z18))\n+\n+/*\n+** svscale_z28_z28_z4:\n+**\tfscale\t{z28\\.s - z29\\.s}, {z28\\.s - z29\\.s}, {z4\\.s - z5\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z4, svfloat32x2_t, svint32x2_t, z28,\n+\t      svscale_f32_x2 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z4_z4_z18:\n+**\tfscale\t{z4\\.s - z5\\.s}, {z4\\.s - z5\\.s}, {z18\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z18, svint32x2_t, svfloat32x2_t, z4,\n+\t      svscale_f32_x2 (z4, z18),\n+\t      svscale (z4, z18))\n+\n+/*\n+** svscale_z28_z28_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z28\\.s - z29\\.s}, {z28\\.s - z29\\.s}, [^\\n]+\n+** |\n+**\tfscale\t{z28\\.s - z29\\.s}, {z28\\.s - z29\\.s}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z23, svfloat32x2_t, svint32x2_t, z28,\n+\t      svscale_f32_x2 (z28, z23),\n+\t      svscale (z28, z23))\n+\n+/*\n+** svscale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.s - z25\\.s}, {z24\\.s - z25\\.s}, z0\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z0, svfloat32x2_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.s - z25\\.s}, {z24\\.s - z25\\.s}, z0\\.s\n+** |\n+**\tfscale\t{z28\\.s - z29\\.s}, {z28\\.s - z29\\.s}, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z28_z0, svfloat32x2_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x2 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** svscale_single_z24_z1_z0:\n+** (\n+**\tmov\tz24\\.d, z1\\.d\n+**\tmov\tz25\\.d, z2\\.d\n+** |\n+**\tmov\tz25\\.d, z2\\.d\n+**\tmov\tz24\\.d, z1\\.d\n+** )\n+**\tfscale\t{z24\\.s - z25\\.s}, {z24\\.s - z25\\.s}, z0\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z1_z0, svfloat32x2_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.s - z25\\.s}, {z24\\.s - z25\\.s}, z0\\.s\n+** (\n+**\tmov\tz1\\.d, z24\\.d\n+**\tmov\tz2\\.d, z25\\.d\n+** |\n+**\tmov\tz2\\.d, z25\\.d\n+**\tmov\tz1\\.d, z24\\.d\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z24_z0, svfloat32x2_t, svint32_t, z1,\n+\t\tsvscale_single_f32_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.s - z[0-9]+\\.s}), \\1, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z1_z0, svfloat32x2_t, svint32_t, z1,\n+\t\tsvscale_single_f32_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z18_z18_z0:\n+**\tfscale\t{z18\\.s - z19\\.s}, {z18\\.s - z19\\.s}, z0\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z18_z18_z0, svfloat32x2_t, svint32_t, z18,\n+\t\tsvscale_single_f32_x2 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** svscale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.s - z[0-9]+\\.s}), \\1, z[0-9]+\\.s\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (svscale_single_awkward, svfloat32x2_t, svint32_t,\n+\t\t\tz0_res = svscale_single_f32_x2 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** svscale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.s - z1\\.s}, {z0\\.s - z1\\.s}, z15\\.s\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (svscale_single_z0_z0_z15, svfloat32x2_t, svint32_t,\n+\t\t    z0 = svscale_single_f32_x2 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** svscale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.s - z25\\.s}, {z24\\.s - z25\\.s}, \\1\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z16, svfloat32x2_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x2 (z24, z16),\n+\t\tsvscale (z24, z16))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c\nnew file mode 100644\nindex 00000000000..fc50de86ed3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c\n@@ -0,0 +1,229 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** svscale_z0_z0_z4:\n+**\tfscale\t{z0\\.s - z3\\.s}, {z0\\.s - z3\\.s}, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z4, svfloat32x4_t, svint32x4_t, z0,\n+\t      svscale_f32_x4 (z0, z4),\n+\t      svscale (z0, z4))\n+\n+/*\n+** svscale_z4_z4_z0:\n+**\tfscale\t{z4\\.s - z7\\.s}, {z4\\.s - z7\\.s}, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z0, svint32x4_t, svfloat32x4_t, z4,\n+\t      svscale_f32_x4 (z4, z0),\n+\t      svscale (z4, z0))\n+\n+/*\n+** svscale_z18_z18_z4:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z4\\.s - z7\\.s}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z18_z18_z4, svfloat32x4_t, svint32x4_t, z18,\n+\t      svscale_f32_x4 (z18, z4),\n+\t      svscale (z18, z4))\n+\n+/*\n+** svscale_z23_z23_z28:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z28\\.s - z31\\.s}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z23_z23_z28, svint32x4_t, svfloat32x4_t, z23,\n+\t      svscale_f32_x4 (z23, z28),\n+\t      svscale (z23, z28))\n+\n+/*\n+** svscale_z28_z28_z4:\n+**\tfscale\t{z28\\.s - z31\\.s}, {z28\\.s - z31\\.s}, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z4, svfloat32x4_t, svint32x4_t, z28,\n+\t      svscale_f32_x4 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z4_z4_z18:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z4\\.s - z7\\.s}, {z4\\.s - z7\\.s}, [^\\n]+\n+** |\n+**\tfscale\t{z4\\.s - z7\\.s}, {z4\\.s - z7\\.s}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z18, svint32x4_t, svfloat32x4_t, z4,\n+\t      svscale_f32_x4 (z4, z18),\n+\t      svscale (z4, z18))\n+\n+/*\n+** svscale_z0_z0_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z0\\.s - z3\\.s}, {z0\\.s - z3\\.s}, [^\\n]+\n+** |\n+**\tfscale\t{z0\\.s - z3\\.s}, {z0\\.s - z3\\.s}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z23, svfloat32x4_t, svint32x4_t, z0,\n+\t      svscale_f32_x4 (z0, z23),\n+\t      svscale (z0, z23))\n+\n+/*\n+** svscale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.s - z27\\.s}, {z24\\.s - z27\\.s}, z0\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z0, svfloat32x4_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.s - z27\\.s}, {z24\\.s - z27\\.s}, z0\\.s\n+** |\n+**\tfscale\t{z28\\.s - z31\\.s}, {z28\\.s - z31\\.s}, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z28_z0, svfloat32x4_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x4 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** svscale_single_z24_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.s - z27\\.s}, {z24\\.s - z27\\.s}, z0\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z1_z0, svfloat32x4_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.s - z27\\.s}, {z24\\.s - z27\\.s}, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z24_z0, svfloat32x4_t, svint32_t, z1,\n+\t\tsvscale_single_f32_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.s - z[0-9]+\\.s}), \\1, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z1_z0, svfloat32x4_t, svint32_t, z1,\n+\t\tsvscale_single_f32_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z18_z18_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, z0\\.s\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z18_z18_z0, svfloat32x4_t, svint32_t, z18,\n+\t\tsvscale_single_f32_x4 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** svscale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.s - z[0-9]+\\.s}), \\1, z[0-9]+\\.s\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (svscale_single_awkward, svfloat32x4_t, svint32_t,\n+\t\t\tz0_res = svscale_single_f32_x4 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** svscale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.s - z3\\.s}, {z0\\.s - z3\\.s}, z15\\.s\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (svscale_single_z0_z0_z15, svfloat32x4_t, svint32_t,\n+\t\t    z0 = svscale_single_f32_x4 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** svscale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.s - z27\\.s}, {z24\\.s - z27\\.s}, \\1\\.s\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z16, svfloat32x4_t, svint32_t, z24,\n+\t\tsvscale_single_f32_x4 (z24, z16),\n+\t\tsvscale (z24, z16))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c\nnew file mode 100644\nindex 00000000000..cedd918ed35\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c\n@@ -0,0 +1,208 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** svscale_z0_z0_z4:\n+**\tfscale\t{z0\\.d - z1\\.d}, {z0\\.d - z1\\.d}, {z4\\.d - z5\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z4, svfloat64x2_t, svint64x2_t, z0,\n+\t      svscale_f64_x2 (z0, z4),\n+\t      svscale (z0, z4))\n+\n+/*\n+** svscale_z4_z4_z0:\n+**\tfscale\t{z4\\.d - z5\\.d}, {z4\\.d - z5\\.d}, {z0\\.d - z1\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z0, svint64x2_t, svfloat64x2_t, z4,\n+\t      svscale_f64_x2 (z4, z0),\n+\t      svscale (z4, z0))\n+\n+/*\n+** svscale_z0_z28_z4:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z4\\.d - z5\\.d}\n+** |\n+**\tfscale\t[^\\n]+, {z4\\.d - z5\\.d}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z28_z4, svfloat64x2_t, svint64x2_t, z0,\n+\t      svscale_f64_x2 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z18_z18_z4:\n+**\tfscale\t{z18\\.d - z19\\.d}, {z18\\.d - z19\\.d}, {z4\\.d - z5\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z18_z18_z4, svfloat64x2_t, svint64x2_t, z18,\n+\t      svscale_f64_x2 (z18, z4),\n+\t      svscale (z18, z4))\n+\n+/*\n+** svscale_z23_z23_z18:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z18\\.d - z19\\.d}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z23_z23_z18, svint64x2_t, svfloat64x2_t, z23,\n+\t      svscale_f64_x2 (z23, z18),\n+\t      svscale (z23, z18))\n+\n+/*\n+** svscale_z28_z28_z4:\n+**\tfscale\t{z28\\.d - z29\\.d}, {z28\\.d - z29\\.d}, {z4\\.d - z5\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z4, svfloat64x2_t, svint64x2_t, z28,\n+\t      svscale_f64_x2 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z4_z4_z18:\n+**\tfscale\t{z4\\.d - z5\\.d}, {z4\\.d - z5\\.d}, {z18\\.d - z19\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z18, svint64x2_t, svfloat64x2_t, z4,\n+\t      svscale_f64_x2 (z4, z18),\n+\t      svscale (z4, z18))\n+\n+/*\n+** svscale_z28_z28_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z28\\.d - z29\\.d}, {z28\\.d - z29\\.d}, [^\\n]+\n+** |\n+**\tfscale\t{z28\\.d - z29\\.d}, {z28\\.d - z29\\.d}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z23, svfloat64x2_t, svint64x2_t, z28,\n+\t      svscale_f64_x2 (z28, z23),\n+\t      svscale (z28, z23))\n+\n+/*\n+** svscale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.d - z25\\.d}, {z24\\.d - z25\\.d}, z0\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z0, svfloat64x2_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.d - z25\\.d}, {z24\\.d - z25\\.d}, z0\\.d\n+** |\n+**\tfscale\t{z28\\.d - z29\\.d}, {z28\\.d - z29\\.d}, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z28_z0, svfloat64x2_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x2 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** svscale_single_z24_z1_z0:\n+** (\n+**\tmov\tz24\\.d, z1\\.d\n+**\tmov\tz25\\.d, z2\\.d\n+** |\n+**\tmov\tz25\\.d, z2\\.d\n+**\tmov\tz24\\.d, z1\\.d\n+** )\n+**\tfscale\t{z24\\.d - z25\\.d}, {z24\\.d - z25\\.d}, z0\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z1_z0, svfloat64x2_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.d - z25\\.d}, {z24\\.d - z25\\.d}, z0\\.d\n+** (\n+**\tmov\tz1\\.d, z24\\.d\n+**\tmov\tz2\\.d, z25\\.d\n+** |\n+**\tmov\tz2\\.d, z25\\.d\n+**\tmov\tz1\\.d, z24\\.d\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z24_z0, svfloat64x2_t, svint64_t, z1,\n+\t\tsvscale_single_f64_x2 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.d - z[0-9]+\\.d}), \\1, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z1_z0, svfloat64x2_t, svint64_t, z1,\n+\t\tsvscale_single_f64_x2 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z18_z18_z0:\n+**\tfscale\t{z18\\.d - z19\\.d}, {z18\\.d - z19\\.d}, z0\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z18_z18_z0, svfloat64x2_t, svint64_t, z18,\n+\t\tsvscale_single_f64_x2 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** svscale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.d - z[0-9]+\\.d}), \\1, z[0-9]+\\.d\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (svscale_single_awkward, svfloat64x2_t, svint64_t,\n+\t\t\tz0_res = svscale_single_f64_x2 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** svscale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.d - z1\\.d}, {z0\\.d - z1\\.d}, z15\\.d\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (svscale_single_z0_z0_z15, svfloat64x2_t, svint64_t,\n+\t\t    z0 = svscale_single_f64_x2 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** svscale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.d - z25\\.d}, {z24\\.d - z25\\.d}, \\1\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z16, svfloat64x2_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x2 (z24, z16),\n+\t\tsvscale (z24, z16))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c\nnew file mode 100644\nindex 00000000000..13eeb1a2e02\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c\n@@ -0,0 +1,229 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** svscale_z0_z0_z4:\n+**\tfscale\t{z0\\.d - z3\\.d}, {z0\\.d - z3\\.d}, {z4\\.d - z7\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z4, svfloat64x4_t, svint64x4_t, z0,\n+\t      svscale_f64_x4 (z0, z4),\n+\t      svscale (z0, z4))\n+\n+/*\n+** svscale_z4_z4_z0:\n+**\tfscale\t{z4\\.d - z7\\.d}, {z4\\.d - z7\\.d}, {z0\\.d - z3\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z0, svint64x4_t, svfloat64x4_t, z4,\n+\t      svscale_f64_x4 (z4, z0),\n+\t      svscale (z4, z0))\n+\n+/*\n+** svscale_z18_z18_z4:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z4\\.d - z7\\.d}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z18_z18_z4, svfloat64x4_t, svint64x4_t, z18,\n+\t      svscale_f64_x4 (z18, z4),\n+\t      svscale (z18, z4))\n+\n+/*\n+** svscale_z23_z23_z28:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, {z28\\.d - z31\\.d}\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z23_z23_z28, svint64x4_t, svfloat64x4_t, z23,\n+\t      svscale_f64_x4 (z23, z28),\n+\t      svscale (z23, z28))\n+\n+/*\n+** svscale_z28_z28_z4:\n+**\tfscale\t{z28\\.d - z31\\.d}, {z28\\.d - z31\\.d}, {z4\\.d - z7\\.d}\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z28_z28_z4, svfloat64x4_t, svint64x4_t, z28,\n+\t      svscale_f64_x4 (z28, z4),\n+\t      svscale (z28, z4))\n+\n+/*\n+** svscale_z4_z4_z18:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z4\\.d - z7\\.d}, {z4\\.d - z7\\.d}, [^\\n]+\n+** |\n+**\tfscale\t{z4\\.d - z7\\.d}, {z4\\.d - z7\\.d}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z4_z4_z18, svint64x4_t, svfloat64x4_t, z4,\n+\t      svscale_f64_x4 (z4, z18),\n+\t      svscale (z4, z18))\n+\n+/*\n+** svscale_z0_z0_z23:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z0\\.d - z3\\.d}, {z0\\.d - z3\\.d}, [^\\n]+\n+** |\n+**\tfscale\t{z0\\.d - z3\\.d}, {z0\\.d - z3\\.d}, [^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_DUAL_XN (svscale_z0_z0_z23, svfloat64x4_t, svint64x4_t, z0,\n+\t      svscale_f64_x4 (z0, z23),\n+\t      svscale (z0, z23))\n+\n+/*\n+** svscale_single_z24_z24_z0:\n+**\tfscale\t{z24\\.d - z27\\.d}, {z24\\.d - z27\\.d}, z0\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z0, svfloat64x4_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z24_z28_z0:\n+** (\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.d - z27\\.d}, {z24\\.d - z27\\.d}, z0\\.d\n+** |\n+**\tfscale\t{z28\\.d - z31\\.d}, {z28\\.d - z31\\.d}, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+** )\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z28_z0, svfloat64x4_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x4 (z28, z0),\n+\t\tsvscale (z28, z0))\n+\n+/*\n+** svscale_single_z24_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t{z24\\.d - z27\\.d}, {z24\\.d - z27\\.d}, z0\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z1_z0, svfloat64x4_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z1_z24_z0:\n+**\tfscale\t{z24\\.d - z27\\.d}, {z24\\.d - z27\\.d}, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z24_z0, svfloat64x4_t, svint64_t, z1,\n+\t\tsvscale_single_f64_x4 (z24, z0),\n+\t\tsvscale (z24, z0))\n+\n+/*\n+** svscale_single_z1_z1_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t({z[0-9]+\\.d - z[0-9]+\\.d}), \\1, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z1_z1_z0, svfloat64x4_t, svint64_t, z1,\n+\t\tsvscale_single_f64_x4 (z1, z0),\n+\t\tsvscale (z1, z0))\n+\n+/*\n+** svscale_single_z18_z18_z0:\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfscale\t[^\\n]+, z0\\.d\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z18_z18_z0, svfloat64x4_t, svint64_t, z18,\n+\t\tsvscale_single_f64_x4 (z18, z0),\n+\t\tsvscale (z18, z0))\n+\n+/*\n+** svscale_single_awkward:\n+**\t...\n+**\tfscale\t({z[0-9]+\\.d - z[0-9]+\\.d}), \\1, z[0-9]+\\.d\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_AWKWARD (svscale_single_awkward, svfloat64x4_t, svint64_t,\n+\t\t\tz0_res = svscale_single_f64_x4 (z1, z0),\n+\t\t\tz0_res = svscale (z1, z0))\n+\n+/*\n+** svscale_single_z0_z0_z15:\n+**\t...\n+**\tfscale\t{z0\\.d - z3\\.d}, {z0\\.d - z3\\.d}, z15\\.d\n+**\t...\n+**\tret\n+*/\n+TEST_XN_SINGLE_Z15 (svscale_single_z0_z0_z15, svfloat64x4_t, svint64_t,\n+\t\t    z0 = svscale_single_f64_x4 (z0, z15),\n+\t\t    z0 = svscale (z0, z15))\n+\n+/*\n+** svscale_single_z24_z24_z16:\n+**\tmov\t(z[0-7])\\.d, z16\\.d\n+**\tfscale\t{z24\\.d - z27\\.d}, {z24\\.d - z27\\.d}, \\1\\.d\n+**\tret\n+*/\n+TEST_XN_SINGLE (svscale_single_z24_z24_z16, svfloat64x4_t, svint64_t, z24,\n+\t\tsvscale_single_f64_x4 (z24, z16),\n+\t\tsvscale (z24, z16))\n",
    "prefixes": [
        "v4",
        "4/8"
    ]
}