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GET /api/1.0/patches/2175587/?format=api
{ "id": 2175587, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175587/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218142621.57402-6-claudio.bantaloukas@arm.com>", "date": "2025-12-18T14:26:17", "name": "[v4,5/8] aarch64: add basic support for sme-f8f16 and sme-f8f32", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0c8b3fccb3d409533189fda8922e21e8e3530542", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251218142621.57402-6-claudio.bantaloukas@arm.com/mbox/", "series": [ { "id": 485861, "url": "http://patchwork.ozlabs.org/api/1.0/series/485861/?format=api", "date": "2025-12-18T14:26:12", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485861/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175587/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=IRKBE3U0;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=IRKBE3U0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v4 5/8] aarch64: add basic support for sme-f8f16 and sme-f8f32", "Date": "Thu, 18 Dec 2025 14:26:17 +0000", "Message-ID": "<20251218142621.57402-6-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "References": "<20251218142621.57402-1-claudio.bantaloukas@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509E5:EE_|PAWPR08MB10923:EE_|DU2PEPF00028D08:EE_|DU0PR08MB8090:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7ba5bffd-afbb-4035-e7c2-08de3e419b6f", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|82310400026|1800799024|36860700013|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n B3jh1+otKhoP+9oDa19KMlCqrKzTCcWCaGxV0r07hk09a7dB7iFXoqHt/zVkhgCwFMidSCJATTaZxZVYYwU0kjxA0ORpTkloaZ2Km6HUoXjZFR/Ke5cM85OraMT/rytjZQeaYJ/pM0s5PYGtO9lwCifPCB3v77TQwGdD568tetdiVU+u5kCtvMXAtNsTdD8WST7QzcxjhlmE02utYtSb2b3F1TrEetf6TdsLiCvnznYLxfGxmjPgo3GGLVDQ7s/NPJKT1pyonLHewUICXiX4xErypHMCfSetjj6KrcN+ah07saKr/J0he0r+i9z+hhu9FNbTk2LsNCS9Mim/+fgj6rMV5HZ4TVz1V+q6hVUl4EBbDFuMKtFUfdftxzeK7ShgQiBCuiybBHBz7ZjjUUOnTtJBJ1R8s13O7ZNFQLd4+z3UlsKiUzHSSkYtoR0nPGwxqvkScY89TvaTdOKRuqAdLU2KkcK0hgdlECB6ELDSJQcrep8Y83NK8TW6jTqcMiz+gxrP9hbxvhOumKXPCXfCMxoG3UNMAWXCn23Xt7M6P53qCXDPY21Z1/XoBwJlVtVIrSjLTneoTg9Ba6jpHJIOq4iIBdhZvs+d+dP/O90OhZIeJ+jCE96T1Nly6Q4kmMa3ooVuTKGTeoYU3j61/Ooxzo/n46MI5sT6cHTPv8FjsGLm2rxbZ7z+zj6zeDMsZuP0TR+yHh/Ii25/9k4wrF8WKstS4htLxfVpfUNMZBUI+/C6M1YRp/LffcG3scOPKXnho8EMfo8de3kXmwNXqnz6Fi2SQ9Jb/ULSaIGyp0N8LqCBu4Vb7yT5xtsGVfAfGIeuYMugcpFQlWQRZ0Gjzq746DWS5nJj/Y/eVQmzvj7E0fvSOzZn9xA9G67r/yg/zd2vfK83FEt2pu4dGpy1CYsvAZs+o0UhLFRABzBm2CU5ptVL33Hb56LbtglgxBrlPz/2dfZFgpicTkEBJSccjmdOc6YOpRVIN5Sa057PKipAXBsn89zCmwfsxz8z+hVhUfS+lD2YhSiBNJMDuuasDDLdgCFSjbanZWZJqP6/K3TfbEEnhWfQoIxSBlmhDR30W9E+Pou2+apUOK0mwHDusvfUNGoobxlqcBX0ENq6tfiE5tK2UOZInkPOWo50jKnSd4sL5K7AkGhVtiDC4KVjntX/1sLUbUGZn9oLuKh+bfD/Br4VW4AouUTYdG6ounkQZiJ1J822rKZc0W4LYYlBrvTyULT3NiVO8aavWJCvDrfstYi2t/wgnMMRY1Ga1yUt6ZHuCxI2Ta/J17Wmx3uOV7W77tBLFrGlC+V8v0hzE9kATvpMZm2QZiul/obcwKirhOLewiSaGlrOLWtcqa1MNNwAbnr6SvwJcriLkVYoKholvAmAzTditvIycfclxgVGQ4RHx085eve/T6DnlkaS4U94U2Q9mTmsIW6a5SMtlkgHaeN1nENCBw30gfJHyt+GQPm8SisX7R4xhY+jNRF6EDTRL8C/IZ8HeW3ow3/kUYRnwSrEhqIrST4OVjHUgIrV5oaD", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(82310400026)(35042699022)(14060799003)(1800799024)(36860700013)(376014)(13003099007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 14:27:43.3702 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7ba5bffd-afbb-4035-e7c2-08de3e419b6f", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU2PEPF00028D08.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for the SME_F8F16 and SME_F8F32 features as architecture\noptions, along with related definitions. This support is required for subsequent\nintrinsics to work.\n\ngcc/\n\t* config/aarch64/aarch64.h:\n\t(TARGET_STREAMING_SME_F8F16, TARGET_STREAMING_SME_F8F32): Add defines.\n\t* config/aarch64/aarch64-c.cc:\n\t(__ARM_FEATURE_SME_F8F16, __ARM_FEATURE_SME_F8F32): Add defines.\n\t* config/aarch64/aarch64-option-extensions.def:\n\t(sme-f8f16, sme-f8f32): Add arch options in command line.\n\t* config/aarch64/aarch64-sve-builtins-functions.h:\n\t(sme_2mode_function_t): Pass unspec_for_mfp8 parameter through ctor.\n\t* config/aarch64/aarch64-sve-builtins-sme.def:\n\t(DEF_SME_FUNCTION_GS, DEF_SME_FUNCTION): Redefine based on\n\tDEF_SME_FUNCTION_GS_FPM.\n\t(DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Redefine based on\n\tDEF_SME_ZA_FUNCTION_GS_FPM.\n\t(AARCH64_FL_SME_F8F16, AARCH64_FL_SME_F8F32): Add new\n\tREQUIRED_EXTENSIONS sections.\n\t* config/aarch64/aarch64-sve-builtins.cc:\n\t(TYPES_za_h_mf8): Add new types.\n\t(TYPES_za_s_mf8): Likewise.\n\t(sme_function_groups): Define using DEF_SME_FUNCTION_GS_FPM instead of\n\tDEF_SME_FUNCTION_GS.\n\t* doc/invoke.texi: (sme-f8f16, sme-f8f32): Add documentation of option.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests checking that\n\tsme-f8f16 and sme-f8f32 prefefs are off by default, and checks for\n\tfeature dependencies.\n\t* lib/target-supports.exp: Add check_effective_target support for\n\tsme-f8f16 and sme-f8f32.\n---\n gcc/config/aarch64/aarch64-c.cc | 4 +++\n .../aarch64/aarch64-option-extensions.def | 4 +++\n .../aarch64/aarch64-sve-builtins-functions.h | 5 +--\n .../aarch64/aarch64-sve-builtins-sme.def | 18 ++++++++--\n gcc/config/aarch64/aarch64-sve-builtins.cc | 18 +++++++---\n gcc/config/aarch64/aarch64.h | 8 +++++\n gcc/doc/invoke.texi | 6 ++++\n .../gcc.target/aarch64/pragma_cpp_predefs_4.c | 34 +++++++++++++++++++\n gcc/testsuite/lib/target-supports.exp | 1 +\n 9 files changed, 89 insertions(+), 9 deletions(-)", "diff": "diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc\nindex 04cd7c354e5..dcfc14ae998 100644\n--- a/gcc/config/aarch64/aarch64-c.cc\n+++ b/gcc/config/aarch64/aarch64-c.cc\n@@ -294,6 +294,10 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)\n \n aarch64_def_or_undef (TARGET_SME, \"__ARM_FEATURE_SME\", pfile);\n aarch64_def_or_undef (TARGET_SME_I16I64, \"__ARM_FEATURE_SME_I16I64\", pfile);\n+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_F8F16),\n+\t\t\t\"__ARM_FEATURE_SME_F8F16\", pfile);\n+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_F8F32),\n+\t\t\t\"__ARM_FEATURE_SME_F8F32\", pfile);\n aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_B16B16),\n \t\t\t\"__ARM_FEATURE_SME_B16B16\", pfile);\n aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_F16F16),\ndiff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def\nindex c43802eb715..c8121baa3fd 100644\n--- a/gcc/config/aarch64/aarch64-option-extensions.def\n+++ b/gcc/config/aarch64/aarch64-option-extensions.def\n@@ -308,6 +308,10 @@ AARCH64_OPT_EXTENSION(\"lut\", LUT, (SIMD), (), (), \"lut\")\n \n AARCH64_OPT_EXTENSION (\"sme-lutv2\", SME_LUTv2, (SME2), (), (), \"smelutv2\")\n \n+AARCH64_OPT_EXTENSION (\"sme-f8f16\", SME_F8F16, (SME2, FP8), (), (), \"smef8f16\")\n+\n+AARCH64_OPT_EXTENSION (\"sme-f8f32\", SME_F8F32, (SME2, FP8), (), (), \"smef8f32\")\n+\n AARCH64_OPT_EXTENSION(\"cpa\", CPA, (), (), (), \"\")\n \n AARCH64_OPT_EXTENSION(\"fprcvt\", FPRCVT, (FP), (), (), \"fprcvt\")\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h\nindex c05946d4ec7..f5cf6bfb899 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h\n@@ -462,8 +462,9 @@ public:\n using parent = read_write_za<unspec_based_function_base>;\n \n CONSTEXPR sme_2mode_function_t (int unspec_for_sint, int unspec_for_uint,\n-\t\t\t\t int unspec_for_fp)\n- : parent (unspec_for_sint, unspec_for_uint, unspec_for_fp, -1, 1)\n+\t\t\t\t int unspec_for_fp, int unspec_for_mfp8 = -1)\n+ : parent (unspec_for_sint, unspec_for_uint, unspec_for_fp, unspec_for_mfp8,\n+\t 1)\n {}\n \n rtx\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\nindex 978a74f438d..c86d5fa730b 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def\n@@ -17,19 +17,25 @@\n along with GCC; see the file COPYING3. If not see\n <http://www.gnu.org/licenses/>. */\n \n+\n+#ifndef DEF_SME_FUNCTION_GS\n+#define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \\\n+ DEF_SME_FUNCTION_GS_FPM (NAME, SHAPE, TYPES, GROUPS, PREDS, unused)\n+#endif\n+\n #ifndef DEF_SME_FUNCTION\n #define DEF_SME_FUNCTION(NAME, SHAPE, TYPES, PREDS) \\\n- DEF_SME_FUNCTION_GS (NAME, SHAPE, TYPES, none, PREDS)\n+ DEF_SME_FUNCTION_GS_FPM (NAME, SHAPE, TYPES, none, PREDS, unused)\n #endif\n \n #ifndef DEF_SME_ZA_FUNCTION_GS\n #define DEF_SME_ZA_FUNCTION_GS(NAME, SHAPE, TYPES, GROUP, PREDS) \\\n- DEF_SME_FUNCTION_GS (NAME, SHAPE, TYPES, GROUP, PREDS)\n+ DEF_SME_ZA_FUNCTION_GS_FPM (NAME, SHAPE, TYPES, GROUP, PREDS, unused)\n #endif\n \n #ifndef DEF_SME_ZA_FUNCTION\n #define DEF_SME_ZA_FUNCTION(NAME, SHAPE, TYPES, PREDS) \\\n- DEF_SME_ZA_FUNCTION_GS (NAME, SHAPE, TYPES, none, PREDS)\n+ DEF_SME_ZA_FUNCTION_GS_FPM (NAME, SHAPE, TYPES, none, PREDS, unused)\n #endif\n \n #define REQUIRED_EXTENSIONS streaming_compatible (0)\n@@ -259,6 +265,12 @@ DEF_SME_FUNCTION_GS (svwrite_lane_zt, write_lane_zt, all_data, none, none)\n DEF_SME_FUNCTION_GS (svluti4_zt, luti4_zt, b_integer, x4, none)\n #undef REQUIRED_EXTENSIONS\n \n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F16)\n+#undef REQUIRED_EXTENSIONS\n+\n+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F8F32)\n+#undef REQUIRED_EXTENSIONS\n+\n #undef DEF_SME_ZA_FUNCTION\n #undef DEF_SME_ZA_FUNCTION_GS\n #undef DEF_SME_FUNCTION\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc\nindex 03481ee4a77..505a2445d1f 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc\n@@ -664,6 +664,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {\n TYPES_za_bhsd_data (S, D), \\\n TYPES_reinterpret1 (D, za128)\n \n+/* _za16_mf8. */\n+#define TYPES_za_h_mf8(S, D) \\\n+ D (za16, mf8)\n+\n /* _za16_bf16. */\n #define TYPES_za_h_bfloat(S, D) \\\n D (za16, bf16)\n@@ -700,6 +704,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {\n #define TYPES_za_s_integer(S, D) \\\n D (za32, s32), D (za32, u32)\n \n+/* _za32_mf8. */\n+#define TYPES_za_s_mf8(S, D) \\\n+ D (za32, mf8)\n+\n /* _za32_f32. */\n #define TYPES_za_s_float(S, D) \\\n D (za32, f32)\n@@ -849,6 +857,7 @@ DEF_SVE_TYPES_ARRAY (all_za);\n DEF_SVE_TYPES_ARRAY (d_za);\n DEF_SVE_TYPES_ARRAY (za_bhsd_data);\n DEF_SVE_TYPES_ARRAY (za_all_data);\n+DEF_SVE_TYPES_ARRAY (za_h_mf8);\n DEF_SVE_TYPES_ARRAY (za_h_bfloat);\n DEF_SVE_TYPES_ARRAY (za_h_float);\n DEF_SVE_TYPES_ARRAY (za_s_b_signed);\n@@ -858,6 +867,7 @@ DEF_SVE_TYPES_ARRAY (za_s_h_integer);\n DEF_SVE_TYPES_ARRAY (za_s_h_data);\n DEF_SVE_TYPES_ARRAY (za_s_unsigned);\n DEF_SVE_TYPES_ARRAY (za_s_integer);\n+DEF_SVE_TYPES_ARRAY (za_s_mf8);\n DEF_SVE_TYPES_ARRAY (za_s_float);\n DEF_SVE_TYPES_ARRAY (za_s_data);\n DEF_SVE_TYPES_ARRAY (za_d_h_integer);\n@@ -987,15 +997,15 @@ static CONSTEXPR const function_group_info neon_sve_function_groups[] = {\n \n /* A list of all arm_sme.h functions. */\n static CONSTEXPR const function_group_info sme_function_groups[] = {\n-#define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \\\n+#define DEF_SME_FUNCTION_GS_FPM(NAME, SHAPE, TYPES, GROUPS, PREDS, FPM_MODE) \\\n { #NAME, &functions::NAME, &shapes::SHAPE, types_##TYPES, groups_##GROUPS, \\\n preds_##PREDS, aarch64_required_extensions::REQUIRED_EXTENSIONS, \\\n- FPM_unused },\n-#define DEF_SME_ZA_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \\\n+ FPM_##FPM_MODE },\n+#define DEF_SME_ZA_FUNCTION_GS_FPM(NAME, SHAPE, TYPES, GROUPS, PREDS, FPM_MODE) \\\n { #NAME, &functions::NAME##_za, &shapes::SHAPE, types_##TYPES, \\\n groups_##GROUPS, preds_##PREDS, \\\n aarch64_required_extensions::REQUIRED_EXTENSIONS \\\n- .and_also (AARCH64_FL_ZA_ON), FPM_unused },\n+ .and_also (AARCH64_FL_ZA_ON), FPM_##FPM_MODE },\n #include \"aarch64-sve-builtins-sme.def\"\n };\n \ndiff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h\nindex e3eb807fb53..deab503d746 100644\n--- a/gcc/config/aarch64/aarch64.h\n+++ b/gcc/config/aarch64/aarch64.h\n@@ -321,6 +321,14 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED\n /* The FEAT_SME_I16I64 extension to SME, enabled through +sme-i16i64. */\n #define TARGET_SME_I16I64 AARCH64_HAVE_ISA (SME_I16I64)\n \n+/* The FEAT_SME_F8F16 extension to SME, enabled through +sme-f8f16. */\n+#define TARGET_STREAMING_SME_F8F16 \\\n+ (AARCH64_HAVE_ISA (SME_F8F16) && TARGET_STREAMING)\n+\n+/* The FEAT_SME_F8F32 extension to SME, enabled through +sme-f8f32. */\n+#define TARGET_STREAMING_SME_F8F32 \\\n+ (AARCH64_HAVE_ISA (SME_F8F32) && TARGET_STREAMING)\n+\n /* The FEAT_SME_B16B16 extension to SME, enabled through +sme-b16b16. */\n #define TARGET_STREAMING_SME_B16B16 \\\n (AARCH64_HAVE_ISA (SME_B16B16) && TARGET_STREAMING)\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex c54eb758b17..0252740175d 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -23079,6 +23079,12 @@ Enable the FEAT_SME_F64F64 extension to SME. This also enables SME\n instructions.\n @item sme2\n Enable the Scalable Matrix Extension 2. This also enables SME instructions.\n+@item sme-f8f16\n+Enable the FEAT_SME_F8F16 extension to SME. This also enables SME2 and FP8\n+instructions.\n+@item sme-f8f32\n+Enable the FEAT_SME_F8F32 extension to SME. This also enables SME2 and FP8\n+instructions.\n @item sme-b16b16\n Enable the FEAT_SME_B16B16 extension to SME. This also enables SME2\n and SVE_B16B16 instructions.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c\nindex 3799fb46df1..284c2a23252 100644\n--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c\n@@ -70,6 +70,12 @@\n #ifdef __ARM_FEATURE_SME_I16I64\n #error Foo\n #endif\n+#ifdef __ARM_FEATURE_SME_F8F16\n+#error Foo\n+#endif\n+#ifdef __ARM_FEATURE_SME_F8F32\n+#error Foo\n+#endif\n #ifdef __ARM_FEATURE_SME_B16B16\n #error Foo\n #endif\n@@ -105,6 +111,34 @@\n #error Foo\n #endif\n \n+#pragma GCC target \"+nothing+sve2+sme-f8f16\"\n+#ifndef __ARM_FEATURE_SME_F8F16\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_SME\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_SME2\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_FP8\n+#error Foo\n+#endif\n+\n+#pragma GCC target \"+nothing+sve2+sme-f8f32\"\n+#ifndef __ARM_FEATURE_SME_F8F32\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_SME\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_SME2\n+#error Foo\n+#endif\n+#ifndef __ARM_FEATURE_FP8\n+#error Foo\n+#endif\n+\n #pragma GCC target \"+nothing+sve2+sme-f16f16\"\n #ifndef __ARM_FEATURE_SME_F16F16\n #error Foo\ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 27759094d85..2946db06058 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -12652,6 +12652,7 @@ set exts {\n # We don't support SME without SVE2, so we'll use armv9 as the base\n # archiecture for SME and the features that require it.\n set exts_sve2 {\n+ \"sme-f8f16\" \"sme-f8f32\"\n \"sme-b16b16\" \"sme-f16f16\" \"sme-i16i64\" \"sme\" \"sme2\" \"sme2p1\"\n \"ssve-fp8dot2\" \"ssve-fp8dot4\" \"ssve-fp8fma\"\n }\n", "prefixes": [ "v4", "5/8" ] }