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GET /api/1.0/patches/2175559/?format=api
{ "id": 2175559, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175559/?format=api", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.0/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218123011.2577148-2-mengqinggang@loongson.cn>", "date": "2025-12-18T12:30:07", "name": "[v2,1/5] LoongArch: Add support for LA32 in sysdeps/loongarch", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c264f118305c527ad9bcc7e9898cf2c47d663397", "submitter": { "id": 87178, "url": "http://patchwork.ozlabs.org/api/1.0/people/87178/?format=api", "name": "mengqinggang", "email": "mengqinggang@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/20251218123011.2577148-2-mengqinggang@loongson.cn/mbox/", "series": [ { "id": 485843, "url": "http://patchwork.ozlabs.org/api/1.0/series/485843/?format=api", "date": "2025-12-18T12:30:06", "name": "Add support for LoongArch32", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485843/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175559/checks/", "tags": {}, "headers": { "Return-Path": "<libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "libc-alpha@sourceware.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "libc-alpha@sourceware.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n dmarc=none (p=none dis=none) header.from=loongson.cn", "sourceware.org; spf=pass smtp.mailfrom=loongson.cn", "server2.sourceware.org;\n arc=none smtp.remote-ip=114.242.206.163" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX98H0b6Pz1y2F\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 23:34:07 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 106734BA2E1E\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 12:34:05 +0000 (GMT)", "from mail.loongson.cn (mail.loongson.cn [114.242.206.163])\n by sourceware.org (Postfix) with ESMTP id 0526B4BA2E2B\n for <libc-alpha@sourceware.org>; Thu, 18 Dec 2025 12:32:16 +0000 (GMT)", "from loongson.cn (unknown [10.2.6.7])\n by gateway (Coremail) with SMTP id _____8BxcfAt9ENpsHYAAA--.2113S3;\n Thu, 18 Dec 2025 20:31:41 +0800 (CST)", "from amd9754.. (unknown [10.2.6.7])\n by front1 (Coremail) with SMTP id qMiowJCxHOEq9ENpLFQBAA--.5537S2;\n Thu, 18 Dec 2025 20:31:38 +0800 (CST)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 106734BA2E1E", "OpenDKIM Filter v2.11.0 sourceware.org 0526B4BA2E2B" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 0526B4BA2E2B", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 0526B4BA2E2B", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1766061137; cv=none;\n b=e/NJdLXpzyeGWJvV9+xzi+ocVkYMbQpiaytTlDAlj4mc1y26t9ZAd+C3i8+vm92VviszyiZ00gdJGfKhmvXIM8unU8RN1yiWpq1nY7fmtX+l0pT1iO5yUCH5o8vKn+DQlLvq2TmX9CJ7I2tp9fEMA7mvZoZuYgwfHbsKHfk+OZo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766061137; c=relaxed/simple;\n bh=dBm3XlH0BOkoWB7/hR492EAoGlKKyMowI/vL3qZZlBc=;\n h=From:To:Subject:Date:Message-Id:MIME-Version;\n b=hWbXbm+E/s7lFo6K+MEL1jYE9pPokeDnun1i3cKUufFBBIZpeJVfYpblmefY2swrpK8NFJYyLMtOkyh6DIJNg18VZrsvl1S5EPNXlH4kcrBe5KCa0k5n6H3kFbMM9zsZLBzJkyVx9DruwIaWshzKFrqgyCHnkeutIPLvf4LTOWs=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "mengqinggang <mengqinggang@loongson.cn>", "To": "libc-alpha@sourceware.org", "Cc": "adhemerval.zanella@linaro.org, xuchenghua@loongson.cn,\n caiyinyu@loongson.cn, chenglulu@loongson.cn, cailulu@loongson.cn,\n xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com,\n luweining@loongson.cn, hejinyang@loongson.cn, mengqinggang@loongson.cn", "Subject": "[PATCH v2 1/5] LoongArch: Add support for LA32 in sysdeps/loongarch", "Date": "Thu, 18 Dec 2025 20:30:07 +0800", "Message-Id": "<20251218123011.2577148-2-mengqinggang@loongson.cn>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20251218123011.2577148-1-mengqinggang@loongson.cn>", "References": "<20251218123011.2577148-1-mengqinggang@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJCxHOEq9ENpLFQBAA--.5537S2", "X-CM-SenderInfo": "5phqw15lqjwttqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "X-BeenThere": "libc-alpha@sourceware.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Libc-alpha mailing list <libc-alpha.sourceware.org>", "List-Unsubscribe": "<https://sourceware.org/mailman/options/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe>", "List-Archive": "<https://sourceware.org/pipermail/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-request@sourceware.org?subject=help>", "List-Subscribe": "<https://sourceware.org/mailman/listinfo/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=subscribe>", "Errors-To": "libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org" }, "content": "---\n scripts/build-many-glibcs.py | 7 ++\n sysdeps/loongarch/configure | 36 ++++++----\n sysdeps/loongarch/configure.ac | 30 ++++++---\n sysdeps/loongarch/dl-machine.h | 16 +++--\n sysdeps/loongarch/dl-tlsdesc-dynamic.h | 37 +++++-----\n sysdeps/loongarch/dl-tlsdesc.S | 6 +-\n sysdeps/loongarch/dl-trampoline.h | 4 +-\n sysdeps/loongarch/hp-timing.h | 9 +++\n sysdeps/loongarch/preconfigure | 3 +-\n sysdeps/loongarch/preconfigure.ac | 3 +-\n sysdeps/loongarch/sfp-machine.h | 33 +++++++++\n sysdeps/loongarch/start.S | 32 ++++++---\n sysdeps/loongarch/sys/asm.h | 93 ++++++++++++++++++++++++--\n sysdeps/loongarch/tst-gnu2-tls2.h | 50 ++++++--------\n 14 files changed, 260 insertions(+), 99 deletions(-)", "diff": "diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py\nindex 940b66a09a..5cc62ff204 100755\n--- a/scripts/build-many-glibcs.py\n+++ b/scripts/build-many-glibcs.py\n@@ -262,6 +262,12 @@ class Context(object):\n os_name='linux-gnu')\n self.add_config(arch='i686',\n os_name='gnu')\n+ self.add_config(arch='loongarch32',\n+ os_name='linux-gnu',\n+ gcc_cfg=['--with-arch=la32v1.0', '--disable-multilib'])\n+ self.add_config(arch='loongarch32',\n+ os_name='linux-gnusf',\n+ gcc_cfg=['--with-arch=la32rv1.0', '--disable-multilib'])\n self.add_config(arch='loongarch64',\n os_name='linux-gnuf64',\n gcc_cfg=['--disable-multilib'])\n@@ -1369,6 +1375,7 @@ def install_linux_headers(policy, cmdlist):\n 'i586': 'x86',\n 'i686': 'x86',\n 'i786': 'x86',\n+ 'loongarch32': 'loongarch',\n 'loongarch64': 'loongarch',\n 'm68k': 'm68k',\n 'microblaze': 'microblaze',\ndiff --git a/sysdeps/loongarch/configure b/sysdeps/loongarch/configure\nindex d3d9fec910..d16ce16d54 100644\n--- a/sysdeps/loongarch/configure\n+++ b/sysdeps/loongarch/configure\n@@ -113,7 +113,17 @@ if test $libc_cv_loongarch_vec_asm = no; then\n as_fn_error $? \"binutils version is too old, use 2.41 or newer version\" \"$LINENO\" 5\n fi\n \n+#AC_COMPILE_IFELSE([AC_LANG_SOURCE([[\n+#void foo (void)\n+#{\n+# asm volatile (\"vldi \\$vr0, 1\" ::: \"\\$vr0\");\n+# asm volatile (\"xvldi \\$xr0, 1\" ::: \"\\$xr0\");\n+#}\n+#]])],\n+# [libc_cv_loongarch_vec_com=yes],\n+# [libc_cv_loongarch_vec_com=no])])\n \n+# Check if compiler support vector instructions.\n { printf \"%s\\n\" \"$as_me:${as_lineno-$LINENO}: checking for vector support in compiler\" >&5\n printf %s \"checking for vector support in compiler... \" >&6; }\n if test ${libc_cv_loongarch_vec_com+y}\n@@ -121,30 +131,28 @@ then :\n printf %s \"(cached) \" >&6\n else case e in #(\n e)\n-cat confdefs.h - <<_ACEOF >conftest.$ac_ext\n-/* end confdefs.h. */\n-\n+cat > conftest.c <<\\EOF\n void foo (void)\n {\n asm volatile (\"vldi \\$vr0, 1\" ::: \"\\$vr0\");\n- asm volatile (\"xvldi \\$xr0, 1\" ::: \"\\$xr0\");\n }\n-\n-_ACEOF\n-if ac_fn_c_try_compile \"$LINENO\"\n-then :\n+EOF\n+if { ac_try='${CC-cc} -c -mlsx $CFLAGS conftest.s -o conftest 1>&5'\n+ { { eval echo \"\\\"\\$as_me\\\":${as_lineno-$LINENO}: \\\"$ac_try\\\"\"; } >&5\n+ (eval $ac_try) 2>&5\n+ ac_status=$?\n+ printf \"%s\\n\" \"$as_me:${as_lineno-$LINENO}: \\$? = $ac_status\" >&5\n+ test $ac_status = 0; }; }; then\n libc_cv_loongarch_vec_com=yes\n-else case e in #(\n- e) libc_cv_loongarch_vec_com=no ;;\n-esac\n+else\n+ libc_cv_loongarch_vec_com=no\n fi\n-rm -f core conftest.err conftest.$ac_objext conftest.beam conftest.$ac_ext ;;\n+rm -f conftest* ;;\n esac\n fi\n { printf \"%s\\n\" \"$as_me:${as_lineno-$LINENO}: result: $libc_cv_loongarch_vec_com\" >&5\n printf \"%s\\n\" \"$libc_cv_loongarch_vec_com\" >&6; }\n-if test \"$libc_cv_loongarch_vec_com\" = yes ;\n-then\n+if test \"$libc_cv_loongarch_vec_com\" = yes ; then\n printf \"%s\\n\" \"#define HAVE_LOONGARCH_VEC_COM 1\" >>confdefs.h\n \n fi\ndiff --git a/sysdeps/loongarch/configure.ac b/sysdeps/loongarch/configure.ac\nindex c56a203574..8130a5e9ad 100644\n--- a/sysdeps/loongarch/configure.ac\n+++ b/sysdeps/loongarch/configure.ac\n@@ -66,19 +66,31 @@ if test $libc_cv_loongarch_vec_asm = no; then\n AC_MSG_ERROR([binutils version is too old, use 2.41 or newer version])\n fi\n \n-AC_CACHE_CHECK([for vector support in compiler],\n-\t\tlibc_cv_loongarch_vec_com, [\n-AC_COMPILE_IFELSE([AC_LANG_SOURCE([[\n+#AC_COMPILE_IFELSE([AC_LANG_SOURCE([[\n+#void foo (void)\n+#{\n+# asm volatile (\"vldi \\$vr0, 1\" ::: \"\\$vr0\");\n+# asm volatile (\"xvldi \\$xr0, 1\" ::: \"\\$xr0\");\n+#}\n+#]])],\n+# [libc_cv_loongarch_vec_com=yes],\n+# [libc_cv_loongarch_vec_com=no])])\n+\n+# Check if compiler support vector instructions.\n+AC_CACHE_CHECK([for vector support in compiler], libc_cv_loongarch_vec_com, [\n+cat > conftest.c <<\\EOF\n void foo (void)\n {\n asm volatile (\"vldi \\$vr0, 1\" ::: \"\\$vr0\");\n- asm volatile (\"xvldi \\$xr0, 1\" ::: \"\\$xr0\");\n }\n-]])],\n- [libc_cv_loongarch_vec_com=yes],\n- [libc_cv_loongarch_vec_com=no])])\n-if test \"$libc_cv_loongarch_vec_com\" = yes ;\n-then\n+EOF\n+if AC_TRY_COMMAND(${CC-cc} -c -mlsx $CFLAGS conftest.s -o conftest 1>&AS_MESSAGE_LOG_FD); then\n+ libc_cv_loongarch_vec_com=yes\n+else\n+ libc_cv_loongarch_vec_com=no\n+fi\n+rm -f conftest*])\n+if test \"$libc_cv_loongarch_vec_com\" = yes ; then\n AC_DEFINE(HAVE_LOONGARCH_VEC_COM)\n fi\n LIBC_CONFIG_VAR([loongarch-vec-com], [$libc_cv_loongarch_vec_com])\ndiff --git a/sysdeps/loongarch/dl-machine.h b/sysdeps/loongarch/dl-machine.h\nindex b01d9339a4..9632eb02c2 100644\n--- a/sysdeps/loongarch/dl-machine.h\n+++ b/sysdeps/loongarch/dl-machine.h\n@@ -98,6 +98,8 @@ static inline ElfW (Addr) elf_machine_dynamic (void)\n return (ElfW(Addr)) _DYNAMIC - elf_machine_load_address ();\n }\n \n+#define STRINGXP(X) __STRING (X)\n+\n /* Initial entry point code for the dynamic linker.\n The C function `_dl_start' is the real entry point;\n its return value is the user program's entry point. */\n@@ -112,19 +114,19 @@ static inline ElfW (Addr) elf_machine_dynamic (void)\n \t# Stash user entry point in s0. \\n\\\n \tor\t$s0, $a0, $zero \\n\\\n \t# Load the original argument count. \\n\\\n-\tld.d\t$a1, $sp, 0 \\n\\\n+\t\" STRINGXP (REG_L) \"\t$a1, $sp, 0 \\n\\\n \t# Call _dl_init (struct link_map *main_map, int argc, \\\n \t\t\t char **argv, char **env) \\n\\\n \tla\t$a0, _rtld_local \\n\\\n-\tld.d\t$a0, $a0, 0 \\n\\\n-\taddi.d\t$a2, $sp, 8 \\n\\\n-\tslli.d\t$a3, $a1, 3 \\n\\\n-\tadd.d\t$a3, $a3, $a2 \\n\\\n-\taddi.d\t$a3, $a3, 8 \\n\\\n+\t\" STRINGXP (REG_L) \"\t$a0, $a0, 0 \\n\\\n+\t\" STRINGXP (ADDI) \"\t$a2, $sp, \" STRINGXP (SZREG) \" \\n\\\n+\t\" STRINGXP (SLLI) \"\t$a3, $a1, \" STRINGXP (PTRLOG) \" \\n\\\n+\t\" STRINGXP (ADD) \"\t$a3, $a3, $a2 \\n\\\n+\t\" STRINGXP (ADDI) \"\t$a3, $a3, \" STRINGXP (SZREG) \" \\n\\\n \t# Stash the stack pointer in s1.\\n\\\n \tor\t$s1, $sp, $zero\t\\n\\\n \t# Adjust $sp for 16-aligned \\n\\\n-\tbstrins.d\t$sp, $zero, 3, 0 \\n\\\n+\t\" REG_ALIGN_C ($sp, 4) \" \\n\\\n \t# Call the function to run the initializers. \\n\\\n \tbl\t_dl_init \\n\\\n \t# Restore the stack pointer for _start.\\n\\\ndiff --git a/sysdeps/loongarch/dl-tlsdesc-dynamic.h b/sysdeps/loongarch/dl-tlsdesc-dynamic.h\nindex 5f78eb205c..417b837e50 100644\n--- a/sysdeps/loongarch/dl-tlsdesc-dynamic.h\n+++ b/sysdeps/loongarch/dl-tlsdesc-dynamic.h\n@@ -53,14 +53,14 @@\n _dl_tlsdesc_dynamic:\n \t/* Save just enough registers to support fast path, if we fall\n \t into slow path we will save additional registers. */\n-\tADDI\tsp, sp, -32\n-\tcfi_adjust_cfa_offset (32)\n+\tADDI\tsp, sp, -(4 * SZREG)\n+\tcfi_adjust_cfa_offset (4 * SZREG)\n \tREG_S\tt0, sp, 0\n-\tREG_S\tt1, sp, 8\n-\tREG_S\tt2, sp, 16\n+\tREG_S\tt1, sp, SZREG\n+\tREG_S\tt2, sp, 2 * SZREG\n \tcfi_rel_offset (12, 0)\n-\tcfi_rel_offset (13, 8)\n-\tcfi_rel_offset (14, 16)\n+\tcfi_rel_offset (13, SZREG)\n+\tcfi_rel_offset (14, 2 * SZREG)\n \n /* Runtime Storage Layout of Thread-Local Storage\n TP point to the start of TLS block.\n@@ -81,11 +81,11 @@ Hign address\tdynamic_block1 <----- dtv5 */\n \tbltu\tt2, t1, .Lslow\n \n \tREG_L\tt1, a0, TLSDESC_MODID /* t1 = td->tlsinfo.ti_module */\n-\t/* t1 = t1 * sizeof(dtv_t) = t1 * (2 * sizeof(void*)) */\n-\tslli.d\tt1, t1, 4\n-\tadd.d\tt1, t1, t0 /* t1 = dtv[td->tlsinfo.ti_module] */\n+\t/* t1 = t1 * sizeof(dtv_pointer) = t1 * (2 * sizeof(void*)) */\n+\tSLLI\tt1, t1, (PTRLOG + 1)\n+\tADD\tt1, t1, t0 /* t1 = dtv[td->tlsinfo.ti_module] */\n \tREG_L\tt1, t1, 0 /* t1 = dtv[td->tlsinfo.ti_module].pointer.val */\n-\tli.d\tt2, TLS_DTV_UNALLOCATED\n+\tLI\tt2, TLS_DTV_UNALLOCATED\n \t/* If dtv[td->tlsinfo.ti_module].pointer.val is TLS_DTV_UNALLOCATED,\n \t goto slow path. */\n \tbeq\tt1, t2, .Lslow\n@@ -93,14 +93,14 @@ Hign address\tdynamic_block1 <----- dtv5 */\n \tcfi_remember_state\n \tREG_L\tt2, a0, TLSDESC_MODOFF\t/* t2 = td->tlsinfo.ti_offset */\n \t/* dtv[td->tlsinfo.ti_module].pointer.val + td->tlsinfo.ti_offset */\n-\tadd.d\ta0, t1, t2\n+\tADD\ta0, t1, t2\n .Lret:\n-\tsub.d\ta0, a0, tp\n+\tSUB\ta0, a0, tp\n \tREG_L\tt0, sp, 0\n-\tREG_L\tt1, sp, 8\n-\tREG_L\tt2, sp, 16\n-\tADDI\tsp, sp, 32\n-\tcfi_adjust_cfa_offset (-32)\n+\tREG_L\tt1, sp, SZREG\n+\tREG_L\tt2, sp, 2 * SZREG\n+\tADDI\tsp, sp, 4 * SZREG\n+\tcfi_adjust_cfa_offset (-(4 * SZREG))\n \tRET\n \n .Lslow:\n@@ -147,7 +147,8 @@ Hign address\tdynamic_block1 <----- dtv5 */\n \t Only one physical fcsr0 register, fcsr1-fcsr3 are aliases\n \t of some fields in fcsr0. */\n \tmovfcsr2gr t0, fcsr0\n-\tst.w\tt0, sp, FRAME_SIZE + 24 /* Use the spare slot above t2. */\n+\t/* Use the spare slot above t2. */\n+\tst.w\tt0, sp, FRAME_SIZE + 3 * SZREG\n \n #ifdef USE_LASX\n #define V_REG_S xvst\n@@ -194,7 +195,7 @@ Hign address\tdynamic_block1 <----- dtv5 */\n \tcfi_adjust_cfa_offset (-V_SPACE)\n \n \t/* Restore fcsr0 register. */\n-\tld.w\tt0, sp, FRAME_SIZE + 24\n+\tld.w\tt0, sp, FRAME_SIZE + 3 * SZREG\n \tmovgr2fcsr fcsr0, t0\n \n #endif /* #ifndef __loongarch_soft_float */\ndiff --git a/sysdeps/loongarch/dl-tlsdesc.S b/sysdeps/loongarch/dl-tlsdesc.S\nindex 906c69b205..e79e968cfb 100644\n--- a/sysdeps/loongarch/dl-tlsdesc.S\n+++ b/sysdeps/loongarch/dl-tlsdesc.S\n@@ -34,7 +34,7 @@\n \tcfi_startproc\n \t.align 2\n _dl_tlsdesc_return:\n-\tREG_L a0, a0, 8\n+\tREG_L a0, a0, SZREG\n \tRET\n \tcfi_endproc\n \t.size\t_dl_tlsdesc_return, .-_dl_tlsdesc_return\n@@ -53,8 +53,8 @@ _dl_tlsdesc_return:\n \tcfi_startproc\n \t.align 2\n _dl_tlsdesc_undefweak:\n-\tREG_L\ta0, a0, 8\n-\tsub.d\ta0, a0, tp\n+\tREG_L\ta0, a0, SZREG\n+\tSUB\ta0, a0, tp\n \tRET\n \tcfi_endproc\n \t.size\t_dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak\ndiff --git a/sysdeps/loongarch/dl-trampoline.h b/sysdeps/loongarch/dl-trampoline.h\nindex c267240370..f13fd3b304 100644\n--- a/sysdeps/loongarch/dl-trampoline.h\n+++ b/sysdeps/loongarch/dl-trampoline.h\n@@ -160,7 +160,7 @@ ENTRY (_dl_runtime_profile)\n \t/* Save arguments to stack. */\n \tADDI\tsp, sp, -SF_SIZE\n \tREG_S\tra, sp, 0\n-\tREG_S\tfp, sp, 8\n+\tREG_S\tfp, sp, SZREG\n \n \tor\tfp, sp, zero\n \n@@ -270,7 +270,7 @@ ENTRY (_dl_runtime_profile)\n 1:\n \t/* The new frame size is in t3. */\n \tSUB\tsp, fp, t3\n-\tBSTRINS sp, zero, 3, 0\n+\tREG_ALIGN_ASM (sp, 4)\n \n \tREG_S\ta0, fp, OFFSET_T1\n \ndiff --git a/sysdeps/loongarch/hp-timing.h b/sysdeps/loongarch/hp-timing.h\nindex 71c96131ee..8d9b7f89d4 100644\n--- a/sysdeps/loongarch/hp-timing.h\n+++ b/sysdeps/loongarch/hp-timing.h\n@@ -30,12 +30,21 @@\n typedef unsigned long long int hp_timing_t;\n \n /* Read the stable counter. */\n+#ifdef __loongarch64\n #define HP_TIMING_NOW(Var) \\\n ({ \\\n unsigned long long int _count; \\\n asm volatile (\"rdtime.d\\t%0,$r0\" : \"=r\" (_count)); \\\n (Var) = _count; \\\n })\n+#else\n+#define HP_TIMING_NOW(Var) \\\n+ ({ unsigned int _countl,_counth ; \\\n+ asm volatile (\"rdtimel.w\\t%0,$r0\\n\\trdtimeh.w\\t%1,$r0\" \\\n+\t\t : \"=r\" (_countl), \"=r\"(_counth)); \\\n+ (Var) = ((_counth & -1ULL << 32 ) | _countl); \\\n+ })\n+#endif\n \n #include <hp-timing-common.h>\n \ndiff --git a/sysdeps/loongarch/preconfigure b/sysdeps/loongarch/preconfigure\nindex 6726ab8302..4248091f53 100644\n--- a/sysdeps/loongarch/preconfigure\n+++ b/sysdeps/loongarch/preconfigure\n@@ -26,7 +26,8 @@ loongarch*)\n \n case \"$abi\" in\n ilp32)\n-\tas_fn_error 1 \"loongarch does not yet support ilp32 ABI!!\" \"$LINENO\" 5\n+\tgrlen=32\n+\tmachine=loongarch/ilp32\n \t;;\n lp64)\n \tgrlen=64\ndiff --git a/sysdeps/loongarch/preconfigure.ac b/sysdeps/loongarch/preconfigure.ac\nindex 56402261df..2602aa17bf 100644\n--- a/sysdeps/loongarch/preconfigure.ac\n+++ b/sysdeps/loongarch/preconfigure.ac\n@@ -26,7 +26,8 @@ loongarch*)\n \n case \"$abi\" in\n ilp32)\n-\tAC_MSG_ERROR([loongarch does not yet support ilp32 ABI!!], 1)\n+\tgrlen=32\n+\tmachine=loongarch/ilp32\n \t;;\n lp64)\n \tgrlen=64\ndiff --git a/sysdeps/loongarch/sfp-machine.h b/sysdeps/loongarch/sfp-machine.h\nindex 113d96651b..28ca6125bb 100644\n--- a/sysdeps/loongarch/sfp-machine.h\n+++ b/sysdeps/loongarch/sfp-machine.h\n@@ -20,6 +20,37 @@\n #include <fenv.h>\n #include <fpu_control.h>\n \n+#if __loongarch_grlen == 32\n+\n+# define _FP_W_TYPE_SIZE\t32\n+# define _FP_W_TYPE\t\tunsigned long\n+# define _FP_WS_TYPE\t\tsigned long\n+# define _FP_I_TYPE\t\tlong\n+\n+# define _FP_MUL_MEAT_S(R, X, Y)\t\t\t\t\\\n+ _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm)\n+# define _FP_MUL_MEAT_D(R, X, Y)\t\t\t\t\\\n+ _FP_MUL_MEAT_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm)\n+# define _FP_MUL_MEAT_Q(R, X, Y)\t\t\t\t\\\n+ _FP_MUL_MEAT_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm)\n+\n+# define _FP_MUL_MEAT_DW_S(R, X, Y)\t\t\t\t\t\\\n+ _FP_MUL_MEAT_DW_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm)\n+# define _FP_MUL_MEAT_DW_D(R, X, Y)\t\t\t\t\t\\\n+ _FP_MUL_MEAT_DW_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm)\n+# define _FP_MUL_MEAT_DW_Q(R, X, Y)\t\t\t\t\t\\\n+ _FP_MUL_MEAT_DW_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm)\n+\n+# define _FP_DIV_MEAT_S(R, X, Y)\t_FP_DIV_MEAT_1_udiv_norm (S, R, X, Y)\n+# define _FP_DIV_MEAT_D(R, X, Y)\t_FP_DIV_MEAT_2_udiv (D, R, X, Y)\n+# define _FP_DIV_MEAT_Q(R, X, Y)\t_FP_DIV_MEAT_4_udiv (Q, R, X, Y)\n+\n+# define _FP_NANFRAC_S\t\t_FP_QNANBIT_S\n+# define _FP_NANFRAC_D\t\t_FP_QNANBIT_D, 0\n+# define _FP_NANFRAC_Q\t\t_FP_QNANBIT_Q, 0, 0, 0\n+\n+#else /* #if __loongarch_grlen == 32 */\n+\n #define _FP_W_TYPE_SIZE 64\n #define _FP_W_TYPE unsigned long\n #define _FP_WS_TYPE signed long\n@@ -47,6 +78,8 @@\n #define _FP_NANFRAC_D _FP_QNANBIT_D\n #define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0\n \n+#endif /* #if __loongarch_grlen == 32 */\n+\n #define _FP_NANSIGN_S 0\n #define _FP_NANSIGN_D 0\n #define _FP_NANSIGN_Q 0\ndiff --git a/sysdeps/loongarch/start.S b/sysdeps/loongarch/start.S\nindex 754c08dc1f..8eb2ab0eab 100644\n--- a/sysdeps/loongarch/start.S\n+++ b/sysdeps/loongarch/start.S\n@@ -57,23 +57,39 @@ ENTRY (ENTRY_POINT)\n /* Terminate call stack by noting ra is undefined. Use a dummy\n .cfi_label to force starting the FDE. */\n \t.cfi_label .Ldummy\n-\tcfi_undefined (1)\n+\tcfi_undefined\t(1)\n \tor\t\ta5, a0, zero /* rtld_fini */\n \n-\tla.pcrel\ta0, t0, main\n+#\tLOAD_ADDR\t(a0, main)\n+#if defined PIC && !defined SHARED\n+\t/* Avoid relocation in static PIE since _start is called before it\n+\t is relocated. */\n+\tla.pcrel\ta0, __wrap_main\n+#else\n+\tLA_GOT\t\t(a0, main)\n+#endif\n+\n \tREG_L\t\ta1, sp, 0\n \tADDI\t\ta2, sp, SZREG\n \n-\t/* Adjust $sp for 16-aligned */\n-\tBSTRINS\t\tsp, zero, 3, 0\n+\t/* Adjust $sp for 16-bytes aligned */\n+\tREG_ALIGN_ASM\t(sp, 4)\n \n \tmove\t\ta3, zero /* used to be init */\n \tmove\t\ta4, zero /* used to be fini */\n \tor\t\ta6, sp, zero /* stack_end */\n \n-\tla.pcrel\tra, t0, __libc_start_main\n-\tjirl\t\tra, ra, 0\n+#\tLOAD_ADDR\t(ra, __libc_start_main)\n+#\tjirl\t\tra, ra, 0\n+#\n+#\tLOAD_ADDR\t(ra, abort)\n+#\tjirl\t\tra, ra, 0\n+\n+\tCALL\t\t(__libc_start_main)\n+\tCALL\t\t(abort)\n \n-\tla.pcrel\tra, t0, abort\n-\tjirl\t\tra, ra, 0\n+#if defined PIC && !defined SHARED\n+__wrap_main:\n+\tTAIL\t\t(main)\n+#endif\n END (ENTRY_POINT)\ndiff --git a/sysdeps/loongarch/sys/asm.h b/sysdeps/loongarch/sys/asm.h\nindex 7ca98bfee7..66ed839418 100644\n--- a/sysdeps/loongarch/sys/asm.h\n+++ b/sysdeps/loongarch/sys/asm.h\n@@ -22,22 +22,103 @@\n #include <sys/regdef.h>\n #include <sysdeps/generic/sysdep.h>\n \n+#define STACK_ALIGN 16\n+\n /* Macros to handle different pointer/register sizes for 32/64-bit code. */\n+#if __loongarch_grlen == 64\n+#define PTRLOG 3\n #define SZREG 8\n-#define SZFREG 8\n-#define SZVREG 16\n-#define SZXREG 32\n #define REG_L ld.d\n #define REG_S st.d\n #define SRLI srli.d\n+#define SRAI srai.d\n #define SLLI slli.d\n #define ADDI addi.d\n #define ADD add.d\n #define SUB sub.d\n-#define BSTRINS bstrins.d\n #define LI li.d\n-#define FREG_L fld.d\n-#define FREG_S fst.d\n+#define BSTRINS bstrins.d\n+\n+/* Align reg to 2^n. Used in assembly. */\n+#define REG_ALIGN_ASM(reg, n) bstrins.d reg, zero, (n-1), 0\n+\n+/* Align reg to 2^n. Used in C. */\n+#define REG_ALIGN_C(reg, n) \\\n+ \"bstrins.d\\t\" __STRING(reg) \", $zero, (\" __STRING(n) \"-1), 0\"\n+\n+#define LOAD_ADDR(reg, sym) la.pcrel reg, t0, sym\n+\n+#define LOAD_LOCAL(reg, sym) \\\n+ pcalau12i reg, %pc_hi20(sym); \\\n+ ld.d\t reg, reg, %pc_lo12(sym);\n+\n+#define LOAD_GLOBAL(reg, sym) \\\n+ la.got reg, sym; \\\n+ ld.d\t reg, reg, 0;\n+\n+#define LA_GOT(reg, sym) la.got reg, t0, sym\n+\n+#define CALL(sym) call36 sym\n+#define TAIL(sym) tail36 t0, sym\n+\n+#elif __loongarch_grlen == 32\n+\n+#define PTRLOG 2\n+#define SZREG 4\n+#define REG_L ld.w\n+#define REG_S st.w\n+#define SRLI srli.w\n+#define SRAI srai.w\n+#define SLLI slli.w\n+#define ADDI addi.w\n+#define ADD add.w\n+#define SUB sub.w\n+#define LI li.w\n+#define BSTRINS bstrins.w\n+\n+/* LA32R not have bstrins.w, use srli.w and slli.w on both LA32S and LA32R. */\n+#define REG_ALIGN_ASM(reg, n) \\\n+ srli.w reg, reg, n; \\\n+ slli.w reg, reg, n;\n+\n+#define REG_ALIGN_C(reg, n) \\\n+ \"srli.w\\t\" __STRING(reg)\", \" __STRING(reg)\", \" __STRING(n) \"\\n\\t\" \\\n+ \"slli.w\\t\" __STRING(reg)\", \" __STRING(reg)\", \" __STRING(n)\n+\n+#define LOAD_ADDR(reg, sym) \\\n+ 1: pcaddu12i\treg, %pcadd_hi20(sym); \\\n+ addi.w\treg, reg, %pcadd_lo12(1b);\n+\n+#define LOAD_LOCAL(reg, sym) \\\n+ 1: pcaddu12i\treg, %pcadd_hi20(sym); \\\n+ ld.w\treg, reg, %pcadd_lo12(1b);\n+\n+#define LOAD_GLOBAL(reg, sym) \\\n+ 1: pcaddu12i\treg, %got_pcadd_hi20(sym); \\\n+ ld.w\treg, reg, %pcadd_lo12(1b); \\\n+ ld.w\treg, reg, 0;\n+\n+#define LA_GOT(reg, sym) la.got reg, sym\n+\n+#define CALL(sym) call30 sym\n+#define TAIL(sym) tail30 t0, sym\n+\n+#else\n+#error __loongarch_grlen must equal 32 or 64\n+#endif\n+\n+#if __loongarch_frlen == 64\n+ #define SZFREG 8\n+ #define FREG_L fld.d\n+ #define FREG_S fst.d\n+#elif __loongarch_frlen == 32\n+ #define SZFREG 4\n+ #define FREG_L fld.s\n+ #define FREG_S fst.s\n+#endif\n+\n+#define SZVREG 16\n+#define SZXREG 32\n \n /* Declare leaf routine.\n The usage of macro LEAF/ENTRY is as follows:\ndiff --git a/sysdeps/loongarch/tst-gnu2-tls2.h b/sysdeps/loongarch/tst-gnu2-tls2.h\nindex 007a4d6869..4abe76baa5 100644\n--- a/sysdeps/loongarch/tst-gnu2-tls2.h\n+++ b/sysdeps/loongarch/tst-gnu2-tls2.h\n@@ -25,17 +25,23 @@\n /* The instruction between BEFORE_TLSDESC_CALL and _dl_tlsdesc_dynamic,\n and the instruction between _dl_tlsdesc_dynamic and AFTER_TLSDESC_CALL,\n may modified most of the general-purpose register. */\n-#define\tSAVE_REGISTER(src)\t\t\t\t\t\t\\\n- asm volatile (\"st.d $r3, %0\" :\"=m\"(src) :);\n+\n+#if LOONGARCH_ABI_GRLEN == 64\n+ #define SAVE_REGISTER(src) asm volatile (\"st.d $r3, %0\" :\"=m\"(src) :);\n+#elif LOONGARCH_ABI_GRLEN == 32\n+ #define SAVE_REGISTER(src) asm volatile (\"st.w $r3, %0\" :\"=m\"(src) :);\n+#else\n+ #error LOONGARCH_ABI_GRLEN must equal 32 or 64\n+#endif\n \n #ifdef __loongarch_soft_float\n \n #define BEFORE_TLSDESC_CALL()\t\t\t\t\t\t\\\n- uint64_t src;\t\t\t\t\t\t\t\t\\\n+ long src;\t\t\t\t\t\t\t\t\\\n SAVE_REGISTER (src);\n \n #define AFTER_TLSDESC_CALL()\t\t\t\t\t\t\\\n- uint64_t restore;\t\t\t\t\t\t\t\\\n+ long restore;\t\t\t\t\t\t\t\\\n SAVE_REGISTER (restore);\t\t\t\t\t\t\\\n if (src != restore)\t\t\t\t\t\t\t\\\n abort ();\n@@ -53,12 +59,12 @@\n asm volatile (\"movcf2gr %0, $fcc7\" :\"=r\"(src[7]));\t\\\n \n #define LOAD_REGISTER_FCSR()\t\t\t\t\\\n- uint64_t src_fcsr = 0x01010101;\t\t\t\\\n- asm volatile (\"li.d $t0, 0x01010101\" ::: \"$t0\");\t\\\n+ int src_fcsr = 0x01010101;\t\t\t\\\n+ asm volatile (\"li.w $t0, 0x01010101\" ::: \"$t0\");\t\\\n asm volatile (\"movgr2fcsr $fcsr0, $t0\" :::);\n \n #define SAVE_REGISTER_FCSR()\t\t\t\t\t\t\\\n- uint64_t restore_fcsr;\t\t\t\t\t\t\\\n+ int restore_fcsr;\t\t\t\t\t\t\\\n asm volatile (\"movfcsr2gr %0, $fcsr0\" :\"=r\"(restore_fcsr));\t\t\\\n if (src_fcsr != restore_fcsr)\t\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n@@ -70,7 +76,7 @@\n unsigned long hwcap = getauxval (AT_HWCAP);\n \n #define\tLOAD_REGISTER_FLOAT()\t\t\t\t\t\t\\\n- for (int i = 0; i < 32; i++)\t\t\t\t\t\t\\\n+ for (int i = 0; i < 24; i++)\t\t\t\t\t\t\\\n src_float[i] = i + 1;\t\t\t\t\t\t\\\n asm volatile (\"fld.d $f0, %0\" ::\"m\"(src_float[0]) :\"$f0\");\t\t\\\n asm volatile (\"fld.d $f1, %0\" ::\"m\"(src_float[1]) :\"$f1\"); \t\t\\\n@@ -96,17 +102,9 @@\n asm volatile (\"fld.d $f21, %0\" ::\"m\"(src_float[21]) :\"$f21\");\t\t\\\n asm volatile (\"fld.d $f22, %0\" ::\"m\"(src_float[22]) :\"$f22\");\t\t\\\n asm volatile (\"fld.d $f23, %0\" ::\"m\"(src_float[23]) :\"$f23\");\t\t\\\n- asm volatile (\"fld.d $f24, %0\" ::\"m\"(src_float[24]) :\"$f24\");\t\t\\\n- asm volatile (\"fld.d $f25, %0\" ::\"m\"(src_float[25]) :\"$f25\");\t\t\\\n- asm volatile (\"fld.d $f26, %0\" ::\"m\"(src_float[26]) :\"$f26\");\t\t\\\n- asm volatile (\"fld.d $f27, %0\" ::\"m\"(src_float[27]) :\"$f27\");\t\t\\\n- asm volatile (\"fld.d $f28, %0\" ::\"m\"(src_float[28]) :\"$f28\");\t\t\\\n- asm volatile (\"fld.d $f29, %0\" ::\"m\"(src_float[29]) :\"$f29\");\t\t\\\n- asm volatile (\"fld.d $f30, %0\" ::\"m\"(src_float[30]) :\"$f30\");\t\t\\\n- asm volatile (\"fld.d $f31, %0\" ::\"m\"(src_float[31]) :\"$f31\");\n \n #define\tSAVE_REGISTER_FLOAT()\t\t\t\t\t\t\\\n- double restore_float[32];\t\t\t\t\t\t\\\n+ double restore_float[24];\t\t\t\t\t\t\\\n asm volatile (\"fst.d $f0, %0\" :\"=m\"(restore_float[0]));\t\t\\\n asm volatile (\"fst.d $f1, %0\" :\"=m\"(restore_float[1])); \t\t\\\n asm volatile (\"fst.d $f2, %0\" :\"=m\"(restore_float[2])); \t\t\\\n@@ -131,14 +129,6 @@\n asm volatile (\"fst.d $f21, %0\" :\"=m\"(restore_float[21]));\t\t\\\n asm volatile (\"fst.d $f22, %0\" :\"=m\"(restore_float[22]));\t\t\\\n asm volatile (\"fst.d $f23, %0\" :\"=m\"(restore_float[23]));\t\t\\\n- asm volatile (\"fst.d $f24, %0\" :\"=m\"(restore_float[24]));\t\t\\\n- asm volatile (\"fst.d $f25, %0\" :\"=m\"(restore_float[25]));\t\t\\\n- asm volatile (\"fst.d $f26, %0\" :\"=m\"(restore_float[26]));\t\t\\\n- asm volatile (\"fst.d $f27, %0\" :\"=m\"(restore_float[27]));\t\t\\\n- asm volatile (\"fst.d $f28, %0\" :\"=m\"(restore_float[28]));\t\t\\\n- asm volatile (\"fst.d $f29, %0\" :\"=m\"(restore_float[29]));\t\t\\\n- asm volatile (\"fst.d $f30, %0\" :\"=m\"(restore_float[30]));\t\t\\\n- asm volatile (\"fst.d $f31, %0\" :\"=m\"(restore_float[31]));\t\t\\\n if (memcmp (src_float, restore_float, sizeof (src_float)) != 0)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n printf (\"Float registers compare failed!\\n\");\t\t\t\\\n@@ -325,9 +315,9 @@\n #endif\n \n #define BEFORE_TLSDESC_CALL()\t\t\t\t\t\t\\\n- uint64_t src;\t\t\t\t\t\t\t\t\\\n- double src_float[32];\t\t\t\t\t\t\t\\\n- uint64_t src_fcc[8];\t\t\t\t\t\t\t\\\n+ long src;\t\t\t\t\t\t\t\t\\\n+ double src_float[24];\t\t\t\t\t\t\t\\\n+ int src_fcc[8];\t\t\t\t\t\t\t\\\n SAVE_REGISTER (src);\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n if (hwcap & HWCAP_LOONGARCH_LASX)\t\t\t\t\t\\\n@@ -349,8 +339,8 @@\n \n \n #define AFTER_TLSDESC_CALL()\t\t\t\t\t\t\\\n- uint64_t restore;\t\t\t\t\t\t\t\\\n- uint64_t restore_fcc[8];\t\t\t\t\t\t\\\n+ long restore;\t\t\t\t\t\t\t\\\n+ int restore_fcc[8];\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n SAVE_REGISTER (restore);\t\t\t\t\t\t\\\n if (src != restore)\t\t\t\t\t\t\t\\\n", "prefixes": [ "v2", "1/5" ] }