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{
    "id": 2175543,
    "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175543/?format=api",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20251218083326.644326-3-brian.ruley@gehealthcare.com>",
    "date": "2025-12-18T08:33:21",
    "name": "[v1,2/7] video: imx: ipuv3: apply clang-format",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "7849c89030e5d0eb46f3957b1696669f59d67509",
    "submitter": {
        "id": 89422,
        "url": "http://patchwork.ozlabs.org/api/1.0/people/89422/?format=api",
        "name": "Brian Ruley",
        "email": "brian.ruley@gehealthcare.com"
    },
    "delegate": {
        "id": 151988,
        "url": "http://patchwork.ozlabs.org/api/1.0/users/151988/?format=api",
        "username": "festevam",
        "first_name": "Fabio",
        "last_name": "Estevam",
        "email": "festevam@gmail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218083326.644326-3-brian.ruley@gehealthcare.com/mbox/",
    "series": [
        {
            "id": 485836,
            "url": "http://patchwork.ozlabs.org/api/1.0/series/485836/?format=api",
            "date": "2025-12-18T08:33:20",
            "name": "Refactor i.MX IPU driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/485836/mbox/"
        }
    ],
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2175543/checks/",
    "tags": {},
    "headers": {
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        "From": "Brian Ruley <brian.ruley@gehealthcare.com>",
        "To": "u-boot@lists.denx.de, Anatolij Gustschin <ag.dev.uboot@gmail.com>,\n Tom Rini <trini@konsulko.com>",
        "Cc": "Brian Ruley <brian.ruley@gehealthcare.com>,\n Stefano Babic <sbabic@nabladev.com>",
        "Subject": "[PATCH v1 2/7] video: imx: ipuv3: apply clang-format",
        "Date": "Thu, 18 Dec 2025 10:33:21 +0200",
        "Message-Id": "<20251218083326.644326-3-brian.ruley@gehealthcare.com>",
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    "content": "Bring the code into compliance with U-Boot's coding style guidelines for\nupcoming changes. Sort includes to tidy things up and apply\n{ RemoveBracesLLVM: true } to remove unnecessary blocks.\n\nSigned-off-by: Brian Ruley <brian.ruley@gehealthcare.com>\n---\n\n drivers/video/imx/ipu.h          |  91 ++---\n drivers/video/imx/ipu_common.c   | 483 +++++++++++------------\n drivers/video/imx/ipu_disp.c     | 645 +++++++++++++++----------------\n drivers/video/imx/ipu_regs.h     | 266 +++++++------\n drivers/video/imx/mxc_ipuv3_fb.c | 163 ++++----\n 5 files changed, 770 insertions(+), 878 deletions(-)",
    "diff": "diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h\nindex 93bc97e6300..58f68b6b9cf 100644\n--- a/drivers/video/imx/ipu.h\n+++ b/drivers/video/imx/ipu.h\n@@ -13,11 +13,11 @@\n #ifndef __ASM_ARCH_IPU_H__\n #define __ASM_ARCH_IPU_H__\n \n-#include <linux/types.h>\n #include <ipu_pixfmt.h>\n+#include <linux/types.h>\n \n-#define IDMA_CHAN_INVALID\t0xFF\n-#define HIGH_RESOLUTION_WIDTH\t1024\n+#define IDMA_CHAN_INVALID 0xFF\n+#define HIGH_RESOLUTION_WIDTH 1024\n \n struct clk {\n \tconst char *name;\n@@ -39,30 +39,30 @@ struct clk {\n \t * Function ptr to recalculate the clock's rate based on parent\n \t * clock's rate\n \t */\n-\tvoid (*recalc) (struct clk *);\n+\tvoid (*recalc)(struct clk *);\n \t/*\n \t * Function ptr to set the clock to a new rate. The rate must match a\n \t * supported rate returned from round_rate. Leave blank if clock is not\n \t* programmable\n \t */\n-\tint (*set_rate) (struct clk *, unsigned long);\n+\tint (*set_rate)(struct clk *, unsigned long);\n \t/*\n \t * Function ptr to round the requested clock rate to the nearest\n \t * supported rate that is less than or equal to the requested rate.\n \t */\n-\tunsigned long (*round_rate) (struct clk *, unsigned long);\n+\tunsigned long (*round_rate)(struct clk *, unsigned long);\n \t/*\n \t * Function ptr to enable the clock. Leave blank if clock can not\n \t * be gated.\n \t */\n-\tint (*enable) (struct clk *);\n+\tint (*enable)(struct clk *);\n \t/*\n \t * Function ptr to disable the clock. Leave blank if clock can not\n \t * be gated.\n \t */\n-\tvoid (*disable) (struct clk *);\n+\tvoid (*disable)(struct clk *);\n \t/* Function ptr to set the parent clock of the clock. */\n-\tint (*set_parent) (struct clk *, struct clk *);\n+\tint (*set_parent)(struct clk *, struct clk *);\n };\n \n /*\n@@ -77,18 +77,18 @@ typedef enum {\n  * IPU Driver channels definitions.\n  * Note these are different from IDMA channels\n  */\n-#define IPU_MAX_CH\t32\n+#define IPU_MAX_CH 32\n #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \\\n \t((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)\n-#define _MAKE_ALT_CHAN(ch)\t\t(ch | (IPU_MAX_CH << 24))\n-#define IPU_CHAN_ID(ch)\t\t\t(ch >> 24)\n-#define IPU_CHAN_ALT(ch)\t\t(ch & 0x02000000)\n-#define IPU_CHAN_ALPHA_IN_DMA(ch)\t((uint32_t) (ch >> 6) & 0x3F)\n-#define IPU_CHAN_GRAPH_IN_DMA(ch)\t((uint32_t) (ch >> 12) & 0x3F)\n-#define IPU_CHAN_VIDEO_IN_DMA(ch)\t((uint32_t) (ch >> 18) & 0x3F)\n-#define IPU_CHAN_OUT_DMA(ch)\t\t((uint32_t) (ch & 0x3F))\n+#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))\n+#define IPU_CHAN_ID(ch) (ch >> 24)\n+#define IPU_CHAN_ALT(ch) (ch & 0x02000000)\n+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t)(ch >> 6) & 0x3F)\n+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t)(ch >> 12) & 0x3F)\n+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t)(ch >> 18) & 0x3F)\n+#define IPU_CHAN_OUT_DMA(ch) ((uint32_t)(ch & 0x3F))\n #define NO_DMA 0x3F\n-#define ALT\t1\n+#define ALT 1\n \n /*\n  * Enumeration of IPU logical channels. An IPU logical channel is defined as a\n@@ -118,16 +118,16 @@ typedef enum {\n  * Enumeration of types of buffers for a logical channel.\n  */\n typedef enum {\n-\tIPU_OUTPUT_BUFFER = 0,\t/*< Buffer for output from IPU */\n-\tIPU_ALPHA_IN_BUFFER = 1,\t/*< Buffer for input to IPU */\n-\tIPU_GRAPH_IN_BUFFER = 2,\t/*< Buffer for input to IPU */\n-\tIPU_VIDEO_IN_BUFFER = 3,\t/*< Buffer for input to IPU */\n+\tIPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */\n+\tIPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */\n+\tIPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */\n+\tIPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */\n \tIPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,\n \tIPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,\n } ipu_buffer_t;\n \n-#define IPU_PANEL_SERIAL\t\t1\n-#define IPU_PANEL_PARALLEL\t\t2\n+#define IPU_PANEL_SERIAL 1\n+#define IPU_PANEL_PARALLEL 2\n \n struct ipu_channel {\n \tu8 video_in_dma;\n@@ -185,45 +185,38 @@ enum ipu_irq_line {\n  * Bitfield of Display Interface signal polarities.\n  */\n typedef struct {\n-\tunsigned datamask_en:1;\n-\tunsigned ext_clk:1;\n-\tunsigned interlaced:1;\n-\tunsigned odd_field_first:1;\n-\tunsigned clksel_en:1;\n-\tunsigned clkidle_en:1;\n-\tunsigned data_pol:1;\t/* true = inverted */\n-\tunsigned clk_pol:1;\t/* true = rising edge */\n-\tunsigned enable_pol:1;\n-\tunsigned Hsync_pol:1;\t/* true = active high */\n-\tunsigned Vsync_pol:1;\n+\tunsigned datamask_en : 1;\n+\tunsigned ext_clk : 1;\n+\tunsigned interlaced : 1;\n+\tunsigned odd_field_first : 1;\n+\tunsigned clksel_en : 1;\n+\tunsigned clkidle_en : 1;\n+\tunsigned data_pol : 1; /* true = inverted */\n+\tunsigned clk_pol : 1; /* true = rising edge */\n+\tunsigned enable_pol : 1;\n+\tunsigned Hsync_pol : 1; /* true = active high */\n+\tunsigned Vsync_pol : 1;\n } ipu_di_signal_cfg_t;\n \n-typedef enum {\n-\tRGB,\n-\tYCbCr,\n-\tYUV\n-} ipu_color_space_t;\n+typedef enum { RGB, YCbCr, YUV } ipu_color_space_t;\n \n /* Common IPU API */\n int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);\n void ipu_uninit_channel(ipu_channel_t channel);\n \n int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t\tuint32_t pixel_fmt,\n-\t\t\t\tuint16_t width, uint16_t height,\n-\t\t\t\tuint32_t stride,\n+\t\t\t\tuint32_t pixel_fmt, uint16_t width,\n+\t\t\t\tuint16_t height, uint32_t stride,\n \t\t\t\tdma_addr_t phyaddr_0, dma_addr_t phyaddr_1,\n \t\t\t\tuint32_t u_offset, uint32_t v_offset);\n \n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\tuint32_t bufNum);\n+\t\t\t    uint32_t bufNum);\n int32_t ipu_enable_channel(ipu_channel_t channel);\n int32_t ipu_disable_channel(ipu_channel_t channel);\n \n-int32_t ipu_init_sync_panel(int disp,\n-\t\t\t    uint32_t pixel_clk,\n-\t\t\t    uint16_t width, uint16_t height,\n-\t\t\t    uint32_t pixel_fmt,\n+int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,\n+\t\t\t    uint16_t height, uint32_t pixel_fmt,\n \t\t\t    uint16_t h_start_width, uint16_t h_sync_width,\n \t\t\t    uint16_t h_end_width, uint16_t v_start_width,\n \t\t\t    uint16_t v_sync_width, uint16_t v_end_width,\n@@ -256,7 +249,7 @@ void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);\n void ipu_dc_uninit(int dc_chan);\n void ipu_dp_dc_enable(ipu_channel_t channel);\n int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n-\t\t uint32_t out_pixel_fmt);\n+\t\tuint32_t out_pixel_fmt);\n void ipu_dp_uninit(ipu_channel_t channel);\n void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);\n ipu_color_space_t format_to_colorspace(uint32_t fmt);\ndiff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c\nindex 61a3fe1e83b..72421aa5a03 100644\n--- a/drivers/video/imx/ipu_common.c\n+++ b/drivers/video/imx/ipu_common.c\n@@ -11,19 +11,19 @@\n  */\n \n /* #define DEBUG */\n+#include \"ipu.h\"\n+#include \"ipu_regs.h\"\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/io.h>\n #include <config.h>\n-#include <log.h>\n+#include <div64.h>\n #include <linux/delay.h>\n-#include <linux/types.h>\n #include <linux/err.h>\n-#include <asm/io.h>\n #include <linux/errno.h>\n-#include <asm/arch/imx-regs.h>\n-#include <asm/arch/crm_regs.h>\n-#include <asm/arch/sys_proto.h>\n-#include <div64.h>\n-#include \"ipu.h\"\n-#include \"ipu_regs.h\"\n+#include <linux/types.h>\n+#include <log.h>\n \n extern struct mxc_ccm_reg *mxc_ccm;\n extern u32 *ipu_cpmem_base;\n@@ -39,61 +39,63 @@ struct ipu_ch_param {\n \n #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))\n \n-#define _param_word(base, w) \\\n-\t(((struct ipu_ch_param *)(base))->word[(w)].data)\n-\n-#define ipu_ch_param_set_field(base, w, bit, size, v) { \\\n-\tint i = (bit) / 32; \\\n-\tint off = (bit) % 32; \\\n-\t_param_word(base, w)[i] |= (v) << off; \\\n-\tif (((bit) + (size) - 1) / 32 > i) { \\\n-\t\t_param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \\\n-\t} \\\n-}\n+#define _param_word(base, w) (((struct ipu_ch_param *)(base))->word[(w)].data)\n+\n+#define ipu_ch_param_set_field(base, w, bit, size, v)                          \\\n+\t{                                                                      \\\n+\t\tint i = (bit) / 32;                                            \\\n+\t\tint off = (bit) % 32;                                          \\\n+\t\t_param_word(base, w)[i] |= (v) << off;                         \\\n+\t\tif (((bit) + (size) - 1) / 32 > i) {                           \\\n+\t\t\t_param_word(base, w)[i + 1] |= (v) >>                  \\\n+\t\t\t\t\t\t       (off ? (32 - off) : 0); \\\n+\t\t}                                                              \\\n+\t}\n \n-#define ipu_ch_param_mod_field(base, w, bit, size, v) { \\\n-\tint i = (bit) / 32; \\\n-\tint off = (bit) % 32; \\\n-\tu32 mask = (1UL << size) - 1; \\\n-\tu32 temp = _param_word(base, w)[i]; \\\n-\ttemp &= ~(mask << off); \\\n-\t_param_word(base, w)[i] = temp | (v) << off; \\\n-\tif (((bit) + (size) - 1) / 32 > i) { \\\n-\t\ttemp = _param_word(base, w)[i + 1]; \\\n-\t\ttemp &= ~(mask >> (32 - off)); \\\n-\t\t_param_word(base, w)[i + 1] = \\\n-\t\t\ttemp | ((v) >> (off ? (32 - off) : 0)); \\\n-\t} \\\n-}\n+#define ipu_ch_param_mod_field(base, w, bit, size, v)                   \\\n+\t{                                                               \\\n+\t\tint i = (bit) / 32;                                     \\\n+\t\tint off = (bit) % 32;                                   \\\n+\t\tu32 mask = (1UL << size) - 1;                           \\\n+\t\tu32 temp = _param_word(base, w)[i];                     \\\n+\t\ttemp &= ~(mask << off);                                 \\\n+\t\t_param_word(base, w)[i] = temp | (v) << off;            \\\n+\t\tif (((bit) + (size) - 1) / 32 > i) {                    \\\n+\t\t\ttemp = _param_word(base, w)[i + 1];             \\\n+\t\t\ttemp &= ~(mask >> (32 - off));                  \\\n+\t\t\t_param_word(base, w)[i + 1] =                   \\\n+\t\t\t\ttemp | ((v) >> (off ? (32 - off) : 0)); \\\n+\t\t}                                                       \\\n+\t}\n \n-#define ipu_ch_param_read_field(base, w, bit, size) ({ \\\n-\tu32 temp2; \\\n-\tint i = (bit) / 32; \\\n-\tint off = (bit) % 32; \\\n-\tu32 mask = (1UL << size) - 1; \\\n-\tu32 temp1 = _param_word(base, w)[i]; \\\n-\ttemp1 = mask & (temp1 >> off); \\\n-\tif (((bit)+(size) - 1) / 32 > i) { \\\n-\t\ttemp2 = _param_word(base, w)[i + 1]; \\\n-\t\ttemp2 &= mask >> (off ? (32 - off) : 0); \\\n-\t\ttemp1 |= temp2 << (off ? (32 - off) : 0); \\\n-\t} \\\n-\ttemp1; \\\n-})\n-\n-#define IPU_SW_RST_TOUT_USEC\t(10000)\n-\n-#define IPUV3_CLK_MX51\t\t133000000\n-#define IPUV3_CLK_MX53\t\t200000000\n-#define IPUV3_CLK_MX6Q\t\t264000000\n-#define IPUV3_CLK_MX6DL\t\t198000000\n+#define ipu_ch_param_read_field(base, w, bit, size)               \\\n+\t({                                                        \\\n+\t\tu32 temp2;                                        \\\n+\t\tint i = (bit) / 32;                               \\\n+\t\tint off = (bit) % 32;                             \\\n+\t\tu32 mask = (1UL << size) - 1;                     \\\n+\t\tu32 temp1 = _param_word(base, w)[i];              \\\n+\t\ttemp1 = mask & (temp1 >> off);                    \\\n+\t\tif (((bit) + (size) - 1) / 32 > i) {              \\\n+\t\t\ttemp2 = _param_word(base, w)[i + 1];      \\\n+\t\t\ttemp2 &= mask >> (off ? (32 - off) : 0);  \\\n+\t\t\ttemp1 |= temp2 << (off ? (32 - off) : 0); \\\n+\t\t}                                                 \\\n+\t\ttemp1;                                            \\\n+\t})\n+\n+#define IPU_SW_RST_TOUT_USEC (10000)\n+\n+#define IPUV3_CLK_MX51 133000000\n+#define IPUV3_CLK_MX53 200000000\n+#define IPUV3_CLK_MX6Q 264000000\n+#define IPUV3_CLK_MX6DL 198000000\n \n void clk_enable(struct clk *clk)\n {\n \tif (clk) {\n-\t\tif (clk->usecount++ == 0) {\n+\t\tif (clk->usecount++ == 0)\n \t\t\tclk->enable(clk);\n-\t\t}\n \t}\n }\n \n@@ -207,12 +209,12 @@ static void clk_ipu_disable(struct clk *clk)\n static struct clk ipu_clk = {\n \t.name = \"ipu_clk\",\n #if defined(CONFIG_MX51) || defined(CONFIG_MX53)\n-\t.enable_reg = (u32 *)(CCM_BASE_ADDR +\n-\t\toffsetof(struct mxc_ccm_reg, CCGR5)),\n+\t.enable_reg =\n+\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)),\n \t.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,\n #else\n-\t.enable_reg = (u32 *)(CCM_BASE_ADDR +\n-\t\toffsetof(struct mxc_ccm_reg, CCGR3)),\n+\t.enable_reg =\n+\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3)),\n \t.enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,\n #endif\n \t.enable = clk_ipu_enable,\n@@ -257,7 +259,7 @@ static inline void ipu_ch_param_set_high_priority(uint32_t ch)\n \n static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)\n {\n-\treturn ((uint32_t) ch >> (6 * type)) & 0x3F;\n+\treturn ((uint32_t)ch >> (6 * type)) & 0x3F;\n };\n \n /* Either DP BG or DP FG can be graphic window */\n@@ -272,15 +274,15 @@ static inline int ipu_is_dmfc_chan(uint32_t dma_chan)\n }\n \n static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,\n-\t\t\t\t\t    dma_addr_t phyaddr)\n+\t\t\t\t\t   dma_addr_t phyaddr)\n {\n \tipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,\n \t\t\t       phyaddr / 8);\n };\n \n-#define idma_is_valid(ch)\t(ch != NO_DMA)\n-#define idma_mask(ch)\t\t(idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)\n-#define idma_is_set(reg, dma)\t(__raw_readl(reg(dma)) & idma_mask(dma))\n+#define idma_is_valid(ch) (ch != NO_DMA)\n+#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)\n+#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))\n \n static void ipu_pixel_clk_recalc(struct clk *clk)\n {\n@@ -288,8 +290,8 @@ static void ipu_pixel_clk_recalc(struct clk *clk)\n \tu64 final_rate = (unsigned long long)clk->parent->rate * 16;\n \n \tdiv = __raw_readl(DI_BS_CLKGEN0(clk->id));\n-\tdebug(\"read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\\n\",\n-\t      div, final_rate, clk->parent->rate);\n+\tdebug(\"read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\\n\", div,\n+\t      final_rate, clk->parent->rate);\n \n \tclk->rate = 0;\n \tif (div != 0) {\n@@ -299,7 +301,7 @@ static void ipu_pixel_clk_recalc(struct clk *clk)\n }\n \n static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,\n-\tunsigned long rate)\n+\t\t\t\t\t      unsigned long rate)\n {\n \tu64 div, final_rate;\n \tu32 remainder;\n@@ -315,7 +317,7 @@ static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,\n \t/* Round the divider value */\n \tif (remainder > (rate / 2))\n \t\tdiv++;\n-\tif (div < 0x10)            /* Min DI disp clock divider is 1 */\n+\tif (div < 0x10) /* Min DI disp clock divider is 1 */\n \t\tdiv = 0x10;\n \tif (div & ~0xFEF)\n \t\tdiv &= 0xFF8;\n@@ -381,7 +383,6 @@ static void ipu_pixel_clk_disable(struct clk *clk)\n \tu32 disp_gen = __raw_readl(IPU_DISP_GEN);\n \tdisp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;\n \t__raw_writel(disp_gen, IPU_DISP_GEN);\n-\n }\n \n static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)\n@@ -402,26 +403,26 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)\n \n static struct clk pixel_clk[] = {\n \t{\n-\t.name = \"pixel_clk\",\n-\t.id = 0,\n-\t.recalc = ipu_pixel_clk_recalc,\n-\t.set_rate = ipu_pixel_clk_set_rate,\n-\t.round_rate = ipu_pixel_clk_round_rate,\n-\t.set_parent = ipu_pixel_clk_set_parent,\n-\t.enable = ipu_pixel_clk_enable,\n-\t.disable = ipu_pixel_clk_disable,\n-\t.usecount = 0,\n+\t\t.name = \"pixel_clk\",\n+\t\t.id = 0,\n+\t\t.recalc = ipu_pixel_clk_recalc,\n+\t\t.set_rate = ipu_pixel_clk_set_rate,\n+\t\t.round_rate = ipu_pixel_clk_round_rate,\n+\t\t.set_parent = ipu_pixel_clk_set_parent,\n+\t\t.enable = ipu_pixel_clk_enable,\n+\t\t.disable = ipu_pixel_clk_disable,\n+\t\t.usecount = 0,\n \t},\n \t{\n-\t.name = \"pixel_clk\",\n-\t.id = 1,\n-\t.recalc = ipu_pixel_clk_recalc,\n-\t.set_rate = ipu_pixel_clk_set_rate,\n-\t.round_rate = ipu_pixel_clk_round_rate,\n-\t.set_parent = ipu_pixel_clk_set_parent,\n-\t.enable = ipu_pixel_clk_enable,\n-\t.disable = ipu_pixel_clk_disable,\n-\t.usecount = 0,\n+\t\t.name = \"pixel_clk\",\n+\t\t.id = 1,\n+\t\t.recalc = ipu_pixel_clk_recalc,\n+\t\t.set_rate = ipu_pixel_clk_set_rate,\n+\t\t.round_rate = ipu_pixel_clk_round_rate,\n+\t\t.set_parent = ipu_pixel_clk_set_parent,\n+\t\t.enable = ipu_pixel_clk_enable,\n+\t\t.disable = ipu_pixel_clk_disable,\n+\t\t.usecount = 0,\n \t},\n };\n \n@@ -455,7 +456,7 @@ static void ipu_reset(void)\n  * @param\tdev\tThe device structure for the IPU passed in by the\n  *\t\t\tdriver framework.\n  *\n- * Return:      Returns 0 on success or negative error code on error\n+ * Return:\tReturns 0 on success or negative error code on error\n  */\n int ipu_probe(void)\n {\n@@ -466,11 +467,11 @@ int ipu_probe(void)\n \tu32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;\n \tu32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);\n \n-\t __raw_writel(0xF00, reg_hsc_mcd);\n+\t__raw_writel(0xF00, reg_hsc_mcd);\n \n \t/* CSI mode reserved*/\n \ttemp = __raw_readl(reg_hsc_mxt_conf);\n-\t __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);\n+\t__raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);\n \n \ttemp = __raw_readl(reg_hsc_mxt_conf);\n \t__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);\n@@ -532,47 +533,34 @@ void ipu_dump_registers(void)\n {\n \tdebug(\"IPU_CONF = \\t0x%08X\\n\", __raw_readl(IPU_CONF));\n \tdebug(\"IDMAC_CONF = \\t0x%08X\\n\", __raw_readl(IDMAC_CONF));\n-\tdebug(\"IDMAC_CHA_EN1 = \\t0x%08X\\n\",\n-\t       __raw_readl(IDMAC_CHA_EN(0)));\n-\tdebug(\"IDMAC_CHA_EN2 = \\t0x%08X\\n\",\n-\t       __raw_readl(IDMAC_CHA_EN(32)));\n-\tdebug(\"IDMAC_CHA_PRI1 = \\t0x%08X\\n\",\n-\t       __raw_readl(IDMAC_CHA_PRI(0)));\n-\tdebug(\"IDMAC_CHA_PRI2 = \\t0x%08X\\n\",\n-\t       __raw_readl(IDMAC_CHA_PRI(32)));\n+\tdebug(\"IDMAC_CHA_EN1 = \\t0x%08X\\n\", __raw_readl(IDMAC_CHA_EN(0)));\n+\tdebug(\"IDMAC_CHA_EN2 = \\t0x%08X\\n\", __raw_readl(IDMAC_CHA_EN(32)));\n+\tdebug(\"IDMAC_CHA_PRI1 = \\t0x%08X\\n\", __raw_readl(IDMAC_CHA_PRI(0)));\n+\tdebug(\"IDMAC_CHA_PRI2 = \\t0x%08X\\n\", __raw_readl(IDMAC_CHA_PRI(32)));\n \tdebug(\"IPU_CHA_DB_MODE_SEL0 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_CHA_DB_MODE_SEL(0)));\n+\t      __raw_readl(IPU_CHA_DB_MODE_SEL(0)));\n \tdebug(\"IPU_CHA_DB_MODE_SEL1 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_CHA_DB_MODE_SEL(32)));\n-\tdebug(\"DMFC_WR_CHAN = \\t0x%08X\\n\",\n-\t       __raw_readl(DMFC_WR_CHAN));\n-\tdebug(\"DMFC_WR_CHAN_DEF = \\t0x%08X\\n\",\n-\t       __raw_readl(DMFC_WR_CHAN_DEF));\n-\tdebug(\"DMFC_DP_CHAN = \\t0x%08X\\n\",\n-\t       __raw_readl(DMFC_DP_CHAN));\n-\tdebug(\"DMFC_DP_CHAN_DEF = \\t0x%08X\\n\",\n-\t       __raw_readl(DMFC_DP_CHAN_DEF));\n-\tdebug(\"DMFC_IC_CTRL = \\t0x%08X\\n\",\n-\t       __raw_readl(DMFC_IC_CTRL));\n-\tdebug(\"IPU_FS_PROC_FLOW1 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_FS_PROC_FLOW1));\n-\tdebug(\"IPU_FS_PROC_FLOW2 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_FS_PROC_FLOW2));\n-\tdebug(\"IPU_FS_PROC_FLOW3 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_FS_PROC_FLOW3));\n-\tdebug(\"IPU_FS_DISP_FLOW1 = \\t0x%08X\\n\",\n-\t       __raw_readl(IPU_FS_DISP_FLOW1));\n+\t      __raw_readl(IPU_CHA_DB_MODE_SEL(32)));\n+\tdebug(\"DMFC_WR_CHAN = \\t0x%08X\\n\", __raw_readl(DMFC_WR_CHAN));\n+\tdebug(\"DMFC_WR_CHAN_DEF = \\t0x%08X\\n\", __raw_readl(DMFC_WR_CHAN_DEF));\n+\tdebug(\"DMFC_DP_CHAN = \\t0x%08X\\n\", __raw_readl(DMFC_DP_CHAN));\n+\tdebug(\"DMFC_DP_CHAN_DEF = \\t0x%08X\\n\", __raw_readl(DMFC_DP_CHAN_DEF));\n+\tdebug(\"DMFC_IC_CTRL = \\t0x%08X\\n\", __raw_readl(DMFC_IC_CTRL));\n+\tdebug(\"IPU_FS_PROC_FLOW1 = \\t0x%08X\\n\", __raw_readl(IPU_FS_PROC_FLOW1));\n+\tdebug(\"IPU_FS_PROC_FLOW2 = \\t0x%08X\\n\", __raw_readl(IPU_FS_PROC_FLOW2));\n+\tdebug(\"IPU_FS_PROC_FLOW3 = \\t0x%08X\\n\", __raw_readl(IPU_FS_PROC_FLOW3));\n+\tdebug(\"IPU_FS_DISP_FLOW1 = \\t0x%08X\\n\", __raw_readl(IPU_FS_DISP_FLOW1));\n }\n \n /*\n  * This function is called to initialize a logical IPU channel.\n  *\n- * @param       channel Input parameter for the logical channel ID to init.\n+ * @param\tchannel Input parameter for the logical channel ID to init.\n  *\n- * @param       params  Input parameter containing union of channel\n- *                      initialization parameters.\n+ * @param\tparams\tInput parameter containing union of channel\n+ *\t\t\tinitialization parameters.\n  *\n- * Return:      Returns 0 on success or negative error code on fail\n+ * Return:\tReturns 0 on success or negative error code on fail\n  */\n int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n {\n@@ -588,7 +576,7 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n \n \tif (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {\n \t\tprintf(\"Warning: channel already initialized %d\\n\",\n-\t\t\tIPU_CHAN_ID(channel));\n+\t\t       IPU_CHAN_ID(channel));\n \t}\n \n \tipu_conf = __raw_readl(IPU_CONF);\n@@ -602,7 +590,7 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n \n \t\tg_dc_di_assignment[1] = params->mem_dc_sync.di;\n \t\tipu_dc_init(1, params->mem_dc_sync.di,\n-\t\t\t     params->mem_dc_sync.interlaced);\n+\t\t\t    params->mem_dc_sync.interlaced);\n \t\tipu_di_use_count[params->mem_dc_sync.di]++;\n \t\tipu_dc_use_count++;\n \t\tipu_dmfc_use_count++;\n@@ -615,9 +603,9 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n \n \t\tg_dc_di_assignment[5] = params->mem_dp_bg_sync.di;\n \t\tipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,\n-\t\t\t     params->mem_dp_bg_sync.out_pixel_fmt);\n+\t\t\t    params->mem_dp_bg_sync.out_pixel_fmt);\n \t\tipu_dc_init(5, params->mem_dp_bg_sync.di,\n-\t\t\t     params->mem_dp_bg_sync.interlaced);\n+\t\t\t    params->mem_dp_bg_sync.interlaced);\n \t\tipu_di_use_count[params->mem_dp_bg_sync.di]++;\n \t\tipu_dc_use_count++;\n \t\tipu_dp_use_count++;\n@@ -625,7 +613,7 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n \t\tbreak;\n \tcase MEM_FG_SYNC:\n \t\tipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,\n-\t\t\t     params->mem_dp_fg_sync.out_pixel_fmt);\n+\t\t\t    params->mem_dp_fg_sync.out_pixel_fmt);\n \n \t\tipu_dc_use_count++;\n \t\tipu_dp_use_count++;\n@@ -644,12 +632,10 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n \t\tipu_conf |= IPU_CONF_DP_EN;\n \tif (ipu_dmfc_use_count == 1)\n \t\tipu_conf |= IPU_CONF_DMFC_EN;\n-\tif (ipu_di_use_count[0] == 1) {\n+\tif (ipu_di_use_count[0] == 1)\n \t\tipu_conf |= IPU_CONF_DI0_EN;\n-\t}\n-\tif (ipu_di_use_count[1] == 1) {\n+\tif (ipu_di_use_count[1] == 1)\n \t\tipu_conf |= IPU_CONF_DI1_EN;\n-\t}\n \n \t__raw_writel(ipu_conf, IPU_CONF);\n \n@@ -660,7 +646,7 @@ err:\n /*\n  * This function is called to uninitialize a logical IPU channel.\n  *\n- * @param       channel Input parameter for the logical channel ID to uninit.\n+ * @param\tchannel Input parameter for the logical channel ID to uninit.\n  */\n void ipu_uninit_channel(ipu_channel_t channel)\n {\n@@ -670,7 +656,7 @@ void ipu_uninit_channel(ipu_channel_t channel)\n \n \tif ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {\n \t\tdebug(\"Channel already uninitialized %d\\n\",\n-\t\t\tIPU_CHAN_ID(channel));\n+\t\t      IPU_CHAN_ID(channel));\n \t\treturn;\n \t}\n \n@@ -683,9 +669,8 @@ void ipu_uninit_channel(ipu_channel_t channel)\n \n \tif (idma_is_set(IDMAC_CHA_EN, in_dma) ||\n \t    idma_is_set(IDMAC_CHA_EN, out_dma)) {\n-\t\tprintf(\n-\t\t\t\"Channel %d is not disabled, disable first\\n\",\n-\t\t\tIPU_CHAN_ID(channel));\n+\t\tprintf(\"Channel %d is not disabled, disable first\\n\",\n+\t\t       IPU_CHAN_ID(channel));\n \t\treturn;\n \t}\n \n@@ -730,12 +715,10 @@ void ipu_uninit_channel(ipu_channel_t channel)\n \t\tipu_conf &= ~IPU_CONF_DP_EN;\n \tif (ipu_dmfc_use_count == 0)\n \t\tipu_conf &= ~IPU_CONF_DMFC_EN;\n-\tif (ipu_di_use_count[0] == 0) {\n+\tif (ipu_di_use_count[0] == 0)\n \t\tipu_conf &= ~IPU_CONF_DI0_EN;\n-\t}\n-\tif (ipu_di_use_count[1] == 0) {\n+\tif (ipu_di_use_count[1] == 0)\n \t\tipu_conf &= ~IPU_CONF_DI1_EN;\n-\t}\n \n \t__raw_writel(ipu_conf, IPU_CONF);\n \n@@ -743,7 +726,6 @@ void ipu_uninit_channel(ipu_channel_t channel)\n \t\tclk_disable(g_ipu_clk);\n \t\tg_ipu_clk_enabled = 0;\n \t}\n-\n }\n \n static inline void ipu_ch_param_dump(int ch)\n@@ -751,49 +733,49 @@ static inline void ipu_ch_param_dump(int ch)\n #ifdef DEBUG\n \tstruct ipu_ch_param *p = ipu_ch_param_addr(ch);\n \tdebug(\"ch %d word 0 - %08X %08X %08X %08X %08X\\n\", ch,\n-\t\t p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],\n-\t\t p->word[0].data[3], p->word[0].data[4]);\n+\t      p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],\n+\t      p->word[0].data[3], p->word[0].data[4]);\n \tdebug(\"ch %d word 1 - %08X %08X %08X %08X %08X\\n\", ch,\n-\t\t p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],\n-\t\t p->word[1].data[3], p->word[1].data[4]);\n+\t      p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],\n+\t      p->word[1].data[3], p->word[1].data[4]);\n \tdebug(\"PFS 0x%x, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));\n \tdebug(\"BPP 0x%x, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));\n \tdebug(\"NPB 0x%x\\n\",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));\n \n \tdebug(\"FW %d, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));\n \tdebug(\"FH %d, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));\n \tdebug(\"Stride %d\\n\",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));\n \n \tdebug(\"Width0 %d+1, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));\n \tdebug(\"Width1 %d+1, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));\n \tdebug(\"Width2 %d+1, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));\n \tdebug(\"Width3 %d+1, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));\n \tdebug(\"Offset0 %d, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));\n \tdebug(\"Offset1 %d, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));\n \tdebug(\"Offset2 %d, \",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));\n \tdebug(\"Offset3 %d\\n\",\n-\t\t ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));\n+\t      ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));\n #endif\n }\n \n static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,\n-\t\t\t\t\t      int red_width, int red_offset,\n-\t\t\t\t\t      int green_width, int green_offset,\n-\t\t\t\t\t      int blue_width, int blue_offset,\n-\t\t\t\t\t      int alpha_width, int alpha_offset)\n+\t\t\t\t\t     int red_width, int red_offset,\n+\t\t\t\t\t     int green_width, int green_offset,\n+\t\t\t\t\t     int blue_width, int blue_offset,\n+\t\t\t\t\t     int alpha_width, int alpha_offset)\n {\n \t/* Setup red width and offset */\n \tipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);\n@@ -809,11 +791,9 @@ static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,\n \tipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);\n }\n \n-static void ipu_ch_param_init(int ch,\n-\t\t\t      uint32_t pixel_fmt, uint32_t width,\n-\t\t\t      uint32_t height, uint32_t stride,\n-\t\t\t      uint32_t u, uint32_t v,\n-\t\t\t      uint32_t uv_stride, dma_addr_t addr0,\n+static void ipu_ch_param_init(int ch, uint32_t pixel_fmt, uint32_t width,\n+\t\t\t      uint32_t height, uint32_t stride, uint32_t u,\n+\t\t\t      uint32_t v, uint32_t uv_stride, dma_addr_t addr0,\n \t\t\t      dma_addr_t addr1)\n {\n \tuint32_t u_offset = 0;\n@@ -838,71 +818,71 @@ static void ipu_ch_param_init(int ch,\n \tswitch (pixel_fmt) {\n \tcase IPU_PIX_FMT_GENERIC:\n \t\t/*Represents 8-bit Generic data */\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 5);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 6);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 63);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 5); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */\n \n \t\tbreak;\n \tcase IPU_PIX_FMT_GENERIC_32:\n \t\t/*Represents 32-bit Generic data */\n \t\tbreak;\n \tcase IPU_PIX_FMT_RGB565:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */\n \n \t\tipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);\n \t\tbreak;\n \tcase IPU_PIX_FMT_BGR24:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 1);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 19);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */\n \n \t\tipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);\n \t\tbreak;\n \tcase IPU_PIX_FMT_RGB24:\n \tcase IPU_PIX_FMT_YUV444:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 1);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 19);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */\n \n \t\tipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);\n \t\tbreak;\n \tcase IPU_PIX_FMT_BGRA32:\n \tcase IPU_PIX_FMT_BGR32:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */\n \n \t\tipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);\n \t\tbreak;\n \tcase IPU_PIX_FMT_RGBA32:\n \tcase IPU_PIX_FMT_RGB32:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */\n \n \t\tipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);\n \t\tbreak;\n \tcase IPU_PIX_FMT_ABGR32:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7);\t/* pix format */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */\n \n \t\tipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);\n \t\tbreak;\n \tcase IPU_PIX_FMT_UYVY:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 0xA);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */\n \t\tbreak;\n \tcase IPU_PIX_FMT_YUYV:\n-\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3);\t/* bits/pixel */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 0x8);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */\n \t\tbreak;\n \tcase IPU_PIX_FMT_YUV420P2:\n \tcase IPU_PIX_FMT_YUV420P:\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 2);\t/* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */\n \n \t\tif (uv_stride < stride / 2)\n \t\t\tuv_stride = stride / 2;\n@@ -912,15 +892,15 @@ static void ipu_ch_param_init(int ch,\n \t\t/* burst size */\n \t\tif ((ch == 8) || (ch == 9) || (ch == 10)) {\n \t\t\tipu_ch_param_set_field(&params, 1, 78, 7, 15);\n-\t\t\tuv_stride = uv_stride*2;\n+\t\t\tuv_stride = uv_stride * 2;\n \t\t} else {\n \t\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31);\n \t\t}\n \t\tbreak;\n \tcase IPU_PIX_FMT_YVU422P:\n \t\t/* BPP & pixel format */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 1);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */\n \n \t\tif (uv_stride < stride / 2)\n \t\t\tuv_stride = stride / 2;\n@@ -930,8 +910,8 @@ static void ipu_ch_param_init(int ch,\n \t\tbreak;\n \tcase IPU_PIX_FMT_YUV422P:\n \t\t/* BPP & pixel format */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 1);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */\n \n \t\tif (uv_stride < stride / 2)\n \t\t\tuv_stride = stride / 2;\n@@ -941,8 +921,8 @@ static void ipu_ch_param_init(int ch,\n \t\tbreak;\n \tcase IPU_PIX_FMT_NV12:\n \t\t/* BPP & pixel format */\n-\t\tipu_ch_param_set_field(&params, 1, 85, 4, 4);\t/* pix format */\n-\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31);\t/* burst size */\n+\t\tipu_ch_param_set_field(&params, 1, 85, 4, 4); /* pix format */\n+\t\tipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */\n \t\tuv_stride = stride;\n \t\tu_offset = (u == 0) ? stride * height : u;\n \t\tbreak;\n@@ -961,9 +941,9 @@ static void ipu_ch_param_init(int ch,\n \t}\n \n \t/* UBO and VBO are 22-bit */\n-\tif (u_offset/8 > 0x3fffff)\n+\tif (u_offset / 8 > 0x3fffff)\n \t\tputs(\"The value of U offset exceeds IPU limitation\\n\");\n-\tif (v_offset/8 > 0x3fffff)\n+\tif (v_offset / 8 > 0x3fffff)\n \t\tputs(\"The value of V offset exceeds IPU limitation\\n\");\n \n \tipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);\n@@ -976,38 +956,37 @@ static void ipu_ch_param_init(int ch,\n /*\n  * This function is called to initialize a buffer for logical IPU channel.\n  *\n- * @param       channel         Input parameter for the logical channel ID.\n+ * @param\tchannel\t\tInput parameter for the logical channel ID.\n  *\n- * @param       type            Input parameter which buffer to initialize.\n+ * @param\ttype\t\tInput parameter which buffer to initialize.\n  *\n- * @param       pixel_fmt       Input parameter for pixel format of buffer.\n- *                              Pixel format is a FOURCC ASCII code.\n+ * @param\tpixel_fmt\tInput parameter for pixel format of buffer.\n+ *\t\t\t\tPixel format is a FOURCC ASCII code.\n  *\n- * @param       width           Input parameter for width of buffer in pixels.\n+ * @param\twidth\t\tInput parameter for width of buffer in pixels.\n  *\n- * @param       height          Input parameter for height of buffer in pixels.\n+ * @param\theight\t\tInput parameter for height of buffer in pixels.\n  *\n- * @param       stride          Input parameter for stride length of buffer\n- *                              in pixels.\n+ * @param\tstride\t\tInput parameter for stride length of buffer\n+ *\t\t\t\tin pixels.\n  *\n- * @param       phyaddr_0       Input parameter buffer 0 physical address.\n+ * @param\tphyaddr_0\tInput parameter buffer 0 physical address.\n  *\n- * @param       phyaddr_1       Input parameter buffer 1 physical address.\n- *                              Setting this to a value other than NULL enables\n- *                              double buffering mode.\n+ * @param\tphyaddr_1\tInput parameter buffer 1 physical address.\n+ *\t\t\t\tSetting this to a value other than NULL enables\n+ *\t\t\t\tdouble buffering mode.\n  *\n- * @param       u\t\tprivate u offset for additional cropping,\n+ * @param\tu\t\tprivate u offset for additional cropping,\n  *\t\t\t\tzero if not used.\n  *\n- * @param       v\t\tprivate v offset for additional cropping,\n+ * @param\tv\t\tprivate v offset for additional cropping,\n  *\t\t\t\tzero if not used.\n  *\n- * Return:      Returns 0 on success or negative error code on fail\n+ * Return:\tReturns 0 on success or negative error code on fail\n  */\n int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t\tuint32_t pixel_fmt,\n-\t\t\t\tuint16_t width, uint16_t height,\n-\t\t\t\tuint32_t stride,\n+\t\t\t\tuint32_t pixel_fmt, uint16_t width,\n+\t\t\t\tuint16_t height, uint32_t stride,\n \t\t\t\tdma_addr_t phyaddr_0, dma_addr_t phyaddr_1,\n \t\t\t\tuint32_t u, uint32_t v)\n {\n@@ -1022,17 +1001,15 @@ int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n \t\tstride = width * bytes_per_pixel(pixel_fmt);\n \n \tif (stride % 4) {\n-\t\tprintf(\n-\t\t\t\"Stride not 32-bit aligned, stride = %d\\n\", stride);\n+\t\tprintf(\"Stride not 32-bit aligned, stride = %d\\n\", stride);\n \t\treturn -EINVAL;\n \t}\n \t/* Build parameter memory data for DMA channel */\n \tipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,\n-\t\t\t   phyaddr_0, phyaddr_1);\n+\t\t\t  phyaddr_0, phyaddr_1);\n \n-\tif (ipu_is_dmfc_chan(dma_chan)) {\n+\tif (ipu_is_dmfc_chan(dma_chan))\n \t\tipu_dmfc_set_wait4eot(dma_chan, width);\n-\t}\n \n \tif (idma_is_set(IDMAC_CHA_PRI, dma_chan))\n \t\tipu_ch_param_set_high_priority(dma_chan);\n@@ -1055,10 +1032,10 @@ int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n /*\n  * This function enables a logical channel.\n  *\n- * @param       channel         Input parameter for the logical channel ID.\n+ * @param\tchannel\t\tInput parameter for the logical channel ID.\n  *\n- * Return:      This function returns 0 on success or negative error code on\n- *              fail.\n+ * Return:\tThis function returns 0 on success or negative error code on\n+ *\t\tfail.\n  */\n int32_t ipu_enable_channel(ipu_channel_t channel)\n {\n@@ -1068,7 +1045,7 @@ int32_t ipu_enable_channel(ipu_channel_t channel)\n \n \tif (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {\n \t\tprintf(\"Warning: channel already enabled %d\\n\",\n-\t\t\tIPU_CHAN_ID(channel));\n+\t\t       IPU_CHAN_ID(channel));\n \t}\n \n \t/* Get input and output dma channels */\n@@ -1096,16 +1073,16 @@ int32_t ipu_enable_channel(ipu_channel_t channel)\n /*\n  * This function clear buffer ready for a logical channel.\n  *\n- * @param       channel         Input parameter for the logical channel ID.\n+ * @param\tchannel\t\tInput parameter for the logical channel ID.\n  *\n- * @param       type            Input parameter which buffer to clear.\n+ * @param\ttype\t\tInput parameter which buffer to clear.\n  *\n- * @param       bufNum          Input parameter for which buffer number clear\n+ * @param\tbufNum\t\tInput parameter for which buffer number clear\n  *\t\t\t\tready state.\n  *\n  */\n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\tuint32_t bufNum)\n+\t\t\t    uint32_t bufNum)\n {\n \tuint32_t dma_ch = channel_2_dma(channel, type);\n \n@@ -1116,13 +1093,10 @@ void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n \tif (bufNum == 0) {\n \t\tif (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {\n \t\t\t__raw_writel(idma_mask(dma_ch),\n-\t\t\t\t\tIPU_CHA_BUF0_RDY(dma_ch));\n-\t\t}\n-\t} else {\n-\t\tif (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {\n-\t\t\t__raw_writel(idma_mask(dma_ch),\n-\t\t\t\t\tIPU_CHA_BUF1_RDY(dma_ch));\n+\t\t\t\t     IPU_CHA_BUF0_RDY(dma_ch));\n \t\t}\n+\t} else if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {\n+\t\t__raw_writel(idma_mask(dma_ch), IPU_CHA_BUF1_RDY(dma_ch));\n \t}\n \t__raw_writel(0x0, IPU_GPR); /* write one to set */\n }\n@@ -1130,13 +1104,13 @@ void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n /*\n  * This function disables a logical channel.\n  *\n- * @param       channel         Input parameter for the logical channel ID.\n+ * @param\tchannel\t\tInput parameter for the logical channel ID.\n  *\n- * @param       wait_for_stop   Flag to set whether to wait for channel end\n- *                              of frame or return immediately.\n+ * @param\twait_for_stop\tFlag to set whether to wait for channel end\n+ *\t\t\t\tof frame or return immediately.\n  *\n- * Return:      This function returns 0 on success or negative error code on\n- *              fail.\n+ * Return:\tThis function returns 0 on success or negative error code on\n+ *\t\tfail.\n  */\n int32_t ipu_disable_channel(ipu_channel_t channel)\n {\n@@ -1145,8 +1119,7 @@ int32_t ipu_disable_channel(ipu_channel_t channel)\n \tuint32_t out_dma;\n \n \tif ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {\n-\t\tdebug(\"Channel already disabled %d\\n\",\n-\t\t\tIPU_CHAN_ID(channel));\n+\t\tdebug(\"Channel already disabled %d\\n\", IPU_CHAN_ID(channel));\n \t\treturn 0;\n \t}\n \n@@ -1154,10 +1127,8 @@ int32_t ipu_disable_channel(ipu_channel_t channel)\n \tout_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);\n \tin_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);\n \n-\tif ((idma_is_valid(in_dma) &&\n-\t\t!idma_is_set(IDMAC_CHA_EN, in_dma))\n-\t\t&& (idma_is_valid(out_dma) &&\n-\t\t!idma_is_set(IDMAC_CHA_EN, out_dma)))\n+\tif ((idma_is_valid(in_dma) && !idma_is_set(IDMAC_CHA_EN, in_dma)) &&\n+\t    (idma_is_valid(out_dma) && !idma_is_set(IDMAC_CHA_EN, out_dma)))\n \t\treturn -EINVAL;\n \n \tif ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||\n@@ -1195,7 +1166,7 @@ int32_t ipu_disable_channel(ipu_channel_t channel)\n uint32_t bytes_per_pixel(uint32_t fmt)\n {\n \tswitch (fmt) {\n-\tcase IPU_PIX_FMT_GENERIC:\t/*generic data */\n+\tcase IPU_PIX_FMT_GENERIC: /*generic data */\n \tcase IPU_PIX_FMT_RGB332:\n \tcase IPU_PIX_FMT_YUV420P:\n \tcase IPU_PIX_FMT_YUV422P:\n@@ -1210,7 +1181,7 @@ uint32_t bytes_per_pixel(uint32_t fmt)\n \tcase IPU_PIX_FMT_RGB24:\n \t\treturn 3;\n \t\tbreak;\n-\tcase IPU_PIX_FMT_GENERIC_32:\t/*generic data */\n+\tcase IPU_PIX_FMT_GENERIC_32: /*generic data */\n \tcase IPU_PIX_FMT_BGR32:\n \tcase IPU_PIX_FMT_BGRA32:\n \tcase IPU_PIX_FMT_RGB32:\ndiff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c\nindex aaba7d135a4..178442a2bca 100644\n--- a/drivers/video/imx/ipu_disp.c\n+++ b/drivers/video/imx/ipu_disp.c\n@@ -12,24 +12,17 @@\n \n /* #define DEBUG */\n \n-#include <log.h>\n-#include <linux/delay.h>\n-#include <linux/types.h>\n-#include <linux/errno.h>\n-#include <asm/io.h>\n-#include <asm/arch/imx-regs.h>\n-#include <asm/arch/sys_proto.h>\n #include \"ipu.h\"\n #include \"ipu_regs.h\"\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/io.h>\n+#include <linux/delay.h>\n+#include <linux/errno.h>\n+#include <linux/types.h>\n+#include <log.h>\n \n-enum csc_type_t {\n-\tRGB2YUV = 0,\n-\tYUV2RGB,\n-\tRGB2RGB,\n-\tYUV2YUV,\n-\tCSC_NONE,\n-\tCSC_NUM\n-};\n+enum csc_type_t { RGB2YUV = 0, YUV2RGB, RGB2RGB, YUV2YUV, CSC_NONE, CSC_NUM };\n \n struct dp_csc_param_t {\n \tint mode;\n@@ -39,9 +32,9 @@ struct dp_csc_param_t {\n #define SYNC_WAVE 0\n \n /* DC display ID assignments */\n-#define DC_DISP_ID_SYNC(di)\t(di)\n-#define DC_DISP_ID_SERIAL\t2\n-#define DC_DISP_ID_ASYNC\t3\n+#define DC_DISP_ID_SYNC(di) (di)\n+#define DC_DISP_ID_SERIAL 2\n+#define DC_DISP_ID_ASYNC 3\n \n int dmfc_type_setup;\n static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;\n@@ -177,18 +170,17 @@ void ipu_dmfc_set_wait4eot(int dma_chan, int width)\n \t__raw_writel(dmfc_gen1, DMFC_GENERAL1);\n }\n \n-static void ipu_di_data_wave_config(int di,\n-\t\t\t\t     int wave_gen,\n-\t\t\t\t     int access_size, int component_size)\n+static void ipu_di_data_wave_config(int di, int wave_gen, int access_size,\n+\t\t\t\t    int component_size)\n {\n \tu32 reg;\n \treg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |\n-\t    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);\n+\t      (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);\n \t__raw_writel(reg, DI_DW_GEN(di, wave_gen));\n }\n \n static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,\n-\t\t\t\t    int up, int down)\n+\t\t\t\t   int up, int down)\n {\n \tu32 reg;\n \n@@ -200,29 +192,29 @@ static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,\n \t__raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));\n }\n \n-static void ipu_di_sync_config(int di, int wave_gen,\n-\t\t\t\tint run_count, int run_src,\n-\t\t\t\tint offset_count, int offset_src,\n-\t\t\t\tint repeat_count, int cnt_clr_src,\n-\t\t\t\tint cnt_polarity_gen_en,\n-\t\t\t\tint cnt_polarity_clr_src,\n-\t\t\t\tint cnt_polarity_trigger_src,\n-\t\t\t\tint cnt_up, int cnt_down)\n+static void ipu_di_sync_config(int di, int wave_gen, int run_count, int run_src,\n+\t\t\t       int offset_count, int offset_src,\n+\t\t\t       int repeat_count, int cnt_clr_src,\n+\t\t\t       int cnt_polarity_gen_en,\n+\t\t\t       int cnt_polarity_clr_src,\n+\t\t\t       int cnt_polarity_trigger_src, int cnt_up,\n+\t\t\t       int cnt_down)\n {\n \tu32 reg;\n \n \tif ((run_count >= 0x1000) || (offset_count >= 0x1000) ||\n-\t\t(repeat_count >= 0x1000) ||\n-\t\t(cnt_up >= 0x400) || (cnt_down >= 0x400)) {\n+\t    (repeat_count >= 0x1000) || (cnt_up >= 0x400) ||\n+\t    (cnt_down >= 0x400)) {\n \t\tprintf(\"DI%d counters out of range.\\n\", di);\n \t\treturn;\n \t}\n \n-\treg = (run_count << 19) | (++run_src << 16) |\n-\t    (offset_count << 3) | ++offset_src;\n+\treg = (run_count << 19) | (++run_src << 16) | (offset_count << 3) |\n+\t      ++offset_src;\n \t__raw_writel(reg, DI_SW_GEN0(di, wave_gen));\n \treg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |\n-\t    (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);\n+\t      (++cnt_polarity_trigger_src << 12) |\n+\t      (++cnt_polarity_clr_src << 9);\n \treg |= (cnt_down << 16) | cnt_up;\n \tif (repeat_count == 0) {\n \t\t/* Enable auto reload */\n@@ -259,7 +251,7 @@ static void ipu_dc_map_clear(int map)\n }\n \n static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,\n-\t\t\t       int wave, int glue, int sync)\n+\t\t\t      int wave, int glue, int sync)\n {\n \tu32 reg;\n \tint stop = 1;\n@@ -292,11 +284,9 @@ static void ipu_dc_link_event(int chan, int event, int addr, int priority)\n  * V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;\n  */\n static const int rgb2ycbcr_coeff[5][3] = {\n-\t{0x4D, 0x96, 0x1D},\n-\t{0x3D5, 0x3AB, 0x80},\n-\t{0x80, 0x395, 0x3EB},\n-\t{0x0000, 0x0200, 0x0200},\t/* B0, B1, B2 */\n-\t{0x2, 0x2, 0x2},\t/* S0, S1, S2 */\n+\t{ 0x4D, 0x96, 0x1D },\t{ 0x3D5, 0x3AB, 0x80 },\n+\t{ 0x80, 0x395, 0x3EB }, { 0x0000, 0x0200, 0x0200 }, /* B0, B1, B2 */\n+\t{ 0x2, 0x2, 0x2 }, /* S0, S1, S2 */\n };\n \n /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));\n@@ -304,11 +294,9 @@ static const int rgb2ycbcr_coeff[5][3] = {\n  * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);\n  */\n static const int ycbcr2rgb_coeff[5][3] = {\n-\t{0x095, 0x000, 0x0CC},\n-\t{0x095, 0x3CE, 0x398},\n-\t{0x095, 0x0FF, 0x000},\n-\t{0x3E42, 0x010A, 0x3DD6},\t/*B0,B1,B2 */\n-\t{0x1, 0x1, 0x1},\t/*S0,S1,S2 */\n+\t{ 0x095, 0x000, 0x0CC }, { 0x095, 0x3CE, 0x398 },\n+\t{ 0x095, 0x0FF, 0x000 }, { 0x3E42, 0x010A, 0x3DD6 }, /*B0,B1,B2 */\n+\t{ 0x1, 0x1, 0x1 }, /*S0,S1,S2 */\n };\n \n #define mask_a(a) ((u32)(a) & 0x3FF)\n@@ -337,48 +325,38 @@ static int rgb_to_yuv(int n, int red, int green, int blue)\n  * Column is for FG:\tRGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE\n  */\n static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {\n-\t{\n-\t\t{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},\n-\t\t{0, 0},\n-\t\t{0, 0},\n-\t\t{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},\n-\t\t{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}\n-\t},\n-\t{\n-\t\t{0, 0},\n-\t\t{DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},\n-\t\t{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},\n-\t\t{0, 0},\n-\t\t{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}\n-\t},\n-\t{\n-\t\t{0, 0},\n-\t\t{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},\n-\t\t{0, 0},\n-\t\t{0, 0},\n-\t\t{0, 0}\n-\t},\n-\t{\n-\t\t{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},\n-\t\t{0, 0},\n-\t\t{0, 0},\n-\t\t{0, 0},\n-\t\t{0, 0}\n-\t},\n-\t{\n-\t\t{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},\n-\t\t{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},\n-\t\t{0, 0},\n-\t\t{0, 0},\n-\t\t{0, 0}\n-\t}\n+\t{ { DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff },\n+\t  { 0, 0 },\n+\t  { 0, 0 },\n+\t  { DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff },\n+\t  { DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff } },\n+\t{ { 0, 0 },\n+\t  { DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff },\n+\t  { DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff },\n+\t  { 0, 0 },\n+\t  { DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff } },\n+\t{ { 0, 0 },\n+\t  { DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff },\n+\t  { 0, 0 },\n+\t  { 0, 0 },\n+\t  { 0, 0 } },\n+\t{ { DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff },\n+\t  { 0, 0 },\n+\t  { 0, 0 },\n+\t  { 0, 0 },\n+\t  { 0, 0 } },\n+\t{ { DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff },\n+\t  { DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff },\n+\t  { 0, 0 },\n+\t  { 0, 0 },\n+\t  { 0, 0 } }\n };\n \n static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;\n static int color_key_4rgb = 1;\n \n static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,\n-\t\t\tunsigned char srm_mode_update)\n+\t\t\t     unsigned char srm_mode_update)\n {\n \tu32 reg;\n \tconst int (*coeff)[5][3];\n@@ -394,19 +372,25 @@ static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,\n \n \tif (coeff) {\n \t\t__raw_writel(mask_a((*coeff)[0][0]) |\n-\t\t\t\t(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());\n+\t\t\t\t     (mask_a((*coeff)[0][1]) << 16),\n+\t\t\t     DP_CSC_A_0());\n \t\t__raw_writel(mask_a((*coeff)[0][2]) |\n-\t\t\t\t(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());\n+\t\t\t\t     (mask_a((*coeff)[1][0]) << 16),\n+\t\t\t     DP_CSC_A_1());\n \t\t__raw_writel(mask_a((*coeff)[1][1]) |\n-\t\t\t\t(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());\n+\t\t\t\t     (mask_a((*coeff)[1][2]) << 16),\n+\t\t\t     DP_CSC_A_2());\n \t\t__raw_writel(mask_a((*coeff)[2][0]) |\n-\t\t\t\t(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());\n+\t\t\t\t     (mask_a((*coeff)[2][1]) << 16),\n+\t\t\t     DP_CSC_A_3());\n \t\t__raw_writel(mask_a((*coeff)[2][2]) |\n-\t\t\t\t(mask_b((*coeff)[3][0]) << 16) |\n-\t\t\t\t((*coeff)[4][0] << 30), DP_CSC_0());\n+\t\t\t\t     (mask_b((*coeff)[3][0]) << 16) |\n+\t\t\t\t     ((*coeff)[4][0] << 30),\n+\t\t\t     DP_CSC_0());\n \t\t__raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |\n-\t\t\t\t(mask_b((*coeff)[3][2]) << 16) |\n-\t\t\t\t((*coeff)[4][2] << 30), DP_CSC_1());\n+\t\t\t\t     (mask_b((*coeff)[3][2]) << 16) |\n+\t\t\t\t     ((*coeff)[4][2] << 30),\n+\t\t\t     DP_CSC_1());\n \t}\n \n \tif (srm_mode_update) {\n@@ -416,7 +400,7 @@ static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,\n }\n \n int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n-\t\t uint32_t out_pixel_fmt)\n+\t\tuint32_t out_pixel_fmt)\n {\n \tint in_fmt, out_fmt;\n \tint dp;\n@@ -440,45 +424,41 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n \tout_fmt = format_to_colorspace(out_pixel_fmt);\n \n \tif (partial) {\n-\t\tif (in_fmt == RGB) {\n+\t\tif (in_fmt == RGB)\n \t\t\tif (out_fmt == RGB)\n \t\t\t\tfg_csc_type = RGB2RGB;\n \t\t\telse\n \t\t\t\tfg_csc_type = RGB2YUV;\n-\t\t} else {\n-\t\t\tif (out_fmt == RGB)\n-\t\t\t\tfg_csc_type = YUV2RGB;\n-\t\t\telse\n-\t\t\t\tfg_csc_type = YUV2YUV;\n-\t\t}\n+\t\telse if (out_fmt == RGB)\n+\t\t\tfg_csc_type = YUV2RGB;\n+\t\telse\n+\t\t\tfg_csc_type = YUV2YUV;\n \t} else {\n-\t\tif (in_fmt == RGB) {\n+\t\tif (in_fmt == RGB)\n \t\t\tif (out_fmt == RGB)\n \t\t\t\tbg_csc_type = RGB2RGB;\n \t\t\telse\n \t\t\t\tbg_csc_type = RGB2YUV;\n-\t\t} else {\n-\t\t\tif (out_fmt == RGB)\n-\t\t\t\tbg_csc_type = YUV2RGB;\n-\t\t\telse\n-\t\t\t\tbg_csc_type = YUV2YUV;\n-\t\t}\n+\t\telse if (out_fmt == RGB)\n+\t\t\tbg_csc_type = YUV2RGB;\n+\t\telse\n+\t\t\tbg_csc_type = YUV2YUV;\n \t}\n \n \t/* Transform color key from rgb to yuv if CSC is enabled */\n \treg = __raw_readl(DP_COM_CONF());\n \tif (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&\n-\t\t(((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||\n-\t\t((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||\n-\t\t((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||\n-\t\t((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {\n+\t    (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||\n+\t     ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||\n+\t     ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||\n+\t     ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {\n \t\tint red, green, blue;\n \t\tint y, u, v;\n \t\tuint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &\n-\t\t\t0xFFFFFFL;\n+\t\t\t\t     0xFFFFFFL;\n \n \t\tdebug(\"_ipu_dp_init color key 0x%x need change to yuv fmt!\\n\",\n-\t\t\tcolor_key);\n+\t\t      color_key);\n \n \t\tred = (color_key >> 16) & 0xFF;\n \t\tgreen = (color_key >> 8) & 0xFF;\n@@ -494,7 +474,7 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n \t\tcolor_key_4rgb = 0;\n \n \t\tdebug(\"_ipu_dp_init color key change to yuv fmt 0x%x!\\n\",\n-\t\t\tcolor_key);\n+\t\t      color_key);\n \t}\n \n \tipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);\n@@ -537,18 +517,14 @@ void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)\n \t\t\tipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);\n \t\t\tipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);\n \t\t\tipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);\n+\t\t} else if (di) {\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 4, 1);\n \t\t} else {\n-\t\t\tif (di) {\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,\n-\t\t\t\t\t4, 1);\n-\t\t\t} else {\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);\n-\t\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,\n-\t\t\t\t\t7, 1);\n-\t\t\t}\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);\n+\t\t\tipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 7, 1);\n \t\t}\n \t\tipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);\n \t\tipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);\n@@ -685,16 +661,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)\n \t\t * this check is useful for tv overlay.\n \t\t */\n \t\tif (g_dc_di_assignment[dc_chan] == 0)\n-\t\t\twhile ((__raw_readl(DC_STAT) & 0x00000002)\n-\t\t\t       != 0x00000002) {\n+\t\t\twhile ((__raw_readl(DC_STAT) & 0x00000002) !=\n+\t\t\t       0x00000002) {\n \t\t\t\tudelay(2000);\n \t\t\t\ttimeout -= 2;\n \t\t\t\tif (timeout <= 0)\n \t\t\t\t\tbreak;\n \t\t\t}\n \t\telse if (g_dc_di_assignment[dc_chan] == 1)\n-\t\t\twhile ((__raw_readl(DC_STAT) & 0x00000020)\n-\t\t\t       != 0x00000020) {\n+\t\t\twhile ((__raw_readl(DC_STAT) & 0x00000020) !=\n+\t\t\t       0x00000020) {\n \t\t\t\tudelay(2000);\n \t\t\t\ttimeout -= 2;\n \t\t\t\tif (timeout <= 0)\n@@ -791,43 +767,42 @@ static int ipu_pixfmt_to_map(uint32_t fmt)\n /*\n  * This function is called to initialize a synchronous LCD panel.\n  *\n- * @param       disp            The DI the panel is attached to.\n+ * @param\tdisp\t\tThe DI the panel is attached to.\n  *\n- * @param       pixel_clk       Desired pixel clock frequency in Hz.\n+ * @param\tpixel_clk\tDesired pixel clock frequency in Hz.\n  *\n- * @param       pixel_fmt       Input parameter for pixel format of buffer.\n- *                              Pixel format is a FOURCC ASCII code.\n+ * @param\tpixel_fmt\tInput parameter for pixel format of buffer.\n+ *\t\t\t\tPixel format is a FOURCC ASCII code.\n  *\n- * @param       width           The width of panel in pixels.\n+ * @param\twidth\t\tThe width of panel in pixels.\n  *\n- * @param       height          The height of panel in pixels.\n+ * @param\theight\t\tThe height of panel in pixels.\n  *\n- * @param       hStartWidth     The number of pixel clocks between the HSYNC\n- *                              signal pulse and the start of valid data.\n+ * @param\thStartWidth\tThe number of pixel clocks between the HSYNC\n+ *\t\t\t\tsignal pulse and the start of valid data.\n  *\n- * @param       hSyncWidth      The width of the HSYNC signal in units of pixel\n- *                              clocks.\n+ * @param\thSyncWidth\tThe width of the HSYNC signal in units of pixel\n+ *\t\t\t\tclocks.\n  *\n- * @param       hEndWidth       The number of pixel clocks between the end of\n- *                              valid data and the HSYNC signal for next line.\n+ * @param\thEndWidth\tThe number of pixel clocks between the end of\n+ *\t\t\t\tvalid data and the HSYNC signal for next line.\n  *\n- * @param       vStartWidth     The number of lines between the VSYNC\n- *                              signal pulse and the start of valid data.\n+ * @param\tvStartWidth\tThe number of lines between the VSYNC\n+ *\t\t\t\tsignal pulse and the start of valid data.\n  *\n- * @param       vSyncWidth      The width of the VSYNC signal in units of lines\n+ * @param\tvSyncWidth\tThe width of the VSYNC signal in units of lines\n  *\n- * @param       vEndWidth       The number of lines between the end of valid\n- *                              data and the VSYNC signal for next frame.\n+ * @param\tvEndWidth\tThe number of lines between the end of valid\n+ *\t\t\t\tdata and the VSYNC signal for next frame.\n  *\n- * @param       sig             Bitfield of signal polarities for LCD interface.\n+ * @param\tsig\t\tBitfield of signal polarities for LCD interface.\n  *\n- * Return:      This function returns 0 on success or negative error code on\n- *              fail.\n+ * Return:\tThis function returns 0 on success or negative error code on\n+ *\t\tfail.\n  */\n \n-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n-\t\t\t    uint16_t width, uint16_t height,\n-\t\t\t    uint32_t pixel_fmt,\n+int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,\n+\t\t\t    uint16_t height, uint32_t pixel_fmt,\n \t\t\t    uint16_t h_start_width, uint16_t h_sync_width,\n \t\t\t    uint16_t h_end_width, uint16_t v_start_width,\n \t\t\t    uint16_t v_sync_width, uint16_t v_end_width,\n@@ -864,22 +839,21 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \t\t\t * of the pixel clock.\n \t\t\t */\n \t\t\tif ((clk_get_usecount(g_pixel_clk[0]) == 0) &&\n-\t\t\t\t(clk_get_usecount(g_pixel_clk[1]) == 0)) {\n+\t\t\t    (clk_get_usecount(g_pixel_clk[1]) == 0)) {\n \t\t\t\tdi_parent = clk_get_parent(g_di_clk[disp]);\n-\t\t\t\trounded_pixel_clk =\n-\t\t\t\t\tclk_round_rate(g_pixel_clk[disp],\n-\t\t\t\t\t\tpixel_clk);\n-\t\t\t\tdiv  = clk_get_rate(di_parent) /\n-\t\t\t\t\trounded_pixel_clk;\n+\t\t\t\trounded_pixel_clk = clk_round_rate(\n+\t\t\t\t\tg_pixel_clk[disp], pixel_clk);\n+\t\t\t\tdiv = clk_get_rate(di_parent) /\n+\t\t\t\t      rounded_pixel_clk;\n \t\t\t\tif (div % 2)\n \t\t\t\t\tdiv++;\n-\t\t\t\tif (clk_get_rate(di_parent) != div *\n-\t\t\t\t\trounded_pixel_clk)\n+\t\t\t\tif (clk_get_rate(di_parent) !=\n+\t\t\t\t    div * rounded_pixel_clk)\n \t\t\t\t\tclk_set_rate(di_parent,\n-\t\t\t\t\t\tdiv * rounded_pixel_clk);\n+\t\t\t\t\t\t     div * rounded_pixel_clk);\n \t\t\t\tudelay(10000);\n \t\t\t\tclk_set_rate(g_di_clk[disp],\n-\t\t\t\t\t2 * rounded_pixel_clk);\n+\t\t\t\t\t     2 * rounded_pixel_clk);\n \t\t\t\tudelay(10000);\n \t\t\t}\n \t\t}\n@@ -893,7 +867,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \tudelay(5000);\n \t/* Get integer portion of divider */\n \tdiv = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /\n-\t\trounded_pixel_clk;\n+\t      rounded_pixel_clk;\n \n \tipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);\n \tipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);\n@@ -908,162 +882,153 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \n \tif (sig.interlaced) {\n \t\t/* Setup internal HSYNC waveform */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t1,\t\t/* counter */\n-\t\t\t\th_total / 2 - 1,/* run count */\n-\t\t\t\tDI_SYNC_CLK,\t/* run_resolution */\n-\t\t\t\t0,\t\t/* offset */\n-\t\t\t\tDI_SYNC_NONE,\t/* offset resolution */\n-\t\t\t\t0,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   1, /* counter */\n+\t\t\t\t   h_total / 2 - 1, /* run count */\n+\t\t\t\t   DI_SYNC_CLK, /* run_resolution */\n+\t\t\t\t   0, /* offset */\n+\t\t\t\t   DI_SYNC_NONE, /* offset resolution */\n+\t\t\t\t   0, /* repeat count */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* Field 1 VSYNC waveform */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t2,\t\t/* counter */\n-\t\t\t\th_total - 1,\t/* run count */\n-\t\t\t\tDI_SYNC_CLK,\t/* run_resolution */\n-\t\t\t\t0,\t\t/* offset */\n-\t\t\t\tDI_SYNC_NONE,\t/* offset resolution */\n-\t\t\t\t0,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t4\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   2, /* counter */\n+\t\t\t\t   h_total - 1, /* run count */\n+\t\t\t\t   DI_SYNC_CLK, /* run_resolution */\n+\t\t\t\t   0, /* offset */\n+\t\t\t\t   DI_SYNC_NONE, /* offset resolution */\n+\t\t\t\t   0, /* repeat count */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   4 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* Setup internal HSYNC waveform */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t3,\t\t/* counter */\n-\t\t\t\tv_total * 2 - 1,/* run count */\n-\t\t\t\tDI_SYNC_INT_HSYNC,\t/* run_resolution */\n-\t\t\t\t1,\t\t/* offset */\n-\t\t\t\tDI_SYNC_INT_HSYNC,\t/* offset resolution */\n-\t\t\t\t0,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t4\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   3, /* counter */\n+\t\t\t\t   v_total * 2 - 1, /* run count */\n+\t\t\t\t   DI_SYNC_INT_HSYNC, /* run_resolution */\n+\t\t\t\t   1, /* offset */\n+\t\t\t\t   DI_SYNC_INT_HSYNC, /* offset resolution */\n+\t\t\t\t   0, /* repeat count */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   4 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* Active Field ? */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t4,\t\t/* counter */\n-\t\t\t\tv_total / 2 - 1,/* run count */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* run_resolution */\n-\t\t\t\tv_start_width,\t/*  offset */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* offset resolution */\n-\t\t\t\t2,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_VSYNC,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   4, /* counter */\n+\t\t\t\t   v_total / 2 - 1, /* run count */\n+\t\t\t\t   DI_SYNC_HSYNC, /* run_resolution */\n+\t\t\t\t   v_start_width, /*  offset */\n+\t\t\t\t   DI_SYNC_HSYNC, /* offset resolution */\n+\t\t\t\t   2, /* repeat count */\n+\t\t\t\t   DI_SYNC_VSYNC, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* Active Line */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t5,\t\t/* counter */\n-\t\t\t\t0,\t\t/* run count */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* run_resolution */\n-\t\t\t\t0,\t\t/*  offset */\n-\t\t\t\tDI_SYNC_NONE,\t/* offset resolution */\n-\t\t\t\theight / 2,\t/* repeat count */\n-\t\t\t\t4,\t\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   5, /* counter */\n+\t\t\t\t   0, /* run count */\n+\t\t\t\t   DI_SYNC_HSYNC, /* run_resolution */\n+\t\t\t\t   0, /*  offset */\n+\t\t\t\t   DI_SYNC_NONE, /* offset resolution */\n+\t\t\t\t   height / 2, /* repeat count */\n+\t\t\t\t   4, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* Field 0 VSYNC waveform */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t6,\t\t/* counter */\n-\t\t\t\tv_total - 1,\t/* run count */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* run_resolution */\n-\t\t\t\t0,\t\t/* offset */\n-\t\t\t\tDI_SYNC_NONE,\t/* offset resolution */\n-\t\t\t\t0,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_CLR_SEL  */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   6, /* counter */\n+\t\t\t\t   v_total - 1, /* run count */\n+\t\t\t\t   DI_SYNC_HSYNC, /* run_resolution */\n+\t\t\t\t   0, /* offset */\n+\t\t\t\t   DI_SYNC_NONE, /* offset resolution */\n+\t\t\t\t   0, /* repeat count */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_CLR_SEL  */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* DC VSYNC waveform */\n \t\tvsync_cnt = 7;\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t7,\t\t/* counter */\n-\t\t\t\tv_total / 2 - 1,/* run count */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* run_resolution  */\n-\t\t\t\t9,\t\t/* offset  */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* offset resolution */\n-\t\t\t\t2,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_VSYNC,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   7, /* counter */\n+\t\t\t\t   v_total / 2 - 1, /* run count */\n+\t\t\t\t   DI_SYNC_HSYNC, /* run_resolution  */\n+\t\t\t\t   9, /* offset  */\n+\t\t\t\t   DI_SYNC_HSYNC, /* offset resolution */\n+\t\t\t\t   2, /* repeat count */\n+\t\t\t\t   DI_SYNC_VSYNC, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* active pixel waveform */\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t8,\t\t/* counter */\n-\t\t\t\t0,\t\t/* run count  */\n-\t\t\t\tDI_SYNC_CLK,\t/* run_resolution */\n-\t\t\t\th_start_width,\t/* offset  */\n-\t\t\t\tDI_SYNC_CLK,\t/* offset resolution */\n-\t\t\t\twidth,\t\t/* repeat count  */\n-\t\t\t\t5,\t\t/* CNT_CLR_SEL  */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN  */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL  */\n-\t\t\t\t0,\t\t/* COUNT UP  */\n-\t\t\t\t0\t\t/* COUNT DOWN */\n-\t\t\t\t);\n-\n-\t\tipu_di_sync_config(\n-\t\t\t\tdisp,\t\t/* display */\n-\t\t\t\t9,\t\t/* counter */\n-\t\t\t\tv_total - 1,\t/* run count */\n-\t\t\t\tDI_SYNC_INT_HSYNC,/* run_resolution */\n-\t\t\t\tv_total / 2,\t/* offset  */\n-\t\t\t\tDI_SYNC_INT_HSYNC,/* offset resolution  */\n-\t\t\t\t0,\t\t/* repeat count */\n-\t\t\t\tDI_SYNC_HSYNC,\t/* CNT_CLR_SEL */\n-\t\t\t\t0,\t\t/* CNT_POLARITY_GEN_EN  */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_CLR_SEL  */\n-\t\t\t\tDI_SYNC_NONE,\t/* CNT_POLARITY_TRIGGER_SEL */\n-\t\t\t\t0,\t\t/* COUNT UP */\n-\t\t\t\t4\t\t/* COUNT DOWN */\n-\t\t\t\t);\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   8, /* counter */\n+\t\t\t\t   0, /* run count  */\n+\t\t\t\t   DI_SYNC_CLK, /* run_resolution */\n+\t\t\t\t   h_start_width, /* offset  */\n+\t\t\t\t   DI_SYNC_CLK, /* offset resolution */\n+\t\t\t\t   width, /* repeat count  */\n+\t\t\t\t   5, /* CNT_CLR_SEL  */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN  */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL  */\n+\t\t\t\t   0, /* COUNT UP  */\n+\t\t\t\t   0 /* COUNT DOWN */\n+\t\t);\n+\n+\t\tipu_di_sync_config(disp, /* display */\n+\t\t\t\t   9, /* counter */\n+\t\t\t\t   v_total - 1, /* run count */\n+\t\t\t\t   DI_SYNC_INT_HSYNC, /* run_resolution */\n+\t\t\t\t   v_total / 2, /* offset  */\n+\t\t\t\t   DI_SYNC_INT_HSYNC, /* offset resolution  */\n+\t\t\t\t   0, /* repeat count */\n+\t\t\t\t   DI_SYNC_HSYNC, /* CNT_CLR_SEL */\n+\t\t\t\t   0, /* CNT_POLARITY_GEN_EN  */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL  */\n+\t\t\t\t   DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */\n+\t\t\t\t   0, /* COUNT UP */\n+\t\t\t\t   4 /* COUNT DOWN */\n+\t\t);\n \n \t\t/* set gentime select and tag sel */\n \t\treg = __raw_readl(DI_SW_GEN1(disp, 9));\n \t\treg &= 0x1FFFFFFF;\n-\t\treg |= (3 - 1)<<29 | 0x00008000;\n+\t\treg |= (3 - 1) << 29 | 0x00008000;\n \t\t__raw_writel(reg, DI_SW_GEN1(disp, 9));\n \n \t\t__raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));\n@@ -1074,34 +1039,32 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \t\tdi_gen |= DI_GEN_POLARITY_8;\n \t} else {\n \t\t/* Setup internal HSYNC waveform */\n-\t\tipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,\n-\t\t\t\t0, DI_SYNC_NONE, 0, DI_SYNC_NONE,\n-\t\t\t\t0, DI_SYNC_NONE,\n-\t\t\t\tDI_SYNC_NONE, 0, 0);\n+\t\tipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, 0,\n+\t\t\t\t   DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,\n+\t\t\t\t   DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);\n \n \t\t/* Setup external (delayed) HSYNC waveform */\n \t\tipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,\n-\t\t\t\tDI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,\n-\t\t\t\t0, DI_SYNC_NONE, 1, DI_SYNC_NONE,\n-\t\t\t\tDI_SYNC_CLK, 0, h_sync_width * 2);\n+\t\t\t\t   DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,\n+\t\t\t\t   0, DI_SYNC_NONE, 1, DI_SYNC_NONE,\n+\t\t\t\t   DI_SYNC_CLK, 0, h_sync_width * 2);\n \t\t/* Setup VSYNC waveform */\n \t\tvsync_cnt = DI_SYNC_VSYNC;\n \t\tipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,\n-\t\t\t\tDI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,\n-\t\t\t\tDI_SYNC_NONE, 1, DI_SYNC_NONE,\n-\t\t\t\tDI_SYNC_INT_HSYNC, 0, v_sync_width * 2);\n+\t\t\t\t   DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,\n+\t\t\t\t   DI_SYNC_NONE, 1, DI_SYNC_NONE,\n+\t\t\t\t   DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);\n \t\t__raw_writel(v_total - 1, DI_SCR_CONF(disp));\n \n \t\t/* Setup active data waveform to sync with DC */\n \t\tipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,\n-\t\t\t\tv_sync_width + v_start_width, DI_SYNC_HSYNC,\n-\t\t\t\theight,\n-\t\t\t\tDI_SYNC_VSYNC, 0, DI_SYNC_NONE,\n-\t\t\t\tDI_SYNC_NONE, 0, 0);\n+\t\t\t\t   v_sync_width + v_start_width, DI_SYNC_HSYNC,\n+\t\t\t\t   height, DI_SYNC_VSYNC, 0, DI_SYNC_NONE,\n+\t\t\t\t   DI_SYNC_NONE, 0, 0);\n \t\tipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,\n-\t\t\t\th_sync_width + h_start_width, DI_SYNC_CLK,\n-\t\t\t\twidth, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,\n-\t\t\t\t0);\n+\t\t\t\t   h_sync_width + h_start_width, DI_SYNC_CLK,\n+\t\t\t\t   width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,\n+\t\t\t\t   0);\n \n \t\t/* reset all unused counters */\n \t\t__raw_writel(0, DI_SW_GEN0(disp, 6));\n@@ -1121,13 +1084,13 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \n \t\t/* Init template microcode */\n \t\tif (disp) {\n-\t\t   ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);\n-\t\t   ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);\n-\t\t   ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);\n+\t\t\tipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);\n+\t\t\tipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);\n+\t\t\tipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);\n \t\t} else {\n-\t\t   ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);\n-\t\t   ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);\n-\t\t   ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);\n+\t\t\tipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);\n+\t\t\tipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);\n+\t\t\tipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);\n \t\t}\n \n \t\tif (sig.Hsync_pol)\n@@ -1137,13 +1100,12 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n \n \t\tif (!sig.clk_pol)\n \t\t\tdi_gen |= DI_GEN_POL_CLK;\n-\n \t}\n \n \t__raw_writel(di_gen, DI_GENERAL(disp));\n \n-\t__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |\n-\t\t\t0x00000002, DI_SYNC_AS_GEN(disp));\n+\t__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002,\n+\t\t     DI_SYNC_AS_GEN(disp));\n \n \treg = __raw_readl(DI_POL(disp));\n \treg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);\n@@ -1165,12 +1127,12 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,\n  *\n  * @param\tchannel\t\tIPUv3 DP channel\n  *\n- * @param       enable          Boolean to enable or disable global alpha\n- *                              blending. If disabled, local blending is used.\n+ * @param\tenable\t\tBoolean to enable or disable global alpha\n+ *\t\t\t\tblending. If disabled, local blending is used.\n  *\n- * @param       alpha           Global alpha value.\n+ * @param\talpha\t\tGlobal alpha value.\n  *\n- * Return:      Returns 0 on success or negative error code on fail\n+ * Return:\tReturns 0 on success or negative error code on fail\n  */\n int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n \t\t\t\t  uint8_t alpha)\n@@ -1180,8 +1142,8 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n \tunsigned char bg_chan;\n \n \tif (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||\n-\t\t(channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||\n-\t\t(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))\n+\t      (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||\n+\t      (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))\n \t\treturn -EINVAL;\n \n \tif (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||\n@@ -1200,7 +1162,7 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n \n \tif (enable) {\n \t\treg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;\n-\t\t__raw_writel(reg | ((uint32_t) alpha << 24),\n+\t\t__raw_writel(reg | ((uint32_t)alpha << 24),\n \t\t\t     DP_GRAPH_WIND_CTRL());\n \n \t\treg = __raw_readl(DP_COM_CONF());\n@@ -1219,13 +1181,13 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n /*\n  * This function sets the transparent color key for SDC graphic plane.\n  *\n- * @param       channel         Input parameter for the logical channel ID.\n+ * @param\tchannel\t\tInput parameter for the logical channel ID.\n  *\n- * @param       enable          Boolean to enable or disable color key\n+ * @param\tenable\t\tBoolean to enable or disable color key\n  *\n- * @param       colorKey        24-bit RGB color for transparent color key.\n+ * @param\tcolorKey\t24-bit RGB color for transparent color key.\n  *\n- * Return:      Returns 0 on success or negative error code on fail\n+ * Return:\tReturns 0 on success or negative error code on fail\n  */\n int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n \t\t\t       uint32_t color_key)\n@@ -1235,17 +1197,16 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n \tint red, green, blue;\n \n \tif (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||\n-\t\t(channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||\n-\t\t(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))\n+\t      (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||\n+\t      (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))\n \t\treturn -EINVAL;\n \n \tcolor_key_4rgb = 1;\n \t/* Transform color key from rgb to yuv if CSC is enabled */\n \tif (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||\n-\t\t((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||\n-\t\t((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||\n-\t\t((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {\n-\n+\t    ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||\n+\t    ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||\n+\t    ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {\n \t\tdebug(\"color key 0x%x need change to yuv fmt\\n\", color_key);\n \n \t\tred = (color_key >> 16) & 0xFF;\ndiff --git a/drivers/video/imx/ipu_regs.h b/drivers/video/imx/ipu_regs.h\nindex 8d6ec4845f4..8e57a2add69 100644\n--- a/drivers/video/imx/ipu_regs.h\n+++ b/drivers/video/imx/ipu_regs.h\n@@ -13,69 +13,71 @@\n #ifndef __IPU_REGS_INCLUDED__\n #define __IPU_REGS_INCLUDED__\n \n-#define IPU_DISP0_BASE\t\t0x00000000\n-#define IPU_MCU_T_DEFAULT\t8\n-#define IPU_DISP1_BASE\t\t(IPU_MCU_T_DEFAULT << 25)\n-#define IPU_CM_REG_BASE\t\t0x00000000\n-#define IPU_STAT_REG_BASE\t0x00000200\n-#define IPU_IDMAC_REG_BASE\t0x00008000\n-#define IPU_ISP_REG_BASE\t0x00010000\n-#define IPU_DP_REG_BASE\t\t0x00018000\n-#define IPU_IC_REG_BASE\t\t0x00020000\n-#define IPU_IRT_REG_BASE\t0x00028000\n-#define IPU_CSI0_REG_BASE\t0x00030000\n-#define IPU_CSI1_REG_BASE\t0x00038000\n-#define IPU_DI0_REG_BASE\t0x00040000\n-#define IPU_DI1_REG_BASE\t0x00048000\n-#define IPU_SMFC_REG_BASE\t0x00050000\n-#define IPU_DC_REG_BASE\t\t0x00058000\n-#define IPU_DMFC_REG_BASE\t0x00060000\n-#define IPU_VDI_REG_BASE\t0x00680000\n+#include <asm/arch/imx-regs.h>\n+\n+#define IPU_DISP0_BASE 0x00000000\n+#define IPU_MCU_T_DEFAULT 8\n+#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)\n+#define IPU_CM_REG_BASE 0x00000000\n+#define IPU_STAT_REG_BASE 0x00000200\n+#define IPU_IDMAC_REG_BASE 0x00008000\n+#define IPU_ISP_REG_BASE 0x00010000\n+#define IPU_DP_REG_BASE 0x00018000\n+#define IPU_IC_REG_BASE 0x00020000\n+#define IPU_IRT_REG_BASE 0x00028000\n+#define IPU_CSI0_REG_BASE 0x00030000\n+#define IPU_CSI1_REG_BASE 0x00038000\n+#define IPU_DI0_REG_BASE 0x00040000\n+#define IPU_DI1_REG_BASE 0x00048000\n+#define IPU_SMFC_REG_BASE 0x00050000\n+#define IPU_DC_REG_BASE 0x00058000\n+#define IPU_DMFC_REG_BASE 0x00060000\n+#define IPU_VDI_REG_BASE 0x00680000\n #if defined(CONFIG_MX51) || defined(CONFIG_MX53)\n-#define IPU_CPMEM_REG_BASE\t0x01000000\n-#define IPU_LUT_REG_BASE\t0x01020000\n-#define IPU_SRM_REG_BASE\t0x01040000\n-#define IPU_TPM_REG_BASE\t0x01060000\n-#define IPU_DC_TMPL_REG_BASE\t0x01080000\n-#define IPU_ISP_TBPR_REG_BASE\t0x010C0000\n+#define IPU_CPMEM_REG_BASE 0x01000000\n+#define IPU_LUT_REG_BASE 0x01020000\n+#define IPU_SRM_REG_BASE 0x01040000\n+#define IPU_TPM_REG_BASE 0x01060000\n+#define IPU_DC_TMPL_REG_BASE 0x01080000\n+#define IPU_ISP_TBPR_REG_BASE 0x010C0000\n #elif defined(CONFIG_MX6)\n-#define IPU_CPMEM_REG_BASE\t0x00100000\n-#define IPU_LUT_REG_BASE\t0x00120000\n-#define IPU_SRM_REG_BASE\t0x00140000\n-#define IPU_TPM_REG_BASE\t0x00160000\n-#define IPU_DC_TMPL_REG_BASE\t0x00180000\n-#define IPU_ISP_TBPR_REG_BASE\t0x001C0000\n+#define IPU_CPMEM_REG_BASE 0x00100000\n+#define IPU_LUT_REG_BASE 0x00120000\n+#define IPU_SRM_REG_BASE 0x00140000\n+#define IPU_TPM_REG_BASE 0x00160000\n+#define IPU_DC_TMPL_REG_BASE 0x00180000\n+#define IPU_ISP_TBPR_REG_BASE 0x001C0000\n #endif\n \n-#define IPU_CTRL_BASE_ADDR\t(IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)\n+#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)\n \n extern u32 *ipu_dc_tmpl_reg;\n \n-#define DC_EVT_NF\t\t0\n-#define DC_EVT_NL\t\t1\n-#define DC_EVT_EOF\t\t2\n-#define DC_EVT_NFIELD\t\t3\n-#define DC_EVT_EOL\t\t4\n-#define DC_EVT_EOFIELD\t\t5\n-#define DC_EVT_NEW_ADDR\t\t6\n-#define DC_EVT_NEW_CHAN\t\t7\n-#define DC_EVT_NEW_DATA\t\t8\n-\n-#define DC_EVT_NEW_ADDR_W_0\t0\n-#define DC_EVT_NEW_ADDR_W_1\t1\n-#define DC_EVT_NEW_CHAN_W_0\t2\n-#define DC_EVT_NEW_CHAN_W_1\t3\n-#define DC_EVT_NEW_DATA_W_0\t4\n-#define DC_EVT_NEW_DATA_W_1\t5\n-#define DC_EVT_NEW_ADDR_R_0\t6\n-#define DC_EVT_NEW_ADDR_R_1\t7\n-#define DC_EVT_NEW_CHAN_R_0\t8\n-#define DC_EVT_NEW_CHAN_R_1\t9\n-#define DC_EVT_NEW_DATA_R_0\t10\n-#define DC_EVT_NEW_DATA_R_1\t11\n+#define DC_EVT_NF 0\n+#define DC_EVT_NL 1\n+#define DC_EVT_EOF 2\n+#define DC_EVT_NFIELD 3\n+#define DC_EVT_EOL 4\n+#define DC_EVT_EOFIELD 5\n+#define DC_EVT_NEW_ADDR 6\n+#define DC_EVT_NEW_CHAN 7\n+#define DC_EVT_NEW_DATA 8\n+\n+#define DC_EVT_NEW_ADDR_W_0 0\n+#define DC_EVT_NEW_ADDR_W_1 1\n+#define DC_EVT_NEW_CHAN_W_0 2\n+#define DC_EVT_NEW_CHAN_W_1 3\n+#define DC_EVT_NEW_DATA_W_0 4\n+#define DC_EVT_NEW_DATA_W_1 5\n+#define DC_EVT_NEW_ADDR_R_0 6\n+#define DC_EVT_NEW_ADDR_R_1 7\n+#define DC_EVT_NEW_CHAN_R_0 8\n+#define DC_EVT_NEW_CHAN_R_1 9\n+#define DC_EVT_NEW_DATA_R_0 10\n+#define DC_EVT_NEW_DATA_R_1 11\n \n /* Software reset for ipu */\n-#define SW_IPU_RST\t8\n+#define SW_IPU_RST 8\n \n enum {\n \tIPU_CONF_DP_EN = 0x00000020,\n@@ -296,67 +298,63 @@ struct ipu_dmfc {\n \tu32 stat;\n };\n \n-#define IPU_CM_REG\t\t((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_CM_REG_BASE))\n-#define IPU_CONF\t\t(&IPU_CM_REG->conf)\n-#define IPU_SRM_PRI1\t\t(&IPU_CM_REG->srm_pri1)\n-#define IPU_SRM_PRI2\t\t(&IPU_CM_REG->srm_pri2)\n-#define IPU_FS_PROC_FLOW1\t(&IPU_CM_REG->fs_proc_flow[0])\n-#define IPU_FS_PROC_FLOW2\t(&IPU_CM_REG->fs_proc_flow[1])\n-#define IPU_FS_PROC_FLOW3\t(&IPU_CM_REG->fs_proc_flow[2])\n-#define IPU_FS_DISP_FLOW1\t(&IPU_CM_REG->fs_disp_flow[0])\n-#define IPU_DISP_GEN\t\t(&IPU_CM_REG->disp_gen)\n-#define IPU_MEM_RST\t\t(&IPU_CM_REG->mem_rst)\n-#define IPU_GPR\t\t\t(&IPU_CM_REG->gpr)\n-#define IPU_CHA_DB_MODE_SEL(ch)\t(&IPU_CM_REG->ch_db_mode_sel[ch / 32])\n-\n-#define IPU_STAT\t\t((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_STAT_REG_BASE))\n-#define IPU_INT_STAT(n)\t\t(&IPU_STAT->int_stat[(n) - 1])\n-#define IPU_CHA_CUR_BUF(ch)\t(&IPU_STAT->cur_buf[ch / 32])\n-#define IPU_CHA_BUF0_RDY(ch)\t(&IPU_STAT->ch_buf0_rdy[ch / 32])\n-#define IPU_CHA_BUF1_RDY(ch)\t(&IPU_STAT->ch_buf1_rdy[ch / 32])\n-#define IPUIRQ_2_STATREG(irq)\t(IPU_INT_STAT(1) + ((irq) / 32))\n-#define IPUIRQ_2_MASK(irq)\t(1UL << ((irq) & 0x1F))\n-\n-#define IPU_INT_CTRL(n)\t\t(&IPU_CM_REG->int_ctrl[(n) - 1])\n-\n-#define IDMAC_REG\t\t((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_IDMAC_REG_BASE))\n-#define IDMAC_CONF\t\t(&IDMAC_REG->conf)\n-#define IDMAC_CHA_EN(ch)\t(&IDMAC_REG->ch_en[ch / 32])\n-#define IDMAC_CHA_PRI(ch)\t(&IDMAC_REG->ch_pri[ch / 32])\n-\n-#define DI_REG(di)\t\t((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\t((di == 1) ? IPU_DI1_REG_BASE : \\\n-\t\t\t\tIPU_DI0_REG_BASE)))\n-#define DI_GENERAL(di)\t\t(&DI_REG(di)->general)\n-#define DI_BS_CLKGEN0(di)\t(&DI_REG(di)->bs_clkgen0)\n-#define DI_BS_CLKGEN1(di)\t(&DI_REG(di)->bs_clkgen1)\n-\n-#define DI_SW_GEN0(di, gen)\t(&DI_REG(di)->sw_gen0[gen - 1])\n-#define DI_SW_GEN1(di, gen)\t(&DI_REG(di)->sw_gen1[gen - 1])\n-#define DI_STP_REP(di, gen)\t(&DI_REG(di)->stp_rep[(gen - 1) / 2])\n-#define DI_STP_REP9(di)\t\t(&DI_REG(di)->stp_rep9)\n-#define DI_SYNC_AS_GEN(di)\t(&DI_REG(di)->sync_as)\n-#define DI_DW_GEN(di, gen)\t(&DI_REG(di)->dw_gen[gen])\n-#define DI_DW_SET(di, gen, set)\t(&DI_REG(di)->dw_set[gen + 12 * set])\n-#define DI_POL(di)\t\t(&DI_REG(di)->pol)\n-#define DI_SCR_CONF(di)\t\t(&DI_REG(di)->scr_conf)\n-\n-#define DMFC_REG\t\t((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_DMFC_REG_BASE))\n-#define DMFC_WR_CHAN\t\t(&DMFC_REG->wr_chan)\n-#define DMFC_WR_CHAN_DEF\t(&DMFC_REG->wr_chan_def)\n-#define DMFC_DP_CHAN\t\t(&DMFC_REG->dp_chan)\n-#define DMFC_DP_CHAN_DEF\t(&DMFC_REG->dp_chan_def)\n-#define DMFC_GENERAL1\t\t(&DMFC_REG->general[0])\n-#define DMFC_IC_CTRL\t\t(&DMFC_REG->ic_ctrl)\n-\n-#define DC_REG\t\t\t((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_DC_REG_BASE))\n-#define DC_MAP_CONF_PTR(n)\t(&DC_REG->dc_map_ptr[n / 2])\n-#define DC_MAP_CONF_VAL(n)\t(&DC_REG->dc_map_val[n / 2])\n+#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + IPU_CM_REG_BASE))\n+#define IPU_CONF (&IPU_CM_REG->conf)\n+#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)\n+#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)\n+#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])\n+#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])\n+#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])\n+#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])\n+#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)\n+#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)\n+#define IPU_GPR (&IPU_CM_REG->gpr)\n+#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])\n+\n+#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + IPU_STAT_REG_BASE))\n+#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1])\n+#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])\n+#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])\n+#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])\n+#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))\n+#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))\n+\n+#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])\n+\n+#define IDMAC_REG \\\n+\t((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + IPU_IDMAC_REG_BASE))\n+#define IDMAC_CONF (&IDMAC_REG->conf)\n+#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])\n+#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])\n+\n+#define DI_REG(di)                              \\\n+\t((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \\\n+\t\t\t   ((di == 1) ? IPU_DI1_REG_BASE : IPU_DI0_REG_BASE)))\n+#define DI_GENERAL(di) (&DI_REG(di)->general)\n+#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)\n+#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)\n+\n+#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])\n+#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])\n+#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])\n+#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)\n+#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)\n+#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])\n+#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])\n+#define DI_POL(di) (&DI_REG(di)->pol)\n+#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)\n+\n+#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + IPU_DMFC_REG_BASE))\n+#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)\n+#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)\n+#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)\n+#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)\n+#define DMFC_GENERAL1 (&DMFC_REG->general[0])\n+#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)\n+\n+#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + IPU_DC_REG_BASE))\n+#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])\n+#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])\n \n static inline struct ipu_dc_ch *dc_ch_offset(int ch)\n {\n@@ -376,38 +374,36 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch)\n \t\tprintf(\"%s: invalid channel %d\\n\", __func__, ch);\n \t\treturn NULL;\n \t}\n-\n }\n \n-#define DC_RL_CH(ch, evt)\t(&dc_ch_offset(ch)->rl[evt / 2])\n+#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])\n \n-#define DC_WR_CH_CONF(ch)\t(&dc_ch_offset(ch)->wr_ch_conf)\n-#define DC_WR_CH_ADDR(ch)\t(&dc_ch_offset(ch)->wr_ch_addr)\n+#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)\n+#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)\n \n-#define DC_WR_CH_CONF_1\t\tDC_WR_CH_CONF(1)\n-#define DC_WR_CH_CONF_5\t\tDC_WR_CH_CONF(5)\n+#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)\n+#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)\n \n-#define DC_GEN\t\t\t(&DC_REG->gen)\n-#define DC_DISP_CONF2(disp)\t(&DC_REG->disp_conf2[disp])\n-#define DC_STAT\t\t\t(&DC_REG->stat)\n+#define DC_GEN (&DC_REG->gen)\n+#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])\n+#define DC_STAT (&DC_REG->stat)\n \n #define DP_SYNC 0\n #define DP_ASYNC0 0x60\n #define DP_ASYNC1 0xBC\n \n-#define DP_REG\t\t\t((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \\\n-\t\t\t\tIPU_DP_REG_BASE))\n-#define DP_COM_CONF()\t\t(&DP_REG->com_conf_sync)\n-#define DP_GRAPH_WIND_CTRL()\t(&DP_REG->graph_wind_ctrl_sync)\n-#define DP_CSC_A_0()\t\t(&DP_REG->csca_sync[0])\n-#define DP_CSC_A_1()\t\t(&DP_REG->csca_sync[1])\n-#define DP_CSC_A_2()\t\t(&DP_REG->csca_sync[2])\n-#define DP_CSC_A_3()\t\t(&DP_REG->csca_sync[3])\n+#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + IPU_DP_REG_BASE))\n+#define DP_COM_CONF() (&DP_REG->com_conf_sync)\n+#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)\n+#define DP_CSC_A_0() (&DP_REG->csca_sync[0])\n+#define DP_CSC_A_1() (&DP_REG->csca_sync[1])\n+#define DP_CSC_A_2() (&DP_REG->csca_sync[2])\n+#define DP_CSC_A_3() (&DP_REG->csca_sync[3])\n \n-#define DP_CSC_0()\t\t(&DP_REG->csc_sync[0])\n-#define DP_CSC_1()\t\t(&DP_REG->csc_sync[1])\n+#define DP_CSC_0() (&DP_REG->csc_sync[0])\n+#define DP_CSC_1() (&DP_REG->csc_sync[1])\n \n /* DC template opcodes */\n-#define WROD(lf)\t\t(0x18 | (lf << 1))\n+#define WROD(lf) (0x18 | (lf << 1))\n \n #endif\ndiff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c\nindex fdeb3cabea7..6b81d522041 100644\n--- a/drivers/video/imx/mxc_ipuv3_fb.c\n+++ b/drivers/video/imx/mxc_ipuv3_fb.c\n@@ -10,23 +10,23 @@\n  * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.\n  */\n \n-#include <log.h>\n-#include <part.h>\n+#include \"../videomodes.h\"\n+#include \"display.h\"\n+#include \"ipu.h\"\n+#include \"ipu_regs.h\"\n+#include \"mxcfb.h\"\n #include <asm/cache.h>\n-#include <linux/errno.h>\n #include <asm/global_data.h>\n-#include <linux/string.h>\n-#include <linux/list.h>\n-#include <linux/fb.h>\n #include <asm/io.h>\n #include <asm/mach-imx/video.h>\n+#include <linux/errno.h>\n+#include <linux/fb.h>\n+#include <linux/list.h>\n+#include <linux/string.h>\n+#include <log.h>\n #include <malloc.h>\n-#include \"../videomodes.h\"\n-#include \"ipu.h\"\n-#include \"mxcfb.h\"\n-#include \"ipu_regs.h\"\n-#include \"display.h\"\n #include <panel.h>\n+#include <part.h>\n \n #include <dm.h>\n #include <video.h>\n@@ -41,7 +41,7 @@ static uint8_t gdisp;\n static uint32_t gpixfmt;\n \n static void fb_videomode_to_var(struct fb_var_screeninfo *var,\n-\t\t\t const struct fb_videomode *mode)\n+\t\t\t\tconst struct fb_videomode *mode)\n {\n \tvar->xres = mode->xres;\n \tvar->yres = mode->yres;\n@@ -82,12 +82,7 @@ struct mxcfb_info {\n \tu32 pseudo_palette[16];\n };\n \n-enum {\n-\tBOTH_ON,\n-\tSRC_ON,\n-\tTGT_ON,\n-\tBOTH_OFF\n-};\n+enum { BOTH_ON, SRC_ON, TGT_ON, BOTH_OFF };\n \n static unsigned long default_bpp = 16;\n static unsigned char g_dp_in_use;\n@@ -132,16 +127,11 @@ static int setup_disp_channel1(struct fb_info *fbi)\n \t */\n \tif (fbi->var.vmode & FB_VMODE_INTERLACED) {\n \t\tparams.mem_dp_bg_sync.interlaced = 1;\n-\t\tparams.mem_dp_bg_sync.out_pixel_fmt =\n-\t\t\tIPU_PIX_FMT_YUV444;\n+\t\tparams.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_YUV444;\n+\t} else if (mxc_fbi->ipu_di_pix_fmt) {\n+\t\tparams.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;\n \t} else {\n-\t\tif (mxc_fbi->ipu_di_pix_fmt) {\n-\t\t\tparams.mem_dp_bg_sync.out_pixel_fmt =\n-\t\t\t\tmxc_fbi->ipu_di_pix_fmt;\n-\t\t} else {\n-\t\t\tparams.mem_dp_bg_sync.out_pixel_fmt =\n-\t\t\t\tIPU_PIX_FMT_RGB666;\n-\t\t}\n+\t\tparams.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;\n \t}\n \tparams.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);\n \tif (mxc_fbi->alpha_chan_en)\n@@ -163,24 +153,16 @@ static int setup_disp_channel2(struct fb_info *fbi)\n \n \tfbi->var.xoffset = fbi->var.yoffset = 0;\n \n-\tdebug(\"%s: %x %d %d %d %lx %lx\\n\",\n-\t\t__func__,\n-\t\tmxc_fbi->ipu_ch,\n-\t\tfbi->var.xres,\n-\t\tfbi->var.yres,\n-\t\tfbi->fix.line_length,\n-\t\tfbi->fix.smem_start,\n-\t\tfbi->fix.smem_start +\n-\t\t(fbi->fix.line_length * fbi->var.yres));\n-\n-\tretval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,\n-\t\t\t\t\t bpp_to_pixfmt(fbi),\n-\t\t\t\t\t fbi->var.xres, fbi->var.yres,\n-\t\t\t\t\t fbi->fix.line_length,\n-\t\t\t\t\t fbi->fix.smem_start +\n-\t\t\t\t\t (fbi->fix.line_length * fbi->var.yres),\n-\t\t\t\t\t fbi->fix.smem_start,\n-\t\t\t\t\t 0, 0);\n+\tdebug(\"%s: %x %d %d %d %lx %lx\\n\", __func__, mxc_fbi->ipu_ch,\n+\t      fbi->var.xres, fbi->var.yres, fbi->fix.line_length,\n+\t      fbi->fix.smem_start,\n+\t      fbi->fix.smem_start + (fbi->fix.line_length * fbi->var.yres));\n+\n+\tretval = ipu_init_channel_buffer(\n+\t\tmxc_fbi->ipu_ch, IPU_INPUT_BUFFER, bpp_to_pixfmt(fbi),\n+\t\tfbi->var.xres, fbi->var.yres, fbi->fix.line_length,\n+\t\tfbi->fix.smem_start + (fbi->fix.line_length * fbi->var.yres),\n+\t\tfbi->fix.smem_start, 0, 0);\n \tif (retval)\n \t\tprintf(\"ipu_init_channel_buffer error %d\\n\", retval);\n \n@@ -190,7 +172,7 @@ static int setup_disp_channel2(struct fb_info *fbi)\n /*\n  * Set framebuffer parameters and change the operating mode.\n  *\n- * @param       info     framebuffer information pointer\n+ * @param\tinfo\t framebuffer information pointer\n  */\n static int mxcfb_set_par(struct fb_info *fbi)\n {\n@@ -245,15 +227,11 @@ static int mxcfb_set_par(struct fb_info *fbi)\n \n \tif (ipu_init_sync_panel(mxc_fbi->ipu_di,\n \t\t\t\t(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,\n-\t\t\t\tfbi->var.xres, fbi->var.yres,\n-\t\t\t\tout_pixel_fmt,\n-\t\t\t\tfbi->var.left_margin,\n-\t\t\t\tfbi->var.hsync_len,\n-\t\t\t\tfbi->var.right_margin,\n-\t\t\t\tfbi->var.upper_margin,\n-\t\t\t\tfbi->var.vsync_len,\n-\t\t\t\tfbi->var.lower_margin,\n-\t\t\t\t0, sig_cfg) != 0) {\n+\t\t\t\tfbi->var.xres, fbi->var.yres, out_pixel_fmt,\n+\t\t\t\tfbi->var.left_margin, fbi->var.hsync_len,\n+\t\t\t\tfbi->var.right_margin, fbi->var.upper_margin,\n+\t\t\t\tfbi->var.vsync_len, fbi->var.lower_margin, 0,\n+\t\t\t\tsig_cfg) != 0) {\n \t\tputs(\"mxcfb: Error initializing panel.\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -271,9 +249,9 @@ static int mxcfb_set_par(struct fb_info *fbi)\n /*\n  * Check framebuffer variable parameters and adjust to valid values.\n  *\n- * @param       var      framebuffer variable parameters\n+ * @param\tvar\t framebuffer variable parameters\n  *\n- * @param       info     framebuffer information pointer\n+ * @param\tinfo\t framebuffer information pointer\n  */\n static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)\n {\n@@ -362,13 +340,13 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)\n \n \tif (var->pixclock < 1000) {\n \t\thtotal = var->xres + var->right_margin + var->hsync_len +\n-\t\t    var->left_margin;\n+\t\t\t var->left_margin;\n \t\tvtotal = var->yres + var->lower_margin + var->vsync_len +\n-\t\t    var->upper_margin;\n+\t\t\t var->upper_margin;\n \t\tvar->pixclock = (vtotal * htotal * 6UL) / 100UL;\n \t\tvar->pixclock = KHZ2PICOS(var->pixclock);\n \t\tprintf(\"pixclock set for 60Hz refresh = %u ps\\n\",\n-\t\t\tvar->pixclock);\n+\t\t       var->pixclock);\n \t}\n \n \tvar->height = -1;\n@@ -384,8 +362,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)\n \tstruct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);\n \n \tif (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {\n-\t\tfbi->fix.smem_len = fbi->var.yres_virtual *\n-\t\t\t\t    fbi->fix.line_length;\n+\t\tfbi->fix.smem_len =\n+\t\t\tfbi->var.yres_virtual * fbi->fix.line_length;\n \t}\n \tfbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);\n \n@@ -400,7 +378,7 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)\n \t}\n \n \tdebug(\"allocated fb @ paddr=0x%08X, size=%d.\\n\",\n-\t\t(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);\n+\t      (uint32_t)fbi->fix.smem_start, fbi->fix.smem_len);\n \n \tfbi->screen_size = fbi->fix.smem_len;\n \n@@ -422,10 +400,10 @@ static int mxcfb_unmap_video_memory(struct fb_info *fbi)\n  * Initializes the framebuffer information pointer. After allocating\n  * sufficient memory for the framebuffer structure, the fields are\n  * filled with custom information passed in from the configurable\n- * structures.  This includes information such as bits per pixel,\n+ * structures.\tThis includes information such as bits per pixel,\n  * color maps, screen width/height and RGBA offsets.\n  *\n- * Return:      Framebuffer structure initialized with our information\n+ * Return:\tFramebuffer structure initialized with our information\n  */\n static struct fb_info *mxcfb_init_fbinfo(void)\n {\n@@ -434,15 +412,10 @@ static struct fb_info *mxcfb_init_fbinfo(void)\n \tstruct fb_info *fbi;\n \tstruct mxcfb_info *mxcfbi;\n \tchar *p;\n-\tint size = sizeof(struct mxcfb_info) + PADDING +\n-\t\tsizeof(struct fb_info);\n-\n-\tdebug(\"%s: %d %d %d %d\\n\",\n-\t\t__func__,\n-\t\tPADDING,\n-\t\tsize,\n-\t\tsizeof(struct mxcfb_info),\n-\t\tsizeof(struct fb_info));\n+\tint size = sizeof(struct mxcfb_info) + PADDING + sizeof(struct fb_info);\n+\n+\tdebug(\"%s: %d %d %d %d\\n\", __func__, PADDING, size,\n+\t      sizeof(struct mxcfb_info), sizeof(struct fb_info));\n \t/*\n \t * Allocate sufficient memory for the fb structure\n \t */\n@@ -458,7 +431,7 @@ static struct fb_info *mxcfb_init_fbinfo(void)\n \n \tmxcfbi = (struct mxcfb_info *)fbi->par;\n \tdebug(\"Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\\n\",\n-\t\t(unsigned int)fbi, (unsigned int)mxcfbi);\n+\t      (unsigned int)fbi, (unsigned int)mxcfbi);\n \n \tfbi->var.activate = FB_ACTIVATE_NOW;\n \n@@ -476,10 +449,10 @@ extern struct clk *g_ipu_clk;\n  * this routine: Framebuffer initialization, Memory allocation and\n  * mapping, Framebuffer registration, IPU initialization.\n  *\n- * Return:      Appropriate error code to the kernel common code\n+ * Return:\tAppropriate error code to the kernel common code\n  */\n-static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,\n-\t\t       uint8_t disp, struct fb_videomode const *mode)\n+static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, uint8_t disp,\n+\t\t       struct fb_videomode const *mode)\n {\n \tstruct fb_info *fbi;\n \tstruct mxcfb_info *mxcfbi;\n@@ -519,8 +492,8 @@ static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,\n \tmxcfbi->ipu_di_pix_fmt = interface_pix_fmt;\n \tfb_videomode_to_var(&fbi->var, mode);\n \tfbi->var.bits_per_pixel = 16;\n-\tfbi->fix.line_length = fbi->var.xres_virtual *\n-\t\t\t       (fbi->var.bits_per_pixel / 8);\n+\tfbi->fix.line_length =\n+\t\tfbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);\n \tfbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;\n \n \tmxcfb_check_var(&fbi->var, fbi);\n@@ -563,8 +536,7 @@ void ipuv3_fb_shutdown(void)\n \t}\n }\n \n-int ipuv3_fb_init(struct fb_videomode const *mode,\n-\t\t  uint8_t disp,\n+int ipuv3_fb_init(struct fb_videomode const *mode, uint8_t disp,\n \t\t  uint32_t pixfmt)\n {\n \tgmode = mode;\n@@ -576,9 +548,9 @@ int ipuv3_fb_init(struct fb_videomode const *mode,\n \n enum {\n \t/* Maximum display size we support */\n-\tLCD_MAX_WIDTH\t\t= 1920,\n-\tLCD_MAX_HEIGHT\t\t= 1080,\n-\tLCD_MAX_LOG2_BPP\t= VIDEO_BPP16,\n+\tLCD_MAX_WIDTH = 1920,\n+\tLCD_MAX_HEIGHT = 1080,\n+\tLCD_MAX_LOG2_BPP = VIDEO_BPP16,\n };\n \n static int ipuv3_video_probe(struct udevice *dev)\n@@ -591,8 +563,8 @@ static int ipuv3_video_probe(struct udevice *dev)\n \tu32 fb_start, fb_end;\n \tint ret;\n \n-\tdebug(\"%s() plat: base 0x%lx, size 0x%x\\n\",\n-\t      __func__, plat->base, plat->size);\n+\tdebug(\"%s() plat: base 0x%lx, size 0x%x\\n\", __func__, plat->base,\n+\t      plat->size);\n \n \tret = ipu_probe();\n \tif (ret)\n@@ -644,8 +616,7 @@ static int ipuv3_video_bind(struct udevice *dev)\n {\n \tstruct video_uc_plat *plat = dev_get_uclass_plat(dev);\n \n-\tplat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *\n-\t\t     (1 << VIDEO_BPP32) / 8;\n+\tplat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * (1 << VIDEO_BPP32) / 8;\n \n \treturn 0;\n }\n@@ -657,15 +628,15 @@ static const struct udevice_id ipuv3_video_ids[] = {\n #ifdef CONFIG_ARCH_MX5\n \t{ .compatible = \"fsl,imx53-ipu\" },\n #endif\n-\t{ }\n+\t{}\n };\n \n U_BOOT_DRIVER(fsl_imx6q_ipu) = {\n-\t.name\t= \"fsl_imx6q_ipu\",\n-\t.id\t= UCLASS_VIDEO,\n+\t.name = \"fsl_imx6q_ipu\",\n+\t.id = UCLASS_VIDEO,\n \t.of_match = ipuv3_video_ids,\n-\t.bind\t= ipuv3_video_bind,\n-\t.probe\t= ipuv3_video_probe,\n-\t.priv_auto\t= sizeof(struct ipuv3_video_priv),\n-\t.flags\t= DM_FLAG_PRE_RELOC,\n+\t.bind = ipuv3_video_bind,\n+\t.probe = ipuv3_video_probe,\n+\t.priv_auto = sizeof(struct ipuv3_video_priv),\n+\t.flags = DM_FLAG_PRE_RELOC,\n };\n",
    "prefixes": [
        "v1",
        "2/7"
    ]
}