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GET /api/1.0/patches/2175539/?format=api
{ "id": 2175539, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175539/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218083326.644326-4-brian.ruley@gehealthcare.com>", "date": "2025-12-18T08:33:22", "name": "[v1,3/7] video: imx: ipuv3: prefer kernel types", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c6bf9b6202abeaae0e6b98ef111d9118123edc54", "submitter": { "id": 89422, "url": "http://patchwork.ozlabs.org/api/1.0/people/89422/?format=api", "name": "Brian Ruley", "email": "brian.ruley@gehealthcare.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.0/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218083326.644326-4-brian.ruley@gehealthcare.com/mbox/", "series": [ { "id": 485836, "url": "http://patchwork.ozlabs.org/api/1.0/series/485836/?format=api", "date": "2025-12-18T08:33:20", "name": "Refactor i.MX IPU driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485836/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175539/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 header.b=u7n3P+0G;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n 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<brian.ruley@gehealthcare.com>,\n Stefano Babic <sbabic@nabladev.com>", "Subject": "[PATCH v1 3/7] video: imx: ipuv3: prefer kernel types", "Date": "Thu, 18 Dec 2025 10:33:22 +0200", "Message-Id": "<20251218083326.644326-4-brian.ruley@gehealthcare.com>", "X-Mailer": "git-send-email 2.39.5", "In-Reply-To": "<20251218083326.644326-1-brian.ruley@gehealthcare.com>", "References": "<20251218083326.644326-1-brian.ruley@gehealthcare.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D4:EE_|IA2PR22MB5650:EE_", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "9a0cd8d3-215f-4d46-9b10-08de3e102119", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|82310400026|36860700013;", "X-Microsoft-Antispam-Message-Info": "\n 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"X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA2PR22MB5650", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 13:13:44 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Conform with U-Boot guidelines and pass checkpatch checks for upcoming\nchanges.\n\nSigned-off-by: Brian Ruley <brian.ruley@gehealthcare.com>\n---\n\n drivers/video/imx/ipu.h | 58 +++++++++++++-------------\n drivers/video/imx/ipu_common.c | 70 ++++++++++++++++----------------\n drivers/video/imx/ipu_disp.c | 50 +++++++++++------------\n drivers/video/imx/mxc_ipuv3_fb.c | 23 +++++------\n 4 files changed, 96 insertions(+), 105 deletions(-)", "diff": "diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h\nindex 58f68b6b9cf..83cd0d8470e 100644\n--- a/drivers/video/imx/ipu.h\n+++ b/drivers/video/imx/ipu.h\n@@ -83,10 +83,10 @@ typedef enum {\n #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))\n #define IPU_CHAN_ID(ch) (ch >> 24)\n #define IPU_CHAN_ALT(ch) (ch & 0x02000000)\n-#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t)(ch >> 6) & 0x3F)\n-#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t)(ch >> 12) & 0x3F)\n-#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t)(ch >> 18) & 0x3F)\n-#define IPU_CHAN_OUT_DMA(ch) ((uint32_t)(ch & 0x3F))\n+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((u32)(ch >> 6) & 0x3F)\n+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((u32)(ch >> 12) & 0x3F)\n+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((u32)(ch >> 18) & 0x3F)\n+#define IPU_CHAN_OUT_DMA(ch) ((u32)(ch & 0x3F))\n #define NO_DMA 0x3F\n #define ALT 1\n \n@@ -148,27 +148,27 @@ enum ipu_dmfc_type {\n */\n typedef union {\n \tstruct {\n-\t\tuint32_t di;\n+\t\tu32 di;\n \t\tunsigned char interlaced;\n \t} mem_dc_sync;\n \tstruct {\n-\t\tuint32_t temp;\n+\t\tu32 temp;\n \t} mem_sdc_fg;\n \tstruct {\n-\t\tuint32_t di;\n+\t\tu32 di;\n \t\tunsigned char interlaced;\n-\t\tuint32_t in_pixel_fmt;\n-\t\tuint32_t out_pixel_fmt;\n+\t\tu32 in_pixel_fmt;\n+\t\tu32 out_pixel_fmt;\n \t\tunsigned char alpha_chan_en;\n \t} mem_dp_bg_sync;\n \tstruct {\n-\t\tuint32_t temp;\n+\t\tu32 temp;\n \t} mem_sdc_bg;\n \tstruct {\n-\t\tuint32_t di;\n+\t\tu32 di;\n \t\tunsigned char interlaced;\n-\t\tuint32_t in_pixel_fmt;\n-\t\tuint32_t out_pixel_fmt;\n+\t\tu32 in_pixel_fmt;\n+\t\tu32 out_pixel_fmt;\n \t\tunsigned char alpha_chan_en;\n \t} mem_dp_fg_sync;\n } ipu_channel_params_t;\n@@ -205,29 +205,28 @@ int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);\n void ipu_uninit_channel(ipu_channel_t channel);\n \n int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t\tuint32_t pixel_fmt, uint16_t width,\n-\t\t\t\tuint16_t height, uint32_t stride,\n-\t\t\t\tdma_addr_t phyaddr_0, dma_addr_t phyaddr_1,\n-\t\t\t\tuint32_t u_offset, uint32_t v_offset);\n+\t\t\t\tu32 pixel_fmt, u16 width, u16 height,\n+\t\t\t\tu32 stride, dma_addr_t phyaddr_0,\n+\t\t\t\tdma_addr_t phyaddr_1, u32 u_offset,\n+\t\t\t\tu32 v_offset);\n \n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t uint32_t bufNum);\n+\t\t\t u32 bufNum);\n int32_t ipu_enable_channel(ipu_channel_t channel);\n int32_t ipu_disable_channel(ipu_channel_t channel);\n \n-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,\n-\t\t\t uint16_t height, uint32_t pixel_fmt,\n-\t\t\t uint16_t h_start_width, uint16_t h_sync_width,\n-\t\t\t uint16_t h_end_width, uint16_t v_start_width,\n-\t\t\t uint16_t v_sync_width, uint16_t v_end_width,\n-\t\t\t uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);\n+int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,\n+\t\t\t u32 pixel_fmt, u16 h_start_width, u16 h_sync_width,\n+\t\t\t u16 h_end_width, u16 v_start_width,\n+\t\t\t u16 v_sync_width, u16 v_end_width, u32 v_to_h_sync,\n+\t\t\t ipu_di_signal_cfg_t sig);\n \n int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n-\t\t\t\t uint8_t alpha);\n+\t\t\t\t u8 alpha);\n int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n-\t\t\t uint32_t colorKey);\n+\t\t\t u32 colorKey);\n \n-uint32_t bytes_per_pixel(uint32_t fmt);\n+u32 bytes_per_pixel(u32 fmt);\n \n void clk_enable(struct clk *clk);\n void clk_disable(struct clk *clk);\n@@ -248,9 +247,8 @@ void ipu_dmfc_set_wait4eot(int dma_chan, int width);\n void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);\n void ipu_dc_uninit(int dc_chan);\n void ipu_dp_dc_enable(ipu_channel_t channel);\n-int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n-\t\tuint32_t out_pixel_fmt);\n+int ipu_dp_init(ipu_channel_t channel, u32 in_pixel_fmt, u32 out_pixel_fmt);\n void ipu_dp_uninit(ipu_channel_t channel);\n void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);\n-ipu_color_space_t format_to_colorspace(uint32_t fmt);\n+ipu_color_space_t format_to_colorspace(u32 fmt);\n #endif\ndiff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c\nindex 72421aa5a03..78bff87097e 100644\n--- a/drivers/video/imx/ipu_common.c\n+++ b/drivers/video/imx/ipu_common.c\n@@ -29,8 +29,8 @@ extern struct mxc_ccm_reg *mxc_ccm;\n extern u32 *ipu_cpmem_base;\n \n struct ipu_ch_param_word {\n-\tuint32_t data[5];\n-\tuint32_t res[3];\n+\tu32 data[5];\n+\tu32 res[3];\n };\n \n struct ipu_ch_param {\n@@ -239,8 +239,8 @@ unsigned char g_ipu_clk_enabled;\n struct clk *g_di_clk[2];\n struct clk *g_pixel_clk[2];\n unsigned char g_dc_di_assignment[10];\n-uint32_t g_channel_init_mask;\n-uint32_t g_channel_enable_mask;\n+u32 g_channel_init_mask;\n+u32 g_channel_enable_mask;\n \n static int ipu_dc_use_count;\n static int ipu_dp_use_count;\n@@ -252,28 +252,28 @@ u32 *ipu_dc_tmpl_reg;\n \n /* Static functions */\n \n-static inline void ipu_ch_param_set_high_priority(uint32_t ch)\n+static inline void ipu_ch_param_set_high_priority(u32 ch)\n {\n \tipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);\n };\n \n-static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)\n+static inline u32 channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)\n {\n-\treturn ((uint32_t)ch >> (6 * type)) & 0x3F;\n+\treturn ((u32)ch >> (6 * type)) & 0x3F;\n };\n \n /* Either DP BG or DP FG can be graphic window */\n-static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)\n+static inline int ipu_is_dp_graphic_chan(u32 dma_chan)\n {\n \treturn (dma_chan == 23 || dma_chan == 27);\n }\n \n-static inline int ipu_is_dmfc_chan(uint32_t dma_chan)\n+static inline int ipu_is_dmfc_chan(u32 dma_chan)\n {\n \treturn ((dma_chan >= 23) && (dma_chan <= 29));\n }\n \n-static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,\n+static inline void ipu_ch_param_set_buffer(u32 ch, int bufNum,\n \t\t\t\t\t dma_addr_t phyaddr)\n {\n \tipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,\n@@ -565,7 +565,7 @@ void ipu_dump_registers(void)\n int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)\n {\n \tint ret = 0;\n-\tuint32_t ipu_conf;\n+\tu32 ipu_conf;\n \n \tdebug(\"init channel = %d\\n\", IPU_CHAN_ID(channel));\n \n@@ -650,9 +650,9 @@ err:\n */\n void ipu_uninit_channel(ipu_channel_t channel)\n {\n-\tuint32_t reg;\n-\tuint32_t in_dma, out_dma = 0;\n-\tuint32_t ipu_conf;\n+\tu32 reg;\n+\tu32 in_dma, out_dma = 0;\n+\tu32 ipu_conf;\n \n \tif ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {\n \t\tdebug(\"Channel already uninitialized %d\\n\",\n@@ -791,13 +791,12 @@ static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,\n \tipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);\n }\n \n-static void ipu_ch_param_init(int ch, uint32_t pixel_fmt, uint32_t width,\n-\t\t\t uint32_t height, uint32_t stride, uint32_t u,\n-\t\t\t uint32_t v, uint32_t uv_stride, dma_addr_t addr0,\n-\t\t\t dma_addr_t addr1)\n+static void ipu_ch_param_init(int ch, u32 pixel_fmt, u32 width, u32 height,\n+\t\t\t u32 stride, u32 u, u32 v, u32 uv_stride,\n+\t\t\t dma_addr_t addr0, dma_addr_t addr1)\n {\n-\tuint32_t u_offset = 0;\n-\tuint32_t v_offset = 0;\n+\tu32 u_offset = 0;\n+\tu32 v_offset = 0;\n \tstruct ipu_ch_param params;\n \n \tmemset(¶ms, 0, sizeof(params));\n@@ -985,13 +984,12 @@ static void ipu_ch_param_init(int ch, uint32_t pixel_fmt, uint32_t width,\n * Return:\tReturns 0 on success or negative error code on fail\n */\n int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t\tuint32_t pixel_fmt, uint16_t width,\n-\t\t\t\tuint16_t height, uint32_t stride,\n-\t\t\t\tdma_addr_t phyaddr_0, dma_addr_t phyaddr_1,\n-\t\t\t\tuint32_t u, uint32_t v)\n+\t\t\t\tu32 pixel_fmt, u16 width, u16 height,\n+\t\t\t\tu32 stride, dma_addr_t phyaddr_0,\n+\t\t\t\tdma_addr_t phyaddr_1, u32 u, u32 v)\n {\n-\tuint32_t reg;\n-\tuint32_t dma_chan;\n+\tu32 reg;\n+\tu32 dma_chan;\n \n \tdma_chan = channel_2_dma(channel, type);\n \tif (!idma_is_valid(dma_chan))\n@@ -1039,9 +1037,9 @@ int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n */\n int32_t ipu_enable_channel(ipu_channel_t channel)\n {\n-\tuint32_t reg;\n-\tuint32_t in_dma;\n-\tuint32_t out_dma;\n+\tu32 reg;\n+\tu32 in_dma;\n+\tu32 out_dma;\n \n \tif (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {\n \t\tprintf(\"Warning: channel already enabled %d\\n\",\n@@ -1082,9 +1080,9 @@ int32_t ipu_enable_channel(ipu_channel_t channel)\n *\n */\n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t uint32_t bufNum)\n+\t\t\t u32 bufNum)\n {\n-\tuint32_t dma_ch = channel_2_dma(channel, type);\n+\tu32 dma_ch = channel_2_dma(channel, type);\n \n \tif (!idma_is_valid(dma_ch))\n \t\treturn;\n@@ -1114,9 +1112,9 @@ void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n */\n int32_t ipu_disable_channel(ipu_channel_t channel)\n {\n-\tuint32_t reg;\n-\tuint32_t in_dma;\n-\tuint32_t out_dma;\n+\tu32 reg;\n+\tu32 in_dma;\n+\tu32 out_dma;\n \n \tif ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {\n \t\tdebug(\"Channel already disabled %d\\n\", IPU_CHAN_ID(channel));\n@@ -1163,7 +1161,7 @@ int32_t ipu_disable_channel(ipu_channel_t channel)\n \treturn 0;\n }\n \n-uint32_t bytes_per_pixel(uint32_t fmt)\n+u32 bytes_per_pixel(u32 fmt)\n {\n \tswitch (fmt) {\n \tcase IPU_PIX_FMT_GENERIC: /*generic data */\n@@ -1196,7 +1194,7 @@ uint32_t bytes_per_pixel(uint32_t fmt)\n \treturn 0;\n }\n \n-ipu_color_space_t format_to_colorspace(uint32_t fmt)\n+ipu_color_space_t format_to_colorspace(u32 fmt)\n {\n \tswitch (fmt) {\n \tcase IPU_PIX_FMT_RGB666:\ndiff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c\nindex 178442a2bca..af6daec7f64 100644\n--- a/drivers/video/imx/ipu_disp.c\n+++ b/drivers/video/imx/ipu_disp.c\n@@ -399,13 +399,12 @@ static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,\n \t}\n }\n \n-int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n-\t\tuint32_t out_pixel_fmt)\n+int ipu_dp_init(ipu_channel_t channel, u32 in_pixel_fmt, u32 out_pixel_fmt)\n {\n \tint in_fmt, out_fmt;\n \tint dp;\n \tint partial = 0;\n-\tuint32_t reg;\n+\tu32 reg;\n \n \tif (channel == MEM_FG_SYNC) {\n \t\tdp = DP_SYNC;\n@@ -454,8 +453,7 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,\n \t ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {\n \t\tint red, green, blue;\n \t\tint y, u, v;\n-\t\tuint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &\n-\t\t\t\t 0xFFFFFFL;\n+\t\tu32 color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFFFFFFL;\n \n \t\tdebug(\"_ipu_dp_init color key 0x%x need change to yuv fmt!\\n\",\n \t\t color_key);\n@@ -584,8 +582,8 @@ void ipu_dc_uninit(int dc_chan)\n void ipu_dp_dc_enable(ipu_channel_t channel)\n {\n \tint di;\n-\tuint32_t reg;\n-\tuint32_t dc_chan;\n+\tu32 reg;\n+\tu32 dc_chan;\n \n \tif (channel == MEM_DC_SYNC)\n \t\tdc_chan = 1;\n@@ -625,9 +623,9 @@ static unsigned char dc_swap;\n \n void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)\n {\n-\tuint32_t reg;\n-\tuint32_t csc;\n-\tuint32_t dc_chan = 0;\n+\tu32 reg;\n+\tu32 csc;\n+\tu32 dc_chan = 0;\n \tint timeout = 50;\n \tint irq = 0;\n \n@@ -745,7 +743,7 @@ void ipu_init_dc_mappings(void)\n \tipu_dc_map_config(4, 2, 21, 0xFC);\n }\n \n-static int ipu_pixfmt_to_map(uint32_t fmt)\n+static int ipu_pixfmt_to_map(u32 fmt)\n {\n \tswitch (fmt) {\n \tcase IPU_PIX_FMT_GENERIC:\n@@ -801,17 +799,16 @@ static int ipu_pixfmt_to_map(uint32_t fmt)\n *\t\tfail.\n */\n \n-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,\n-\t\t\t uint16_t height, uint32_t pixel_fmt,\n-\t\t\t uint16_t h_start_width, uint16_t h_sync_width,\n-\t\t\t uint16_t h_end_width, uint16_t v_start_width,\n-\t\t\t uint16_t v_sync_width, uint16_t v_end_width,\n-\t\t\t uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)\n+int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,\n+\t\t\t u32 pixel_fmt, u16 h_start_width, u16 h_sync_width,\n+\t\t\t u16 h_end_width, u16 v_start_width,\n+\t\t\t u16 v_sync_width, u16 v_end_width, u32 v_to_h_sync,\n+\t\t\t ipu_di_signal_cfg_t sig)\n {\n-\tuint32_t reg;\n-\tuint32_t di_gen, vsync_cnt;\n-\tuint32_t div, rounded_pixel_clk;\n-\tuint32_t h_total, v_total;\n+\tu32 reg;\n+\tu32 di_gen, vsync_cnt;\n+\tu32 div, rounded_pixel_clk;\n+\tu32 h_total, v_total;\n \tint map;\n \tstruct clk *di_parent;\n \n@@ -1135,9 +1132,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,\n * Return:\tReturns 0 on success or negative error code on fail\n */\n int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n-\t\t\t\t uint8_t alpha)\n+\t\t\t\t u8 alpha)\n {\n-\tuint32_t reg;\n+\tu32 reg;\n \n \tunsigned char bg_chan;\n \n@@ -1162,8 +1159,7 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n \n \tif (enable) {\n \t\treg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;\n-\t\t__raw_writel(reg | ((uint32_t)alpha << 24),\n-\t\t\t DP_GRAPH_WIND_CTRL());\n+\t\t__raw_writel(reg | ((u32)alpha << 24), DP_GRAPH_WIND_CTRL());\n \n \t\treg = __raw_readl(DP_COM_CONF());\n \t\t__raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());\n@@ -1190,9 +1186,9 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n * Return:\tReturns 0 on success or negative error code on fail\n */\n int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n-\t\t\t uint32_t color_key)\n+\t\t\t u32 color_key)\n {\n-\tuint32_t reg;\n+\tu32 reg;\n \tint y, u, v;\n \tint red, green, blue;\n \ndiff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c\nindex 6b81d522041..6c271490ba1 100644\n--- a/drivers/video/imx/mxc_ipuv3_fb.c\n+++ b/drivers/video/imx/mxc_ipuv3_fb.c\n@@ -37,8 +37,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi);\n static int mxcfb_unmap_video_memory(struct fb_info *fbi);\n \n static struct fb_videomode const *gmode;\n-static uint8_t gdisp;\n-static uint32_t gpixfmt;\n+static u8 gdisp;\n+static u32 gpixfmt;\n \n static void fb_videomode_to_var(struct fb_var_screeninfo *var,\n \t\t\t\tconst struct fb_videomode *mode)\n@@ -75,9 +75,9 @@ struct mxcfb_info {\n \tdma_addr_t alpha_phy_addr1;\n \tvoid *alpha_virt_addr0;\n \tvoid *alpha_virt_addr1;\n-\tuint32_t alpha_mem_len;\n-\tuint32_t cur_ipu_buf;\n-\tuint32_t cur_ipu_alpha_buf;\n+\tu32 alpha_mem_len;\n+\tu32 cur_ipu_buf;\n+\tu32 cur_ipu_alpha_buf;\n \n \tu32 pseudo_palette[16];\n };\n@@ -89,9 +89,9 @@ static unsigned char g_dp_in_use;\n static struct fb_info *mxcfb_info[3];\n static int ext_clk_used;\n \n-static uint32_t bpp_to_pixfmt(struct fb_info *fbi)\n+static u32 bpp_to_pixfmt(struct fb_info *fbi)\n {\n-\tuint32_t pixfmt = 0;\n+\tu32 pixfmt = 0;\n \n \tdebug(\"bpp_to_pixfmt: %d\\n\", fbi->var.bits_per_pixel);\n \n@@ -180,7 +180,7 @@ static int mxcfb_set_par(struct fb_info *fbi)\n \tu32 mem_len;\n \tipu_di_signal_cfg_t sig_cfg;\n \tstruct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;\n-\tuint32_t out_pixel_fmt;\n+\tu32 out_pixel_fmt;\n \n \tipu_disable_channel(mxc_fbi->ipu_ch);\n \tipu_uninit_channel(mxc_fbi->ipu_ch);\n@@ -378,7 +378,7 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)\n \t}\n \n \tdebug(\"allocated fb @ paddr=0x%08X, size=%d.\\n\",\n-\t (uint32_t)fbi->fix.smem_start, fbi->fix.smem_len);\n+\t (u32)fbi->fix.smem_start, fbi->fix.smem_len);\n \n \tfbi->screen_size = fbi->fix.smem_len;\n \n@@ -451,7 +451,7 @@ extern struct clk *g_ipu_clk;\n *\n * Return:\tAppropriate error code to the kernel common code\n */\n-static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, uint8_t disp,\n+static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, u8 disp,\n \t\t struct fb_videomode const *mode)\n {\n \tstruct fb_info *fbi;\n@@ -536,8 +536,7 @@ void ipuv3_fb_shutdown(void)\n \t}\n }\n \n-int ipuv3_fb_init(struct fb_videomode const *mode, uint8_t disp,\n-\t\t uint32_t pixfmt)\n+int ipuv3_fb_init(struct fb_videomode const *mode, u8 disp, u32 pixfmt)\n {\n \tgmode = mode;\n \tgdisp = disp;\n", "prefixes": [ "v1", "3/7" ] }