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{ "id": 2175507, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175507/?format=api", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/1.0/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218104243.562667-6-ganboing@gmail.com>", "date": "2025-12-18T10:42:41", "name": "[v6,5/7] platform: generic: eswin: add EIC7700", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f2903a7f6cf2274e230e3c0e220dcbc015bd4c22", "submitter": { "id": 86401, "url": "http://patchwork.ozlabs.org/api/1.0/people/86401/?format=api", "name": "Bo Gan", "email": "ganboing@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20251218104243.562667-6-ganboing@gmail.com/mbox/", "series": [ { "id": 485819, "url": "http://patchwork.ozlabs.org/api/1.0/series/485819/?format=api", "date": "2025-12-18T10:42:37", "name": "Initial ESWIN/EIC7700 and Hifive P550 support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/485819/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175507/checks/", "tags": {}, "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=kqWwRNis;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=K2XklhFl;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Initial platform support for ESWIN Computing EIC7700 based\n on public SoC datasheet[1] and tested on HiFive Premier P550. Vendor\n U-boot/Linux\n boots fine, and I've tested Geekbench 6.5.0 Preview and got [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:432 listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n provider\n [ganboing(at)gmail.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Initial platform support for ESWIN Computing EIC7700 based on public SoC\ndatasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots\nfine, and I've tested Geekbench 6.5.0 Preview and got scores on par with\nthe vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and\nother boards will be implemented in subsequent commits. At this point,\nonly SoC-level warm reset is implemented.\n\nThe files and functions are intentionally named as eic770x in many places\nfor future enhancements to support the 2 die version of the same SoC,\nnamely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only\ndeals with the single die version, and the assumption is we can be either\ndie with id=0 or id=1, but there's only a single die in the system, or we\nare only using a single die out of 2. However, the way the SoC handles 2-\ndie greatly affects how we configure it in a 1-die setup. EIC770X address\nmap has die 0/1 memory regions interleaved (see comments in eic770x.c).\nIf only 1 die is connected or active, it creates holes in the address map\nfor those regions corresponding to the remote die. When speculative-\nexecution or HW prefetcher touches data-cacheable regions that happen to\nfall into those holes, it can trigger bus error. Specifically:\n\n - Remote (non-existent) die L3 zero device\n - Remote (non-existent) die cached memory region\n - Other holes in Memory Port\n\nTo make matters worse, EIC770X doesn't have cache coherent DMA, and due\nto the fact that the P550 core lacks Svpbmt, the SoC maps main memory\ntwice as different regions, so it can bypass cache and fetch the data\ndirectly from memory. In address space, we have two memory regions, one\nas cached, the other as uncached. Thus, we also need an extra PMP entry\nto protect OpenSBI blob from the uncached window. To do this, platform\ncode requires single_fw_region, otherwise, we'll run out of PMP entries.\n\nEIC770X also have several feature disable/enable CSRs accessible in M\nmode. By default many core features such as speculation and HW prefetch\nare disabled, and M mode software is responsible of enabling. Hence,\nintroduce 4 new build time tunable parameters to Kconfig, which reflects\nthe values get updated to those CSRs:\n - ESWIN_EIC770X_FEAT0_CFG\n - ESWIN_EIC770X_FEAT1_CFG\n - ESWIN_EIC770X_L1_HWPF_CFG\n - ESWIN_EIC770X_L2_HWPF_CFG\n\nThe default values are somewhat optimal for generic workloads. They are\ndumped when running SiFive's vendor OpenSBI, and in addition, with my\nown tuning to address the perf regression reported by drmpeg [3]\n\nTo build the firmware+u-boot blob, Use the following, and docs [4] for\ntesting it with UART boot without flashing:\n\nmake FW_TEXT_START=0x80000000 \\\n FW_PAYLOAD_OFFSET=0x200000 \\\n FW_PAYLOAD_PATH=u-boot-nodtb.bin \\\n FW_PAYLOAD_FDT_ADDR=0xf8000000 \\\n FW_FDT_PATH=u-boot.dtb\n\n[1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual\n[2] https://github.com/geerlingguy/sbc-reviews/issues/82\n[3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15\n[4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md\n\nSigned-off-by: Bo Gan <ganboing@gmail.com>\n---\n platform/generic/Kconfig | 5 +\n platform/generic/configs/defconfig | 1 +\n platform/generic/eswin/Kconfig | 29 ++\n platform/generic/eswin/eic770x.c | 403 +++++++++++++++++++++++\n platform/generic/eswin/objects.mk | 10 +\n platform/generic/include/eswin/eic770x.h | 79 +++++\n 6 files changed, 527 insertions(+)\n create mode 100644 platform/generic/eswin/Kconfig\n create mode 100644 platform/generic/eswin/eic770x.c\n create mode 100644 platform/generic/eswin/objects.mk\n create mode 100644 platform/generic/include/eswin/eic770x.h", "diff": "diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig\nindex b1808012..716fab42 100644\n--- a/platform/generic/Kconfig\n+++ b/platform/generic/Kconfig\n@@ -48,6 +48,10 @@ config PLATFORM_ANDES_QILAI\n \tselect ANDES_SBI\n \tdefault n\n \n+config PLATFORM_ESWIN_EIC770X\n+\tbool \"ESWIN EIC770X support\"\n+\tdefault n\n+\n config PLATFORM_OPENHWGROUP_OPENPITON\n \tbool \"OpenHWGroup Openpiton support\"\n \tdefault n\n@@ -98,6 +102,7 @@ config PLATFORM_SPACEMIT_K1\n \tdefault n\n \n source \"$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig\"\n+source \"$(OPENSBI_SRC_DIR)/platform/generic/eswin/Kconfig\"\n source \"$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig\"\n \n endif\ndiff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig\nindex d0e2ec26..aab1560f 100644\n--- a/platform/generic/configs/defconfig\n+++ b/platform/generic/configs/defconfig\n@@ -1,6 +1,7 @@\n CONFIG_PLATFORM_ALLWINNER_D1=y\n CONFIG_PLATFORM_ANDES_AE350=y\n CONFIG_PLATFORM_ANDES_QILAI=y\n+CONFIG_PLATFORM_ESWIN_EIC770X=y\n CONFIG_PLATFORM_OPENHWGROUP_ARIANE=y\n CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y\n CONFIG_PLATFORM_RENESAS_RZFIVE=y\ndiff --git a/platform/generic/eswin/Kconfig b/platform/generic/eswin/Kconfig\nnew file mode 100644\nindex 00000000..84d0f43a\n--- /dev/null\n+++ b/platform/generic/eswin/Kconfig\n@@ -0,0 +1,29 @@\n+# SPDX-License-Identifier: BSD-2-Clause\n+\n+config ESWIN_EIC770X_FEAT0_CFG\n+\tint \"ESWIN EIC7700X Feature Disable 0 CSR Configuration\"\n+\tdefault 0x4000\n+\thelp\n+\t CSR Value to initialize EIC770X_FEAT0 (0x7c1) with.\n+\t Refer to EIC770X SoC TRM for recommendations.\n+\n+config ESWIN_EIC770X_FEAT1_CFG\n+\tint \"ESWIN EIC7700X Feature Disable 1 CSR Configuration\"\n+\tdefault 0x80\n+\thelp\n+\t CSR Value to initialize EIC770X_FEAT1 (0x7c2) with.\n+\t Refer to EIC770X SoC TRM for recommendations.\n+\n+config ESWIN_EIC770X_L1_HWPF_CFG\n+\tint \"ESWIN EIC7700X L1 HW Prefetcher CSR Configuration\"\n+\tdefault 0x1005c1be649\n+\thelp\n+\t CSR Value to initialize EIC770X_L1_HWPF (0x7c3) with.\n+\t Refer to EIC770X SoC TRM for recommendations.\n+\n+config ESWIN_EIC770X_L2_HWPF_CFG\n+\tint \"ESWIN EIC7700X L2 HW Prefetcher CSR Configuration\"\n+\tdefault 0x929f\n+\thelp\n+\t CSR Value to initialize EIC770X_L2_HWPF (0x7c4) with.\n+\t Refer to EIC770X SoC TRM for recommendations.\ndiff --git a/platform/generic/eswin/eic770x.c b/platform/generic/eswin/eic770x.c\nnew file mode 100644\nindex 00000000..bce53a19\n--- /dev/null\n+++ b/platform/generic/eswin/eic770x.c\n@@ -0,0 +1,403 @@\n+/*\n+ * SPDX-License-Identifier: BSD-2-Clause\n+ *\n+ * Copyright (c) 2025 Bo Gan <ganboing@gmail.com>\n+ *\n+ */\n+\n+#include <platform_override.h>\n+#include <sbi/riscv_io.h>\n+#include <sbi/sbi_console.h>\n+#include <sbi/sbi_system.h>\n+#include <sbi/sbi_math.h>\n+#include <sbi/sbi_hart_pmp.h>\n+#include <sbi/sbi_hart_protection.h>\n+#include <eswin/eic770x.h>\n+\n+static struct sbi_hart_protection eswin_eic7700_pmp_protection;\n+\n+static int eic770x_system_reset_check(u32 type, u32 reason)\n+{\n+\tswitch (type) {\n+\tcase SBI_SRST_RESET_TYPE_COLD_REBOOT:\n+\tcase SBI_SRST_RESET_TYPE_WARM_REBOOT:\n+\t\treturn 1;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static void eic770x_system_reset(u32 type, u32 reason)\n+{\n+\tswitch (type) {\n+\tcase SBI_SRST_RESET_TYPE_COLD_REBOOT:\n+\tcase SBI_SRST_RESET_TYPE_WARM_REBOOT:\n+\t\tsbi_printf(\"%s: resetting...\\n\", __func__);\n+\t\twritel(EIC770X_SYSCRG_RST_VAL, (void *)EIC770X_SYSCRG_RST);\n+\t}\n+\n+\tsbi_hart_hang();\n+}\n+\n+static struct sbi_system_reset_device *board_reset = NULL;\n+static struct sbi_system_reset_device eic770x_reset = {\n+\t.name = \"eic770x_reset\",\n+\t.system_reset_check = eic770x_system_reset_check,\n+\t.system_reset = eic770x_system_reset,\n+};\n+\n+#define add_root_mem_chk(...) do { \\\n+\trc = sbi_domain_root_add_memrange(__VA_ARGS__); \\\n+\tif (rc) \\\n+\t\treturn rc; \\\n+} while (0)\n+\n+/**\n+ * EIC7700 special arrangement of PMP entries:\n+ *\n+ * We have to use extra PMPs to block data cacheable regions that\n+ * that doesn't belong to the current hart's die in order to prevent\n+ * speculative accesses or HW prefetcher from generating bus error:\n+ *\n+ * \tbus error of cause event: 9, accrued: 0x220,\n+ *\tphysical address: 0x24ffffffa0\n+ *\n+ * The data cacheable regions (per datasheet) include:\n+ *\n+ * - [0x1a000000, 0x1a400000) -- Die 0 L3 zero device\n+ * - [0x3a000000, 0x3a400000) -- Die 1 L3 zero device\n+ * - [0x80000000, 0x80_00000000) -- memory port\n+ *\n+ * To make the blocker effective for M mode too, the extra PMPs need\n+ * LOCK bit to be set, and once set, we can't change them later.\n+ * We also have to to use 1 extra PMP to protect OpenSBI in uncached\n+ * memory. EIC770X maps main memory (DRAM) twice -- one in memory\n+ * port (cached), the other in system port (uncached). P550 doesn't\n+ * support Svpbmt, so EIC770X use the uncached window to handle DMA\n+ * that are cache incoherent -- pretty much all peripherals\n+ *\n+ * Final PMP configuration:\n+ *\n+ * From die 0 point of view, block\n+ * - [0x3a000000, 0x3a400000) -- Die 1 L3 zero device\n+ * - [0x10_00000000, 0x80_00000000) -- Die 1 cached mem + holes\n+ *\n+ * Root domain Harts:\n+ * PMP[0]: [ 0x80000000, 0x80080000) ____ Firmware in cached mem\n+ * PMP[1]: [0xc0_00000000, 0xc0_00080000) ____ Firmware in uncached\n+ * PMP[2]: [ 0x3a000000, 0x3a400000) L___ Die 1 L3 zero device\n+ * PMP[3]: [ 0x2000000 0x2010000) ____ CLINT\n+ * PMP[4]: [ 0x0, 0x10_00000000) _RWX P550/System/Die 0 cached mem\n+ * PMP[5]: <Free>\n+ * PMP[6]: [ 0x0, 0x80_00000000) L___ P550/System/Memory Port\n+ * PMP[7]: [ 0x0, 0xffffffffffffffff] _RWX Everything\n+ *\n+ * From die 1 point of view, block\n+ * - [0x1a000000, 0x1a400000) -- Die 0 L3 zero device\n+ * - [0x80000000, 0x20_00000000) -- Die 0 cached mem + holes\n+ * - [0x30_00000000, 0x80_00000000) -- other holes in Memory port\n+ *\n+ * Root domain Harts:\n+ * PMP[0]: [0x20_00000000, 0x20_00080000) ____ Firmware in cached mem\n+ * PMP[1]: [0xe0_00000000, 0xe0_00080000) ____ Firmware in uncached\n+ * PMP[2]: [ 0x1a000000, 0x1a400000) L___ Die 0 L3 zero dev\n+ * PMP[3]: [ 0x22000000 0x22010000) ____ CLINT\n+ * PMP[4]: [ 0x0, 0x80000000) _RWX Die 0/1 P550 internal\n+ * PMP[5]: [0x20_00000000, 0x30_00000000) _RWX Die 1 cached memory\n+ * PMP[6]: [ 0x0, 0x80_00000000) L___ P550/System/Memory Port\n+ * PMP[7]: [ 0x0, 0xffffffffffffffff] _RWX Everything\n+ *\n+ * EIC770X memory port map:\n+ * P550 Internal\n+ * ├─ 0x0000_0000 - 0x2000_0000 die 0 internal\n+ * └─ 0x2000_0000 - 0x4000_0000 die 1 internal\n+ * System Port 0\n+ * ├─ 0x4000_0000 - 0x6000_0000 die 0 low MMIO\n+ * └─ 0x6000_0000 - 0x8000_0000 die 1 low MMIO\n+ * Memory Port\n+ * ├─ 0x8000_0000 - 0x10_8000_0000 die 0 memory (cached)\n+ * ├─ 0x20_0000_0000 - 0x30_0000_0000 die 1 memory (cached)\n+ * └─ 0x40_0000_0000 - 0x60_0000_0000 interleaved memory (cached)\n+ * System Port 1\n+ * ├─ 0x80_0000_0000 - 0xa0_0000_0000 die 0 high MMIO\n+ * ├─ 0xa0_0000_0000 - 0xc0_0000_0000 die 1 high MMIO\n+ * ├─ 0xc0_0000_0000 - 0xd0_0000_0000 die 0 memory (uncached)\n+ * ├─ 0xe0_0000_0000 - 0xf0_0000_0000 die 1 memory (uncached)\n+ * ├─ 0x100_0000_0000 - 0x120_0000_0000 interleaved memory (uncached)\n+ * └─ ...\n+ *\n+ * In early_init, add memory regions such that lib/ code has the knowledge\n+ * of blocked ranges. When the driver code inserts new regions, lib/ code\n+ * can optimize away unnecessary ones. Next, in final_init, we program the\n+ * PMPs to a default state that'll keep ourselves functional (CLINT/...\n+ * accessible). Later, in pmp_configure, do the actual configuration of\n+ * PMP, using domain memory regions and permissions.\n+ */\n+\n+static int eswin_eic7700_early_init(bool cold_boot)\n+{\n+\tstruct sbi_scratch *scratch = sbi_scratch_thishart_ptr();\n+\tint rc;\n+\n+\tif (!cold_boot)\n+\t\treturn generic_early_init(cold_boot);\n+\n+\tif (board_reset)\n+\t\tsbi_system_reset_add_device(board_reset);\n+\tsbi_system_reset_add_device(&eic770x_reset);\n+\n+\t/* Enable bus blocker */\n+\twritel(1, (void*)EIC770X_TL64D2D_OUT);\n+\twritel(1, (void*)EIC770X_TL256D2D_OUT);\n+\twritel(1, (void*)EIC770X_TL256D2D_IN);\n+\tasm volatile (\"fence o, rw\");\n+\n+\t/* Block firmware in uncached memory */\n+\tadd_root_mem_chk(EIC770X_TO_UNCACHED(\n+\t\t\t scratch->fw_start),\n+\t\t\t 1UL << log2roundup(scratch->fw_size),\n+\t\t\t 1UL << log2roundup(scratch->fw_size),\n+\t\t\t(SBI_DOMAIN_MEMREGION_M_READABLE |\n+\t\t\t SBI_DOMAIN_MEMREGION_M_WRITABLE |\n+\t\t\t SBI_DOMAIN_MEMREGION_M_EXECUTABLE |\n+\t\t\t SBI_DOMAIN_MEMREGION_MMIO |\n+\t\t\t SBI_DOMAIN_MEMREGION_FW));\n+\n+\t/* Allow SURW of P550 + System Port */\n+\tadd_root_mem_chk(0,\n+\t\t\t EIC770X_MEMPORT_BASE,\n+\t\t\t EIC770X_MEMPORT_BASE,\n+\t\t\t(SBI_DOMAIN_MEMREGION_MMIO |\n+\t\t\t SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));\n+\n+\tif (current_hart_die()) {\n+\t\t/* Allow SURWX of die 1 cached memory */\n+\t\tadd_root_mem_chk(EIC770X_D1_MEM_BASE,\n+\t\t\t\t EIC770X_D1_MEM_SIZE,\n+\t\t\t\t EIC770X_D1_MEM_SIZE,\n+\t\t\t\t(SBI_DOMAIN_MEMREGION_M_READABLE |\n+\t\t\t\t SBI_DOMAIN_MEMREGION_M_WRITABLE |\n+\t\t\t\t SBI_DOMAIN_MEMREGION_SU_RWX));\n+\t} else {\n+\t\t/* Allow SURWX of P550 + System Port + die 0 cached memory */\n+\t\tadd_root_mem_chk(0,\n+\t\t\t\t EIC770X_D0_MEM_LIMIT,\n+\t\t\t\t EIC770X_D0_MEM_LIMIT,\n+\t\t\t\t(SBI_DOMAIN_MEMREGION_M_READABLE |\n+\t\t\t\t SBI_DOMAIN_MEMREGION_M_WRITABLE |\n+\t\t\t\t SBI_DOMAIN_MEMREGION_SU_RWX));\n+\t}\n+\n+\t/* Block P550 + System Port 0 + Memory Port (enforced) */\n+\tadd_root_mem_chk(0,\n+\t\t\t EIC770X_MEMPORT_LIMIT,\n+\t\t\t EIC770X_MEMPORT_LIMIT,\n+\t\t\t(SBI_DOMAIN_MEMREGION_MMIO |\n+\t\t\t SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS));\n+\n+\trc = sbi_hart_protection_register(&eswin_eic7700_pmp_protection);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn generic_early_init(cold_boot);\n+}\n+\n+#define PMP_FW_START 0\n+#define PMP_FW_COUNT 2\n+#define PMP_RESERVED_A 2\n+#define PMP_FREE_A_START 3\n+#define PMP_FREE_A_COUNT 3\n+#define PMP_RESERVED_B 6\n+#define PMP_FREE_B_START 7\n+#define PMP_FREE_B_COUNT 1\n+\n+static int eswin_eic7700_final_init(bool cold_boot)\n+{\n+\t/**\n+\t * For both dies after final_init:\n+\t *\n+\t * PMP[0]: Protect OpenSBI in cached memory\n+\t * PMP[1]: Protect OpenSBI in uncached memory\n+\t * PMP[2]: Block remote die P550 L3 Zero Device\n+\t * PMP[3-5]: <Free ranges A>\n+\t * PMP[5]: Temporary enable P550 + System Port\n+\t * PMP[6]: Block all P550 + System + Memory Port\n+\t * PMP[7-7]: <Free ranges B>\n+\t */\n+\tstruct sbi_domain_memregion *reg;\n+\tunsigned int pmp_idx = PMP_FW_START,\n+\t\t pmp_max = PMP_FW_START + PMP_FW_COUNT;\n+\tint rc;\n+\n+\n+\t/**\n+\t * Do generic_final_init stuff first, because it touchs FDT.\n+\t * After final_init, we'll block entire memory port with the\n+\t * LOCK bit set, which means we can't access memory outside\n+\t * of [fw_start, fw_start + fw_size). The FDT could very well\n+\t * reside outside of firmware region. Later, pmp_configure()\n+\t * may unblock it with some preceding entries for root domain\n+\t * harts. It may not unblock it, however, for non-root harts.\n+\t */\n+\trc = generic_final_init(cold_boot);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Process firmware regions */\n+\tsbi_domain_for_each_memregion(&root, reg) {\n+\t\tif (!SBI_DOMAIN_MEMREGION_IS_FIRMWARE(reg->flags))\n+\t\t\tcontinue;\n+\n+\t\tif (pmp_idx >= pmp_max) {\n+\t\t\tsbi_printf(\"%s: insufficient FW PMP entries\\n\",\n+\t\t\t\t __func__);\n+\t\t\treturn SBI_EFAIL;\n+\t\t}\n+\t\tpmp_set(pmp_idx++, sbi_domain_get_oldpmp_flags(reg),\n+\t\t\treg->base, reg->order);\n+\t}\n+\n+\tpmp_set(PMP_RESERVED_A, PMP_L, EIC770X_L3_ZERO_REMOTE,\n+\t\t\t log2roundup(EIC770X_L3_ZERO_SIZE));\n+\t/**\n+\t * Enable P550 internal + System Port, so OpenSBI can access\n+\t * CLINT/PLIC/UART. Might be overwritten in pmp_configure.\n+\t */\n+\tpmp_set(PMP_FREE_A_START + PMP_FREE_A_COUNT - 1, 0, 0,\n+\t\tlog2roundup(EIC770X_MEMPORT_BASE));\n+\n+\tpmp_set(PMP_RESERVED_B, PMP_L, 0,\n+\t\tlog2roundup(EIC770X_MEMPORT_LIMIT));\n+\t/**\n+\t * These must come after the setup of PMP, as we are about to\n+\t * enable speculation and HW prefetcher bits\n+\t */\n+\tcsr_write(EIC770X_CSR_FEAT0, CONFIG_ESWIN_EIC770X_FEAT0_CFG);\n+\tcsr_write(EIC770X_CSR_FEAT1, CONFIG_ESWIN_EIC770X_FEAT1_CFG);\n+\tcsr_write(EIC770X_CSR_L1_HWPF, CONFIG_ESWIN_EIC770X_L1_HWPF_CFG);\n+\tcsr_write(EIC770X_CSR_L2_HWPF, CONFIG_ESWIN_EIC770X_L2_HWPF_CFG);\n+\n+\treturn 0;\n+}\n+\n+static int eswin_eic7700_pmp_configure(struct sbi_scratch *scratch)\n+{\n+\tstruct sbi_domain *dom = sbi_domain_thishart_ptr();\n+\tstruct sbi_domain_memregion *reg, *prev = NULL;\n+\tunsigned int pmp_idx, pmp_max;\n+\tunsigned int i, j;\n+\n+\t/* Process the first free range A [3-5] */\n+\tpmp_idx = PMP_FREE_A_START,\n+\tpmp_max = PMP_FREE_A_START + PMP_FREE_A_COUNT;\n+\n+\tsbi_domain_for_each_memregion_idx(dom, reg, i) {\n+\t\tif (SBI_DOMAIN_MEMREGION_IS_FIRMWARE(reg->flags))\n+\t\t\tcontinue;\n+\n+\t\t/**\n+\t\t * This must be the one blocking P550 + System Port +\n+\t\t * Memory Port we setup in early_init, or a superset\n+\t\t * of it. If seen, break, and program the rest in\n+\t\t * free range B.\n+\t\t */\n+\t\tif (reg->base == 0 &&\n+\t\t reg->order >= log2roundup(EIC770X_MEMPORT_LIMIT))\n+\t\t\tbreak;\n+\n+\t\t/**\n+\t\t * Relaxation:\n+\t\t * Treat a previous region with SURW as SURWX if the\n+\t\t * current has SURWX, and current region with MMIO\n+\t\t * if previous has MMIO, and see if it can be merged.\n+\t\t * This saves 1 PMP entry on die 0/\n+\t\t */\n+\t\tif (prev && sbi_domain_memregion_is_subset(prev, reg) &&\n+\t\t (reg->flags | SBI_DOMAIN_MEMREGION_MMIO) ==\n+\t\t (prev->flags | SBI_DOMAIN_MEMREGION_SU_EXECUTABLE))\n+\t\t\tpmp_idx--;\n+\n+\t\tif (pmp_idx >= pmp_max)\n+\t\t\tgoto no_more_pmp;\n+\n+\t\tpmp_set(pmp_idx++, sbi_domain_get_oldpmp_flags(reg),\n+\t\t\treg->base, reg->order);\n+\t\tprev = reg;\n+\t}\n+\t/* Disable the rest */\n+\twhile (pmp_idx < pmp_max)\n+\t\tpmp_disable(pmp_idx++);\n+\n+\t/* Process the second free range B [7-7] */\n+\tpmp_idx = PMP_FREE_B_START,\n+\tpmp_max = PMP_FREE_B_START + PMP_FREE_B_COUNT;\n+\n+\tsbi_domain_for_each_memregion_idx(dom, reg, j) {\n+\t\tif (i >= j)\n+\t\t\tcontinue;\n+\n+\t\tif (pmp_idx >= pmp_max)\n+\t\t\tgoto no_more_pmp;\n+\n+\t\tpmp_set(pmp_idx++, sbi_domain_get_oldpmp_flags(reg),\n+\t\t\treg->base, reg->order);\n+\t}\n+\t/* Disable the rest */\n+\twhile (pmp_idx < pmp_max)\n+\t\tpmp_disable(pmp_idx++);\n+\n+\tsbi_hart_pmp_fence();\n+\treturn 0;\n+no_more_pmp:\n+\tsbi_printf(\"%s: insufficient PMP entries\\n\", __func__);\n+\treturn SBI_EFAIL;\n+}\n+\n+static void eswin_eic7700_pmp_unconfigure(struct sbi_scratch *scratch)\n+{\n+\t/* Enable P550 internal + System Port */\n+\tpmp_set(PMP_FREE_A_START + PMP_FREE_A_COUNT - 1, 0, 0,\n+\t\tlog2roundup(EIC770X_MEMPORT_BASE));\n+\n+\tfor (unsigned int i = 0; i < PMP_FREE_A_COUNT - 1; i++)\n+\t\tpmp_disable(i + PMP_FREE_A_START);\n+\n+\tfor (unsigned int i = 0; i < PMP_FREE_B_COUNT; i++)\n+\t\tpmp_disable(i + PMP_FREE_B_START);\n+}\n+\n+static struct sbi_hart_protection eswin_eic7700_pmp_protection = {\n+\t.name = \"eic7700_pmp\",\n+\t.rating = -1UL,\n+\t.configure = eswin_eic7700_pmp_configure,\n+\t.unconfigure = eswin_eic7700_pmp_unconfigure,\n+};\n+\n+static bool eswin_eic7700_single_fw_region(void)\n+{\n+\treturn true;\n+}\n+\n+static int eswin_eic7700_platform_init(const void *fdt, int nodeoff,\n+\t\t\t\t\tconst struct fdt_match *match)\n+{\n+\tconst struct eic770x_board_override *board_override = match->data;\n+\n+\tgeneric_platform_ops.early_init = eswin_eic7700_early_init;\n+\tgeneric_platform_ops.final_init = eswin_eic7700_final_init;\n+\tgeneric_platform_ops.single_fw_region = eswin_eic7700_single_fw_region;\n+\n+\tif (board_override)\n+\t\tboard_reset = board_override->reset_dev;\n+\treturn 0;\n+}\n+\n+static const struct fdt_match eswin_eic7700_match[] = {\n+\t{ .compatible = \"eswin,eic7700\" },\n+\t{ },\n+};\n+\n+const struct fdt_driver eswin_eic7700 = {\n+\t.match_table = eswin_eic7700_match,\n+\t.init = eswin_eic7700_platform_init,\n+};\ndiff --git a/platform/generic/eswin/objects.mk b/platform/generic/eswin/objects.mk\nnew file mode 100644\nindex 00000000..be5420ce\n--- /dev/null\n+++ b/platform/generic/eswin/objects.mk\n@@ -0,0 +1,10 @@\n+#\n+# SPDX-License-Identifier: BSD-2-Clause\n+#\n+# Copyright (C) 2025 Bo Gan <ganboing@gmail.com>\n+#\n+\n+ifeq ($(PLATFORM_RISCV_XLEN), 64)\n+carray-platform_override_modules-$(CONFIG_PLATFORM_ESWIN_EIC770X) += eswin_eic7700\n+platform-objs-$(CONFIG_PLATFORM_ESWIN_EIC770X) += eswin/eic770x.o\n+endif\ndiff --git a/platform/generic/include/eswin/eic770x.h b/platform/generic/include/eswin/eic770x.h\nnew file mode 100644\nindex 00000000..b1994669\n--- /dev/null\n+++ b/platform/generic/include/eswin/eic770x.h\n@@ -0,0 +1,79 @@\n+/*\n+ * SPDX-License-Identifier: BSD-2-Clause\n+ *\n+ * Copyright (c) 2025 Bo Gan <ganboing@gmail.com>\n+ *\n+ */\n+\n+#ifndef __EIC770X_H__\n+#define __EIC770X_H__\n+\n+#include <sbi/riscv_asm.h>\n+\n+struct eic770x_board_override {\n+\tstruct sbi_system_reset_device *reset_dev;\n+};\n+\n+/* CSRs */\n+#define EIC770X_CSR_BRPREDICT\t0x7c0\n+#define EIC770X_CSR_FEAT0\t0x7c1\n+#define EIC770X_CSR_FEAT1\t0x7c2\n+#define EIC770X_CSR_L1_HWPF\t0x7c3\n+#define EIC770X_CSR_L2_HWPF\t0x7c4\n+\n+/* Hart ID to core/die conversion */\n+#define CPU_CORE_BITS\t\t2\n+#define CPU_CORE_MASK\t\t((1 << CPU_CORE_BITS) - 1)\n+#define CPU_DIE_SHIFT\t\tCPU_CORE_BITS\n+#define CPU_DIE_BITS\t\t1\n+#define CPU_DIE_MASK\t\t((1 << CPU_DIE_BITS) - 1)\n+\n+#define hart_core(i)\t\t((i) & CPU_CORE_MASK)\n+#define hart_die(i)\t\t(((i) >> CPU_DIE_SHIFT) & CPU_DIE_MASK)\n+#define current_hart_core()\thart_core(current_hartid())\n+#define current_hart_die()\thart_die(current_hartid())\n+\n+/* P550 Internal and System Port 0 */\n+#define EIC770X_P550INT_SIZE\t0x20000000UL\n+#define EIC770X_P550INT_BASE(d)\t(0UL + EIC770X_P550INT_SIZE * (d))\n+#define EIC770X_P550INT_LOCAL\tEIC770X_P550INT_BASE(current_hart_die())\n+#define EIC770X_TL64D2D_OUT\t(EIC770X_P550INT_LOCAL + 0x200000)\n+#define EIC770X_TL256D2D_OUT\t(EIC770X_P550INT_LOCAL + 0x202000)\n+#define EIC770X_TL256D2D_IN\t(EIC770X_P550INT_LOCAL + 0x204000)\n+#define EIC770X_L3_ZERO_SIZE\t0x400000UL\n+#define EIC770X_L3_ZERO_BASE(d)\t(EIC770X_P550INT_BASE(d) + 0x1a000000)\n+#define EIC770X_L3_ZERO_LOCAL\tEIC770X_L3_ZERO_BASE(current_hart_die())\n+#define EIC770X_L3_ZERO_REMOTE\tEIC770X_L3_ZERO_BASE(1 - current_hart_die())\n+\n+#define EIC770X_SYSPORT_SIZE\t0x20000000UL\n+#define EIC770X_SYSPORT_BASE(d)\t(0x40000000UL + EIC770X_SYSPORT_SIZE * (d))\n+#define EIC770X_SYSPORT_LOCAL\tEIC770X_SYSPORT_BASE(current_hart_die())\n+#define EIC770X_SYSCRG\t\t(EIC770X_SYSPORT_LOCAL + 0x11828000UL)\n+#define EIC770X_SYSCRG_RST\t(EIC770X_SYSCRG + 0x300UL)\n+#define EIC770X_SYSCRG_RST_VAL\t0x1AC0FFE6UL\n+\n+/* Memory Ports */\n+#define EIC770X_MEMPORT_BASE\t0x0080000000UL // 2G\n+#define EIC770X_MEMPORT_SIZE\t0x7f80000000UL // +510G\n+#define EIC770X_MEMPORT_LIMIT\t(EIC770X_MEMPORT_BASE + EIC770X_MEMPORT_SIZE)\n+#define EIC770X_D0_MEM_BASE\t0x0080000000UL // 2G\n+#define EIC770X_D0_MEM_SIZE\t0x0f80000000UL // +62G\n+#define EIC770X_D0_MEM_LIMIT\t(EIC770X_D0_MEM_BASE + EIC770X_D0_MEM_SIZE)\n+#define EIC770X_D1_MEM_BASE\t0x2000000000UL // 128G\n+#define EIC770X_D1_MEM_SIZE\t0x1000000000UL // +64G\n+#define EIC770X_D1_MEM_LIMIT\t(EIC770X_D1_MEM_BASE + EIC770X_D1_MEM_SIZE)\n+#define EIC770X_CACHED_BASE\t(current_hart_die() ? \\\n+\t\t\t\tEIC770X_D1_MEM_BASE : \\\n+\t\t\t\tEIC770X_D0_MEM_BASE)\n+\n+/* Uncached memory mapped in System Port 1 */\n+#define EIC770X_D0_UC_BASE\t0xc000000000UL\n+#define EIC770X_D1_UC_BASE\t0xe000000000UL\n+#define EIC770X_UNCACHED_BASE\t(current_hart_die() ? \\\n+\t\t\t\tEIC770X_D1_UC_BASE : \\\n+\t\t\t\tEIC770X_D0_UC_BASE)\n+\n+#define EIC770X_TO_UNCACHED(x)\t((x) - EIC770X_CACHED_BASE + \\\n+\t\t\t\tEIC770X_UNCACHED_BASE)\n+\n+#endif\n", "prefixes": [ "v6", "5/7" ] }