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GET /api/1.0/patches/2175434/?format=api
{ "id": 2175434, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175434/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218062643.624796-6-zhenzhong.duan@intel.com>", "date": "2025-12-18T06:26:26", "name": "[v6,5/9] vfio/iommufd: Add IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR flag support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3fcce172ae8b3775c68785dbf66f6eba0ecbbc86", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/1.0/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218062643.624796-6-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 485789, "url": "http://patchwork.ozlabs.org/api/1.0/series/485789/?format=api", "date": "2025-12-18T06:26:21", "name": "vfio: relax the vIOMMU check", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/485789/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175434/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=Sf6ijzyd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX13J20Nsz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 17:29:16 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vW7UG-0003NO-M6; Thu, 18 Dec 2025 01:27:44 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1vW7UC-0003N2-6j\n for qemu-devel@nongnu.org; Thu, 18 Dec 2025 01:27:40 -0500", "from mgamail.intel.com ([198.175.65.18])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1vW7UA-00018G-Dk\n for qemu-devel@nongnu.org; Thu, 18 Dec 2025 01:27:39 -0500", "from orviesa005.jf.intel.com ([10.64.159.145])\n by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Dec 2025 22:27:35 -0800", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Dec 2025 22:27:32 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1766039258; x=1797575258;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=8pHmfZaBwbWLgM/IjiqWNY/mA7gOe1aG5iy7P69PVJA=;\n b=Sf6ijzydBgiArtM1g9DGLZEvRZuLy0caBrNpspRyLcZhhrl0Ob/gBBot\n pWc0kisJxLLkbmULgTsQ1OoAUMVnTtTQGDyW/rJXeXOPxszRRcCYe01C0\n dtcw6/vitzojKoDxo5nmJnenAjRltZH6dQMgC2+OULb2CHhMqCAWn7Qgx\n DKaxtrFrsOt4HaM7Di3NEp1Ce0zlEyg336Dw+yjLhwtp4H/cpBEHJF58/\n gzpedSCRnJO4nRQCmso0UiCM/9XWhL1scWx237bFRgeFH/vhQIVWCeWDb\n EYQ42KSN9ys5v2ho75YL47iGRJgWAqnwMot/gUI2GcXYV3bf73KzMU2J0 g==;", "X-CSE-ConnectionGUID": [ "+SAvyB0zSp2wS52q9aJUjA==", "/hWPKtPdQi20cxkh9I19lQ==" ], "X-CSE-MsgGUID": [ "UCRi5kOjQW6EKwWgWKxDBA==", "FJsvAo1aQtWgjcunhR3Cfw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11645\"; a=\"68028539\"", "E=Sophos;i=\"6.21,156,1763452800\"; d=\"scan'208\";a=\"68028539\"", "E=Sophos;i=\"6.21,156,1763452800\"; d=\"scan'208\";a=\"203569894\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@eviden.com,\n eric.auger@redhat.com, joao.m.martins@oracle.com, avihaih@nvidia.com,\n xudong.hao@intel.com, giovanni.cabiddu@intel.com, rohith.s.r@intel.com,\n mark.gross@intel.com, arjan.van.de.ven@intel.com,\n Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v6 5/9] vfio/iommufd: Add IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR\n flag support", "Date": "Thu, 18 Dec 2025 01:26:26 -0500", "Message-ID": "<20251218062643.624796-6-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.1", "In-Reply-To": "<20251218062643.624796-1-zhenzhong.duan@intel.com>", "References": "<20251218062643.624796-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.18;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Pass IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR when doing the last dirty\nbitmap query right before unmap, no PTEs flushes. This accelerates the\nquery without issue because unmap will tear down the mapping anyway.\n\nCo-developed-by: Joao Martins <joao.m.martins@oracle.com>\nSigned-off-by: Joao Martins <joao.m.martins@oracle.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Cédric Le Goater <clg@redhat.com>\nReviewed-by: Yi Liu <yi.l.liu@intel.com>\nTested-by: Xudong Hao <xudong.hao@intel.com>\nTested-by: Giovannio Cabiddu <giovanni.cabiddu@intel.com>\nTested-by: Rohith S R <rohith.s.r@intel.com>\n---\n include/system/iommufd.h | 2 +-\n backends/iommufd.c | 5 +++--\n hw/vfio/iommufd.c | 5 +++--\n backends/trace-events | 2 +-\n 4 files changed, 8 insertions(+), 6 deletions(-)", "diff": "diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex a659f36a20..767a8e4cb6 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -64,7 +64,7 @@ bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id,\n bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id,\n uint64_t iova, ram_addr_t size,\n uint64_t page_size, uint64_t *data,\n- Error **errp);\n+ uint64_t flags, Error **errp);\n bool iommufd_backend_invalidate_cache(IOMMUFDBackend *be, uint32_t id,\n uint32_t data_type, uint32_t entry_len,\n uint32_t *entry_num, void *data,\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex fdfb7c9d67..086bd67aea 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -361,7 +361,7 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be,\n uint32_t hwpt_id,\n uint64_t iova, ram_addr_t size,\n uint64_t page_size, uint64_t *data,\n- Error **errp)\n+ uint64_t flags, Error **errp)\n {\n int ret;\n struct iommu_hwpt_get_dirty_bitmap get_dirty_bitmap = {\n@@ -371,11 +371,12 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be,\n .length = size,\n .page_size = page_size,\n .data = (uintptr_t)data,\n+ .flags = flags,\n };\n \n ret = ioctl(be->fd, IOMMU_HWPT_GET_DIRTY_BITMAP, &get_dirty_bitmap);\n trace_iommufd_backend_get_dirty_bitmap(be->fd, hwpt_id, iova, size,\n- page_size, ret ? errno : 0);\n+ flags, page_size, ret ? errno : 0);\n if (ret) {\n error_setg_errno(errp, errno,\n \"IOMMU_HWPT_GET_DIRTY_BITMAP (iova: 0x%\"HWADDR_PRIx\ndiff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c\nindex 7eaa8b3372..63f8442865 100644\n--- a/hw/vfio/iommufd.c\n+++ b/hw/vfio/iommufd.c\n@@ -74,7 +74,8 @@ static int iommufd_cdev_unmap(const VFIOContainer *bcontainer,\n if (iotlb && vfio_container_dirty_tracking_is_started(bcontainer)) {\n if (!vfio_container_devices_dirty_tracking_is_supported(bcontainer) &&\n bcontainer->dirty_pages_supported) {\n- ret = vfio_container_query_dirty_bitmap(bcontainer, iova, size, 0,\n+ ret = vfio_container_query_dirty_bitmap(bcontainer, iova, size,\n+ IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR,\n iotlb->translated_addr,\n &local_err);\n if (ret) {\n@@ -231,7 +232,7 @@ static int iommufd_query_dirty_bitmap(const VFIOContainer *bcontainer,\n if (!iommufd_backend_get_dirty_bitmap(container->be, hwpt->hwpt_id,\n iova, size, page_size,\n (uint64_t *)vbmap->bitmap,\n- errp)) {\n+ backend_flag, errp)) {\n return -EINVAL;\n }\n }\ndiff --git a/backends/trace-events b/backends/trace-events\nindex 56132d3fd2..e1992ba12f 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -19,5 +19,5 @@ iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) \" iommufd=%d ioas=%d\"\n iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t out_hwpt_id, int ret) \" iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%\"PRIx64\" out_hwpt=%u (%d)\"\n iommufd_backend_free_id(int iommufd, uint32_t id, int ret) \" iommufd=%d id=%d (%d)\"\n iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) \" iommufd=%d hwpt=%u enable=%d (%d)\"\n-iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, uint64_t size, uint64_t page_size, int ret) \" iommufd=%d hwpt=%u iova=0x%\"PRIx64\" size=0x%\"PRIx64\" page_size=0x%\"PRIx64\" (%d)\"\n+iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) \" iommufd=%d hwpt=%u iova=0x%\"PRIx64\" size=0x%\"PRIx64\" flags=0x%\"PRIx64\" page_size=0x%\"PRIx64\" (%d)\"\n iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_type, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t data_ptr, int ret) \" iommufd=%d id=%u data_type=%u entry_len=%u entry_num=%u done_num=%u data_ptr=0x%\"PRIx64\" (%d)\"\n", "prefixes": [ "v6", "5/9" ] }