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GET /api/1.0/patches/2175425/?format=api
{ "id": 2175425, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175425/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218061557.1999367-4-varadarajan.narayanan@oss.qualcomm.com>", "date": "2025-12-18T06:15:54", "name": "[RESEND,v2,3/6] phy: qcom: Add QMP USB PHY driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ae12364b31623ac5fecf16a0f2af2d2e6ac77e46", "submitter": { "id": 92283, "url": "http://patchwork.ozlabs.org/api/1.0/people/92283/?format=api", "name": "Varadarajan Narayanan", "email": "varadarajan.narayanan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.0/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251218061557.1999367-4-varadarajan.narayanan@oss.qualcomm.com/mbox/", "series": [ { "id": 485788, "url": "http://patchwork.ozlabs.org/api/1.0/series/485788/?format=api", "date": "2025-12-18T06:15:51", "name": "Enable fastboot support for IPQ9574 based boards", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485788/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175425/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UQqjeBQt;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=JTfzGgRD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"UQqjeBQt\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"JTfzGgRD\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX0n34y77z1y2F\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 17:16:55 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id DC1ED83CB9;\n\tThu, 18 Dec 2025 07:16:31 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 5AE6483CB1; Thu, 18 Dec 2025 07:16:30 +0100 (CET)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 811AD83CAA\n for <u-boot@lists.denx.de>; Thu, 18 Dec 2025 07:16:25 +0100 (CET)", "from pps.filterd (m0279867.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 5BI1YYrQ4147962\n for <u-boot@lists.denx.de>; Thu, 18 Dec 2025 06:16:23 GMT", "from mail-pj1-f70.google.com (mail-pj1-f70.google.com\n [209.85.216.70])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b40u79wr7-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Thu, 18 Dec 2025 06:16:23 +0000 (GMT)", "by mail-pj1-f70.google.com with SMTP id\n 98e67ed59e1d1-34ac819b2f2so463541a91.0\n for <u-boot@lists.denx.de>; Wed, 17 Dec 2025 22:16:23 -0800 (PST)", "from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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AGHT+IFZqVzG7HeD1nTxz3oDG2xCOrI0E9b+2jysamFwf0dX2lZcsNhBXXEbs5iVtz8ZTUd58RU+pg==", "From": "Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>", "To": "trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, peng.fan@nxp.com, jh80.chung@samsung.com,\n lukma@denx.de, varadarajan.narayanan@oss.qualcomm.com,\n marek.vasut+renesas@mailbox.org, michal.simek@amd.com,\n alexeymin@postmarketos.org, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[RESEND v2 3/6] phy: qcom: Add QMP USB PHY driver", "Date": "Thu, 18 Dec 2025 11:45:54 +0530", "Message-Id": "<20251218061557.1999367-4-varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20251218061557.1999367-1-varadarajan.narayanan@oss.qualcomm.com>", "References": "<20251218061557.1999367-1-varadarajan.narayanan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": 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engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0\n impostorscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180049", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Port Qualcomm QMP USB PHY driver from Linux. This PHY is available in\nmany Qcom SoCs. Enabled and tested the driver on IPQ9574.\n\nSigned-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\n---\n drivers/phy/qcom/Kconfig | 8 +\n drivers/phy/qcom/Makefile | 1 +\n drivers/phy/qcom/phy-qcom-qmp-common.h | 62 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v4.h | 17 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v4.h | 34 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v5.h | 36 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v6.h | 17 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v7.h | 17 +\n drivers/phy/qcom/phy-qcom-qmp-pcs-v7.h | 32 +\n .../phy/qcom/phy-qcom-qmp-qserdes-com-v7.h | 87 +\n .../phy/qcom/phy-qcom-qmp-qserdes-txrx-v7.h | 78 +\n drivers/phy/qcom/phy-qcom-qmp-usb.c | 2114 +++++++++++++++++\n drivers/phy/qcom/phy-qcom-qmp.h | 15 +\n 13 files changed, 2518 insertions(+)\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-common.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v5.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v6.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v7.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v7.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v7.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v7.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-usb.c", "diff": "diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig\nindex 0dd69f7ffd0..ea4d52248ab 100644\n--- a/drivers/phy/qcom/Kconfig\n+++ b/drivers/phy/qcom/Kconfig\n@@ -24,6 +24,14 @@ config PHY_QCOM_QMP_UFS\n \thelp\n \t Enable this to support the UFS QMP PHY on various Qualcomm chipsets.\n \n+config PHY_QCOM_QMP_USB\n+\ttristate \"Qualcomm QMP USB PHY Driver\"\n+\tselect GENERIC_PHY\n+\tdefault PHY_QCOM_QMP\n+\thelp\n+\t Enable this to support the QMP USB PHY transceiver that is used\n+\t with USB3 controllers on Qualcomm chips.\n+\n config PHY_QCOM_QUSB2\n \ttristate \"Qualcomm USB QUSB2 PHY driver\"\n \tdepends on PHY && ARCH_SNAPDRAGON\ndiff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile\nindex 1c4e7d8d391..ef83a122234 100644\n--- a/drivers/phy/qcom/Makefile\n+++ b/drivers/phy/qcom/Makefile\n@@ -2,6 +2,7 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o\n obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o\n obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o\n obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o\n+obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o\n obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o\n obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o\n obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-common.h b/drivers/phy/qcom/phy-qcom-qmp-common.h\nnew file mode 100644\nindex 00000000000..71356fb7dd0\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-common.h\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_COMMON_H_\n+#define QCOM_PHY_QMP_COMMON_H_\n+\n+struct qmp_phy_init_tbl {\n+\tunsigned int offset;\n+\tunsigned int val;\n+\tchar *name;\n+\t/*\n+\t * mask of lanes for which this register is written\n+\t * for cases when second lane needs different values\n+\t */\n+\tu8 lane_mask;\n+};\n+\n+#define QMP_PHY_INIT_CFG(o, v)\t\t\\\n+\t{\t\t\t\t\\\n+\t\t.offset = o,\t\t\\\n+\t\t.val = v,\t\t\\\n+\t\t.name = #o,\t\t\\\n+\t\t.lane_mask = 0xff,\t\\\n+\t}\n+\n+#define QMP_PHY_INIT_CFG_LANE(o, v, l)\t\\\n+\t{\t\t\t\t\\\n+\t\t.offset = o,\t\t\\\n+\t\t.val = v,\t\t\\\n+\t\t.name = #o,\t\t\\\n+\t\t.lane_mask = l,\t\t\\\n+\t}\n+\n+static inline void qmp_configure_lane(struct udevice *dev, void __iomem *base,\n+\t\t\t\t const struct qmp_phy_init_tbl tbl[],\n+\t\t\t\t int num, u8 lane_mask)\n+{\n+\tint i;\n+\tconst struct qmp_phy_init_tbl *t = tbl;\n+\n+\tif (!t)\n+\t\treturn;\n+\n+\tfor (i = 0; i < num; i++, t++) {\n+\t\tif (!(t->lane_mask & lane_mask))\n+\t\t\tcontinue;\n+\n+\t\tdev_dbg(dev, \"Writing Reg: %s Offset: 0x%04x Val: 0x%02x\\n\",\n+\t\t\tt->name, t->offset, t->val);\n+\t\twritel(t->val, base + t->offset);\n+\t}\n+}\n+\n+static inline void qmp_configure(struct udevice *dev, void __iomem *base,\n+\t\t\t\t const struct qmp_phy_init_tbl tbl[], int num)\n+{\n+\tqmp_configure_lane(dev, base, tbl, num, 0xff);\n+}\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v4.h\nnew file mode 100644\nindex 00000000000..e256a089f22\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v4.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_MISC_V4_H_\n+#define QCOM_PHY_QMP_PCS_MISC_V4_H_\n+\n+/* Only for QMP V4 PHY - PCS_MISC registers */\n+#define QPHY_V4_PCS_MISC_TYPEC_CTRL\t\t\t0x00\n+#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL\t\t0x04\n+#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1\t\t0x08\n+#define QPHY_V4_PCS_MISC_CLAMP_ENABLE\t\t\t0x0c\n+#define QPHY_V4_PCS_MISC_TYPEC_STATUS\t\t\t0x10\n+#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS\t\t0x14\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v4.h\nnew file mode 100644\nindex 00000000000..d7fd4ac0fc5\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v4.h\n@@ -0,0 +1,34 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_USB_V4_H_\n+#define QCOM_PHY_QMP_PCS_USB_V4_H_\n+\n+/* Only for QMP V4 PHY - USB3 PCS registers */\n+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1\t\t0x000\n+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS\t\t0x004\n+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL\t\t0x008\n+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2\t\t0x00c\n+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS\t0x010\n+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR\t\t0x014\n+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL\t0x018\n+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART\t\t0x01c\n+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL\t\t0x020\n+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START\t0x024\n+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME\t\t0x028\n+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME\t\t0x02c\n+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME\t\t0x030\n+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2\t0x034\n+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2\t0x038\n+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L\t\t0x03c\n+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H\t\t0x040\n+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD\t\t0x044\n+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY\t\t0x048\n+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH\t\t0x04c\n+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL\t\t0x050\n+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL\t0x054\n+#define QPHY_V4_PCS_USB3_TEST_CONTROL\t\t\t0x058\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v5.h\nnew file mode 100644\nindex 00000000000..73de626223e\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v5.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_\n+#define QCOM_PHY_QMP_PCS_USB_V5_H_\n+\n+/* Only for QMP V5 PHY - USB3 have different offsets than V4 */\n+#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1\t\t0x000\n+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS\t\t0x004\n+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL\t\t0x008\n+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2\t\t0x00c\n+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS\t0x010\n+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR\t\t0x014\n+#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL\t0x018\n+#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART\t\t0x01c\n+#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL\t\t0x020\n+#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START\t0x024\n+#define QPHY_V5_PCS_USB3_LFPS_CONFIG1\t\t\t0x028\n+#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME\t\t0x02c\n+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME\t\t0x030\n+#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME\t\t0x034\n+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2\t0x038\n+#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2\t0x03c\n+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L\t\t0x040\n+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H\t\t0x044\n+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD\t\t0x048\n+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY\t\t0x04c\n+#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH\t\t0x050\n+#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL\t\t0x054\n+#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL\t0x058\n+#define QPHY_V5_PCS_USB3_TEST_CONTROL\t\t\t0x05c\n+#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL\t\t0x060\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v6.h\nnew file mode 100644\nindex 00000000000..df670143feb\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v6.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_\n+#define QCOM_PHY_QMP_PCS_USB_V6_H_\n+\n+#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1\t\t0x00\n+#define QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL\t\t0x08\n+#define QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR\t\t0x14\n+#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL\t0x18\n+#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2\t0x3c\n+#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L\t\t0x40\n+#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H\t\t0x44\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v7.h\nnew file mode 100644\nindex 00000000000..24368d45ae7\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-usb-v7.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_\n+#define QCOM_PHY_QMP_PCS_USB_V7_H_\n+\n+#define QPHY_V7_PCS_USB3_POWER_STATE_CONFIG1\t\t0x00\n+#define QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL\t\t0x08\n+#define QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR\t\t0x14\n+#define QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL\t0x18\n+#define QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2\t0x3c\n+#define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L\t\t0x40\n+#define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H\t\t0x44\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v7.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v7.h\nnew file mode 100644\nindex 00000000000..c7759892ed2\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v7.h\n@@ -0,0 +1,32 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_V7_H_\n+#define QCOM_PHY_QMP_PCS_V7_H_\n+\n+/* Only for QMP V7 PHY - USB/PCIe PCS registers */\n+#define QPHY_V7_PCS_SW_RESET\t\t\t0x000\n+#define QPHY_V7_PCS_PCS_STATUS1\t\t\t0x014\n+#define QPHY_V7_PCS_POWER_DOWN_CONTROL\t\t0x040\n+#define QPHY_V7_PCS_START_CONTROL\t\t0x044\n+#define QPHY_V7_PCS_POWER_STATE_CONFIG1\t\t0x090\n+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1\t\t0x0c4\n+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2\t\t0x0c8\n+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3\t\t0x0cc\n+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6\t\t0x0d8\n+#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1\t\t0x0dc\n+#define QPHY_V7_PCS_RX_SIGDET_LVL\t\t0x188\n+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L\t0x190\n+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H\t0x194\n+#define QPHY_V7_PCS_RATE_SLEW_CNTRL1\t\t0x198\n+#define QPHY_V7_PCS_CDR_RESET_TIME\t\t0x1b0\n+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1\t0x1c0\n+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2\t0x1c4\n+#define QPHY_V7_PCS_PCS_TX_RX_CONFIG\t\t0x1d0\n+#define QPHY_V7_PCS_EQ_CONFIG1\t\t\t0x1dc\n+#define QPHY_V7_PCS_EQ_CONFIG2\t\t\t0x1e0\n+#define QPHY_V7_PCS_EQ_CONFIG5\t\t\t0x1ec\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v7.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v7.h\nnew file mode 100644\nindex 00000000000..7430f492147\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v7.h\n@@ -0,0 +1,87 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_\n+#define QCOM_PHY_QMP_QSERDES_COM_V7_H_\n+\n+/* Only for QMP V7 PHY - QSERDES COM registers */\n+\n+#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1\t\t\t0x00\n+#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1\t\t\t0x04\n+#define QSERDES_V7_COM_CP_CTRL_MODE1\t\t\t\t0x10\n+#define QSERDES_V7_COM_PLL_RCTRL_MODE1\t\t\t\t0x14\n+#define QSERDES_V7_COM_PLL_CCTRL_MODE1\t\t\t\t0x18\n+#define QSERDES_V7_COM_CORECLK_DIV_MODE1\t\t\t0x1c\n+#define QSERDES_V7_COM_LOCK_CMP1_MODE1\t\t\t\t0x20\n+#define QSERDES_V7_COM_LOCK_CMP2_MODE1\t\t\t\t0x24\n+#define QSERDES_V7_COM_DEC_START_MODE1\t\t\t\t0x28\n+#define QSERDES_V7_COM_DEC_START_MSB_MODE1\t\t\t0x2c\n+#define QSERDES_V7_COM_DIV_FRAC_START1_MODE1\t\t\t0x30\n+#define QSERDES_V7_COM_DIV_FRAC_START2_MODE1\t\t\t0x34\n+#define QSERDES_V7_COM_DIV_FRAC_START3_MODE1\t\t\t0x38\n+#define QSERDES_V7_COM_HSCLK_SEL_1\t\t\t\t0x3c\n+#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1\t\t\t0x40\n+#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1\t\t\t0x44\n+#define QSERDES_V7_COM_VCO_TUNE1_MODE1\t\t\t\t0x48\n+#define QSERDES_V7_COM_VCO_TUNE2_MODE1\t\t\t\t0x4c\n+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1\t\t0x50\n+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1\t\t0x54\n+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0\t\t0x58\n+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0\t\t0x5c\n+#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0\t\t\t0x60\n+#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0\t\t\t0x64\n+#define QSERDES_V7_COM_CP_CTRL_MODE0\t\t\t\t0x70\n+#define QSERDES_V7_COM_PLL_RCTRL_MODE0\t\t\t\t0x74\n+#define QSERDES_V7_COM_PLL_CCTRL_MODE0\t\t\t\t0x78\n+#define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0\t\t\t0x7c\n+#define QSERDES_V7_COM_LOCK_CMP1_MODE0\t\t\t\t0x80\n+#define QSERDES_V7_COM_LOCK_CMP2_MODE0\t\t\t\t0x84\n+#define QSERDES_V7_COM_DEC_START_MODE0\t\t\t\t0x88\n+#define QSERDES_V7_COM_DEC_START_MSB_MODE0\t\t\t0x8c\n+#define QSERDES_V7_COM_DIV_FRAC_START1_MODE0\t\t\t0x90\n+#define QSERDES_V7_COM_DIV_FRAC_START2_MODE0\t\t\t0x94\n+#define QSERDES_V7_COM_DIV_FRAC_START3_MODE0\t\t\t0x98\n+#define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1\t\t\t0x9c\n+#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0\t\t\t0xa0\n+#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0\t\t\t0xa4\n+#define QSERDES_V7_COM_VCO_TUNE1_MODE0\t\t\t\t0xa8\n+#define QSERDES_V7_COM_VCO_TUNE2_MODE0\t\t\t\t0xac\n+#define QSERDES_V7_COM_BG_TIMER\t\t\t\t\t0xbc\n+#define QSERDES_V7_COM_SSC_EN_CENTER\t\t\t\t0xc0\n+#define QSERDES_V7_COM_SSC_ADJ_PER1\t\t\t\t0xc4\n+#define QSERDES_V7_COM_SSC_PER1\t\t\t\t\t0xcc\n+#define QSERDES_V7_COM_SSC_PER2\t\t\t\t\t0xd0\n+#define QSERDES_V7_COM_PLL_POST_DIV_MUX\t\t\t\t0xd8\n+#define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN\t\t\t0xdc\n+#define QSERDES_V7_COM_CLK_ENABLE1\t\t\t\t0xe0\n+#define QSERDES_V7_COM_SYS_CLK_CTRL\t\t\t\t0xe4\n+#define QSERDES_V7_COM_SYSCLK_BUF_ENABLE\t\t\t0xe8\n+#define QSERDES_V7_COM_PLL_IVCO\t\t\t\t\t0xf4\n+#define QSERDES_V7_COM_PLL_IVCO_MODE1\t\t\t\t0xf8\n+#define QSERDES_V7_COM_SYSCLK_EN_SEL\t\t\t\t0x110\n+#define QSERDES_V7_COM_RESETSM_CNTRL\t\t\t\t0x118\n+#define QSERDES_V7_COM_LOCK_CMP_EN\t\t\t\t0x120\n+#define QSERDES_V7_COM_LOCK_CMP_CFG\t\t\t\t0x124\n+#define QSERDES_V7_COM_VCO_TUNE_CTRL\t\t\t\t0x13c\n+#define QSERDES_V7_COM_VCO_TUNE_MAP\t\t\t\t0x140\n+#define QSERDES_V7_COM_VCO_TUNE_INITVAL2\t\t\t0x148\n+#define QSERDES_V7_COM_VCO_TUNE_MAXVAL2\t\t\t\t0x158\n+#define QSERDES_V7_COM_CLK_SELECT\t\t\t\t0x164\n+#define QSERDES_V7_COM_CORE_CLK_EN\t\t\t\t0x170\n+#define QSERDES_V7_COM_CMN_CONFIG_1\t\t\t\t0x174\n+#define QSERDES_V7_COM_SVS_MODE_CLK_SEL\t\t\t\t0x17c\n+#define QSERDES_V7_COM_CMN_MISC_1\t\t\t\t0x184\n+#define QSERDES_V7_COM_CMN_MODE\t\t\t\t\t0x188\n+#define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL\t\t\t0x198\n+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1\t\t\t0x1a4\n+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2\t\t\t0x1a8\n+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3\t\t\t0x1ac\n+#define QSERDES_V7_COM_ADDITIONAL_MISC\t\t\t\t0x1b4\n+#define QSERDES_V7_COM_ADDITIONAL_MISC_2\t\t\t0x1b8\n+#define QSERDES_V7_COM_ADDITIONAL_MISC_3\t\t\t0x1bc\n+#define QSERDES_V7_COM_CMN_STATUS\t\t\t\t0x1d0\n+#define QSERDES_V7_COM_C_READY_STATUS\t\t\t\t0x1f8\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v7.h\nnew file mode 100644\nindex 00000000000..91f865b1134\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v7.h\n@@ -0,0 +1,78 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V7_H_\n+#define QCOM_PHY_QMP_QSERDES_TXRX_V7_H_\n+\n+#define QSERDES_V7_TX_CLKBUF_ENABLE\t\t\t\t0x08\n+#define QSERDES_V7_TX_RESET_TSYNC_EN\t\t\t\t0x1c\n+#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN\t\t\t0x20\n+#define QSERDES_V7_TX_TX_BAND\t\t\t\t\t0x24\n+#define QSERDES_V7_TX_INTERFACE_SELECT\t\t\t\t0x2c\n+#define QSERDES_V7_TX_RES_CODE_LANE_TX\t\t\t\t0x34\n+#define QSERDES_V7_TX_RES_CODE_LANE_RX\t\t\t\t0x38\n+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX\t\t\t0x3c\n+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX\t\t\t0x40\n+#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN\t\t0x60\n+#define QSERDES_V7_TX_BIST_PATTERN7\t\t\t\t0x7c\n+#define QSERDES_V7_TX_LANE_MODE_1\t\t\t\t0x84\n+#define QSERDES_V7_TX_LANE_MODE_2\t\t\t\t0x88\n+#define QSERDES_V7_TX_LANE_MODE_3\t\t\t\t0x8c\n+#define QSERDES_V7_TX_LANE_MODE_4\t\t\t\t0x90\n+#define QSERDES_V7_TX_LANE_MODE_5\t\t\t\t0x94\n+#define QSERDES_V7_TX_RCV_DETECT_LVL_2\t\t\t\t0xa4\n+#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN\t\t\t\t0xc0\n+#define QSERDES_V7_TX_TX_INTERFACE_MODE\t\t\t\t0xc4\n+#define QSERDES_V7_TX_VMODE_CTRL1\t\t\t\t0xc8\n+#define QSERDES_V7_TX_PI_QEC_CTRL\t\t\t\t0xe4\n+\n+#define QSERDES_V7_RX_UCDR_FO_GAIN\t\t\t\t0x08\n+#define QSERDES_V7_RX_UCDR_SO_GAIN\t\t\t\t0x14\n+#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN\t\t\t0x30\n+#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE\t\t0x34\n+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW\t\t\t0x3c\n+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH\t\t\t0x40\n+#define QSERDES_V7_RX_UCDR_PI_CONTROLS\t\t\t\t0x44\n+#define QSERDES_V7_RX_UCDR_SB2_THRESH1\t\t\t\t0x4c\n+#define QSERDES_V7_RX_UCDR_SB2_THRESH2\t\t\t\t0x50\n+#define QSERDES_V7_RX_UCDR_SB2_GAIN1\t\t\t\t0x54\n+#define QSERDES_V7_RX_UCDR_SB2_GAIN2\t\t\t\t0x58\n+#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE\t\t\t0x60\n+#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH\t\t\t0xcc\n+#define QSERDES_V7_RX_VGA_CAL_CNTRL1\t\t\t\t0xd4\n+#define QSERDES_V7_RX_VGA_CAL_CNTRL2\t\t\t\t0xd8\n+#define QSERDES_V7_RX_GM_CAL\t\t\t\t\t0xdc\n+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2\t\t\t0xec\n+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3\t\t\t0xf0\n+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4\t\t\t0xf4\n+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW\t\t\t0xf8\n+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH\t\t\t0xfc\n+#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1\t\t0x110\n+#define QSERDES_V7_RX_SIDGET_ENABLES\t\t\t\t0x118\n+#define QSERDES_V7_RX_SIGDET_CNTRL\t\t\t\t0x11c\n+#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL\t\t\t0x124\n+#define QSERDES_V7_RX_RX_MODE_00_LOW\t\t\t\t0x15c\n+#define QSERDES_V7_RX_RX_MODE_00_HIGH\t\t\t\t0x160\n+#define QSERDES_V7_RX_RX_MODE_00_HIGH2\t\t\t\t0x164\n+#define QSERDES_V7_RX_RX_MODE_00_HIGH3\t\t\t\t0x168\n+#define QSERDES_V7_RX_RX_MODE_00_HIGH4\t\t\t\t0x16c\n+#define QSERDES_V7_RX_RX_MODE_01_LOW\t\t\t\t0x170\n+#define QSERDES_V7_RX_RX_MODE_01_HIGH\t\t\t\t0x174\n+#define QSERDES_V7_RX_RX_MODE_01_HIGH2\t\t\t\t0x178\n+#define QSERDES_V7_RX_RX_MODE_01_HIGH3\t\t\t\t0x17c\n+#define QSERDES_V7_RX_RX_MODE_01_HIGH4\t\t\t\t0x180\n+#define QSERDES_V7_RX_RX_MODE_10_LOW\t\t\t\t0x184\n+#define QSERDES_V7_RX_RX_MODE_10_HIGH\t\t\t\t0x188\n+#define QSERDES_V7_RX_RX_MODE_10_HIGH2\t\t\t\t0x18c\n+#define QSERDES_V7_RX_RX_MODE_10_HIGH3\t\t\t\t0x190\n+#define QSERDES_V7_RX_RX_MODE_10_HIGH4\t\t\t\t0x194\n+#define QSERDES_V7_RX_DFE_EN_TIMER\t\t\t\t0x1a0\n+#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET\t\t\t0x1a4\n+#define QSERDES_V7_RX_DCC_CTRL1\t\t\t\t\t0x1a8\n+#define QSERDES_V7_RX_VTH_CODE\t\t\t\t\t0x1b0\n+#define QSERDES_V7_RX_SIGDET_CAL_CTRL1\t\t\t\t0x1e4\n+#define QSERDES_V7_RX_SIGDET_CAL_TRIM\t\t\t\t0x1f8\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-usb.c b/drivers/phy/qcom/phy-qcom-qmp-usb.c\nnew file mode 100644\nindex 00000000000..0d6a9da174b\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-usb.c\n@@ -0,0 +1,2114 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <clk.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <dm/device_compat.h>\n+#include <dm/devres.h>\n+#include <generic-phy.h>\n+#include <malloc.h>\n+#include <reset.h>\n+\n+#include <asm/io.h>\n+#include <linux/bitops.h>\n+#include <linux/clk-provider.h>\n+#include <linux/delay.h>\n+#include <linux/iopoll.h>\n+#include <linux/ioport.h>\n+\n+#include \"phy-qcom-qmp-common.h\"\n+\n+#include \"phy-qcom-qmp.h\"\n+#include \"phy-qcom-qmp-pcs-misc-v3.h\"\n+#include \"phy-qcom-qmp-pcs-misc-v4.h\"\n+#include \"phy-qcom-qmp-pcs-usb-v4.h\"\n+#include \"phy-qcom-qmp-pcs-usb-v5.h\"\n+#include \"phy-qcom-qmp-pcs-usb-v6.h\"\n+#include \"phy-qcom-qmp-pcs-usb-v7.h\"\n+\n+#include \"phy-qcom-qmp-pcs-v4.h\"\n+#include \"phy-qcom-qmp-pcs-v5.h\"\n+#include \"phy-qcom-qmp-pcs-v6.h\"\n+#include \"phy-qcom-qmp-pcs-v7.h\"\n+#include \"phy-qcom-qmp-qserdes-com-v4.h\"\n+#include \"phy-qcom-qmp-qserdes-com-v5.h\"\n+#include \"phy-qcom-qmp-qserdes-com-v6.h\"\n+#include \"phy-qcom-qmp-qserdes-com-v7.h\"\n+#include \"phy-qcom-qmp-qserdes-txrx-v4.h\"\n+#include \"phy-qcom-qmp-qserdes-txrx-v5.h\"\n+#include \"phy-qcom-qmp-qserdes-txrx-v6.h\"\n+#include \"phy-qcom-qmp-qserdes-txrx-v7.h\"\n+\n+#define SW_RESET\t\t\t\tBIT(0)\n+/* QPHY_POWER_DOWN_CONTROL */\n+#define SW_PWRDN\t\t\t\tBIT(0)\n+/* QPHY_START_CONTROL bits */\n+#define SERDES_START\t\t\t\tBIT(0)\n+#define PCS_START\t\t\t\tBIT(1)\n+/* QPHY_PCS_READY_STATUS bit */\n+#define PCS_READY\t\t\t\tBIT(0)\n+\n+#define PHY_INIT_COMPLETE_TIMEOUT\t\t10000\n+\n+/* set of registers with offsets different per-PHY */\n+enum qphy_reg_layout {\n+\t/* PCS registers */\n+\tQPHY_SW_RESET,\n+\tQPHY_START_CTRL,\n+\tQPHY_PCS_STATUS,\n+\tQPHY_PCS_AUTONOMOUS_MODE_CTRL,\n+\tQPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,\n+\tQPHY_PCS_POWER_DOWN_CONTROL,\n+\tQPHY_PCS_MISC_CLAMP_ENABLE,\n+\t/* Keep last to ensure regs_layout arrays are properly initialized */\n+\tQPHY_LAYOUT_SIZE\n+};\n+\n+static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V2_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V2_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V2_PCS_USB_PCS_STATUS,\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V2_PCS_POWER_DOWN_CONTROL,\n+};\n+\n+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V3_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V3_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V3_PCS_PCS_STATUS,\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V3_PCS_POWER_DOWN_CONTROL,\n+\t[QPHY_PCS_MISC_CLAMP_ENABLE]\t= QPHY_V3_PCS_MISC_CLAMP_ENABLE,\n+};\n+\n+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V4_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V4_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V4_PCS_PCS_STATUS1,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V4_PCS_POWER_DOWN_CONTROL,\n+\n+\t/* In PCS_USB */\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,\n+\t[QPHY_PCS_MISC_CLAMP_ENABLE]\t= QPHY_V4_PCS_MISC_CLAMP_ENABLE,\n+};\n+\n+static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V5_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V5_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V5_PCS_PCS_STATUS1,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V5_PCS_POWER_DOWN_CONTROL,\n+\n+\t/* In PCS_USB */\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,\n+};\n+\n+static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V6_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V6_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V6_PCS_PCS_STATUS1,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V6_PCS_POWER_DOWN_CONTROL,\n+\n+\t/* In PCS_USB */\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,\n+};\n+\n+static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {\n+\t[QPHY_SW_RESET]\t\t\t= QPHY_V7_PCS_SW_RESET,\n+\t[QPHY_START_CTRL]\t\t= QPHY_V7_PCS_START_CONTROL,\n+\t[QPHY_PCS_STATUS]\t\t= QPHY_V7_PCS_PCS_STATUS1,\n+\t[QPHY_PCS_POWER_DOWN_CONTROL]\t= QPHY_V7_PCS_POWER_DOWN_CONTROL,\n+\n+\t/* In PCS_USB */\n+\t[QPHY_PCS_AUTONOMOUS_MODE_CTRL]\t= QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,\n+\t[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,\n+};\n+\n+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),\n+\t/* PLL and Loop filter settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),\n+\t/* SSC settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),\n+\t/* PLL and Loop filter settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),\n+\t/* SSC settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),\n+};\n+\n+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),\n+};\n+\n+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),\n+\t/* PLL and Loop filter settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),\n+\t/* SSC settings */\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),\n+};\n+\n+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),\n+};\n+\n+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),\n+\tQMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),\n+};\n+\n+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {\n+\t/* FLL settings */\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),\n+\n+\t/* Lock Det settings */\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),\n+\tQMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),\n+};\n+\n+static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xc4),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x89),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),\n+};\n+\n+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),\n+};\n+\n+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),\n+};\n+\n+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),\n+};\n+\n+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {\n+\t/* FLL settings */\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),\n+\n+\t/* Lock Det settings */\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),\n+\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),\n+\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),\n+\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+\tQMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),\n+};\n+\n+static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),\n+};\n+\n+static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0xf2),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+};\n+\n+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),\n+};\n+\n+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),\n+};\n+\n+static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xec),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x19),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),\n+};\n+\n+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),\n+};\n+\n+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+};\n+\n+static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+\tQMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),\n+};\n+\n+static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),\n+};\n+\n+static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),\n+};\n+\n+static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),\n+\tQMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),\n+};\n+\n+static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),\n+};\n+\n+static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),\n+\tQMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),\n+};\n+\n+struct qmp_usb_offsets {\n+\tu16 serdes;\n+\tu16 pcs;\n+\tu16 pcs_misc;\n+\tu16 pcs_usb;\n+\tu16 tx;\n+\tu16 rx;\n+};\n+\n+/* struct qmp_phy_cfg - per-PHY initialization config */\n+struct qmp_phy_cfg {\n+\tconst struct qmp_usb_offsets *offsets;\n+\n+\t/* Init sequence for PHY blocks - serdes, tx, rx, pcs */\n+\tconst struct qmp_phy_init_tbl *serdes_tbl;\n+\tint serdes_tbl_num;\n+\tconst struct qmp_phy_init_tbl *tx_tbl;\n+\tint tx_tbl_num;\n+\tconst struct qmp_phy_init_tbl *rx_tbl;\n+\tint rx_tbl_num;\n+\tconst struct qmp_phy_init_tbl *pcs_tbl;\n+\tint pcs_tbl_num;\n+\tconst struct qmp_phy_init_tbl *pcs_usb_tbl;\n+\tint pcs_usb_tbl_num;\n+\n+\t/* regulators to be requested */\n+\tconst char * const *vreg_list;\n+\tint num_vregs;\n+\n+\t/* array of registers with different offsets */\n+\tconst unsigned int *regs;\n+\n+\t/* true, if PHY needs delay after POWER_DOWN */\n+\tbool has_pwrdn_delay;\n+\n+\t/* Offset from PCS to PCS_USB region */\n+\tunsigned int pcs_usb_offset;\n+};\n+\n+struct qmp_usb {\n+\tstruct udevice *dev;\n+\n+\tconst struct qmp_phy_cfg *cfg;\n+\n+\tvoid __iomem *serdes;\n+\tvoid __iomem *pcs;\n+\tvoid __iomem *pcs_misc;\n+\tvoid __iomem *pcs_usb;\n+\tvoid __iomem *tx;\n+\tvoid __iomem *rx;\n+\n+\tstruct clk *pipe_clk;\n+\tstruct clk_bulk clks;\n+\tint num_clks;\n+\tint num_resets;\n+\tstruct reset_ctl_bulk *resets;\n+\tstruct regulator_bulk_data *vregs;\n+\n+\tenum phy_mode mode;\n+\n+\tstruct phy *phy;\n+\n+\tstruct clk_fixed_rate pipe_clk_fixed;\n+};\n+\n+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)\n+{\n+\tu32 reg;\n+\n+\treg = readl(base + offset);\n+\treg |= val;\n+\twritel(reg, base + offset);\n+\n+\t/* ensure that above write is through */\n+\treadl(base + offset);\n+}\n+\n+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)\n+{\n+\tu32 reg;\n+\n+\treg = readl(base + offset);\n+\treg &= ~val;\n+\twritel(reg, base + offset);\n+\n+\t/* ensure that above write is through */\n+\treadl(base + offset);\n+}\n+\n+/* list of clocks required by phy */\n+static const char * const qmp_usb_phy_clk_l[] = {\n+\t\"aux\", \"cfg_ahb\", \"ref\", \"com_aux\",\n+};\n+\n+/* list of resets */\n+static const char * const usb3phy_legacy_reset_l[] = {\n+\t\"phy\", \"common\",\n+};\n+\n+static const char * const usb3phy_reset_l[] = {\n+\t\"phy_phy\", \"phy\",\n+};\n+\n+/* list of regulators */\n+static const char * const qmp_phy_vreg_l[] = {\n+\t\"vdda-phy\", \"vdda-pll\",\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x800,\n+\t.pcs_misc\t= 0x600,\n+\t.tx\t\t= 0x200,\n+\t.rx\t\t= 0x400,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x800,\n+\t.pcs_usb\t= 0x800,\n+\t.tx\t\t= 0x200,\n+\t.rx\t\t= 0x400,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x600,\n+\t.tx\t\t= 0x200,\n+\t.rx\t\t= 0x400,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x0800,\n+\t.pcs_usb\t= 0x0e00,\n+\t.tx\t\t= 0x0200,\n+\t.rx\t\t= 0x0400,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x0200,\n+\t.pcs_usb\t= 0x1200,\n+\t.tx\t\t= 0x0e00,\n+\t.rx\t\t= 0x1000,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x0200,\n+\t.pcs_usb\t= 0x1200,\n+\t.tx\t\t= 0x0e00,\n+\t.rx\t\t= 0x1000,\n+};\n+\n+static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {\n+\t.serdes\t\t= 0,\n+\t.pcs\t\t= 0x0200,\n+\t.pcs_usb\t= 0x1200,\n+\t.tx\t\t= 0x0e00,\n+\t.rx\t\t= 0x1000,\n+};\n+\n+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v3,\n+\n+\t.serdes_tbl\t\t= ipq9574_usb3_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),\n+\t.tx_tbl\t\t\t= msm8996_usb3_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_tx_tbl),\n+\t.rx_tbl\t\t\t= ipq8074_usb3_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(ipq8074_usb3_rx_tbl),\n+\t.pcs_tbl\t\t= ipq8074_usb3_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v3_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v3,\n+\n+\t.serdes_tbl\t\t= ipq8074_usb3_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(ipq8074_usb3_serdes_tbl),\n+\t.tx_tbl\t\t\t= msm8996_usb3_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_tx_tbl),\n+\t.rx_tbl\t\t\t= ipq8074_usb3_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(ipq8074_usb3_rx_tbl),\n+\t.pcs_tbl\t\t= ipq8074_usb3_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v3_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_ipq9574,\n+\n+\t.serdes_tbl\t\t= ipq9574_usb3_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),\n+\t.tx_tbl\t\t\t= ipq9574_usb3_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(ipq9574_usb3_tx_tbl),\n+\t.rx_tbl\t\t\t= ipq9574_usb3_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(ipq9574_usb3_rx_tbl),\n+\t.pcs_tbl\t\t= ipq9574_usb3_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(ipq9574_usb3_pcs_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v3_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v3_msm8996,\n+\n+\t.serdes_tbl\t\t= msm8996_usb3_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_serdes_tbl),\n+\t.tx_tbl\t\t\t= msm8996_usb3_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_tx_tbl),\n+\t.rx_tbl\t\t\t= msm8996_usb3_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_rx_tbl),\n+\t.pcs_tbl\t\t= msm8996_usb3_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(msm8996_usb3_pcs_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v2_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg qdu1000_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sm8350_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sm8350_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= qdu1000_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= qdu1000_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v4_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x1000,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sc8280xp_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sc8280xp_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sc8280xp_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sa8775p_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sa8775p_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v5_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg qcs8300_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sc8280xp_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= qcs8300_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(qcs8300_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= qcs8300_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(qcs8300_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sa8775p_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sa8775p_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v5_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sc8280xp_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sc8280xp_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sc8280xp_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sc8280xp_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sc8280xp_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v5_usb3phy_regs_layout,\n+};\n+\n+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v3,\n+\n+\t.serdes_tbl\t\t= qmp_v3_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= qmp_v3_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= qmp_v3_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= qmp_v3_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v3_usb3phy_regs_layout,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v4,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sm8150_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sm8150_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sm8150_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sm8150_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v4_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x600,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v4,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sm8250_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sm8250_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sm8250_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sm8250_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v4_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x600,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v4,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sdx55_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sdx55_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sm8250_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sm8250_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v4_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x600,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sdx65_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sdx65_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sm8350_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sm8350_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v5_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x1000,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v6,\n+\n+\t.serdes_tbl\t\t= sdx75_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sdx75_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sdx75_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sdx75_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sdx75_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v6_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x1000,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v5,\n+\n+\t.serdes_tbl\t\t= sm8150_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= sm8350_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= sm8350_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= sm8350_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= sm8350_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v5_usb3phy_regs_layout,\n+\t.pcs_usb_offset\t\t= 0x1000,\n+\n+\t.has_pwrdn_delay\t= true,\n+};\n+\n+static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {\n+\t.offsets\t\t= &qmp_usb_offsets_v7,\n+\n+\t.serdes_tbl\t\t= x1e80100_usb3_uniphy_serdes_tbl,\n+\t.serdes_tbl_num\t\t= ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),\n+\t.tx_tbl\t\t\t= x1e80100_usb3_uniphy_tx_tbl,\n+\t.tx_tbl_num\t\t= ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),\n+\t.rx_tbl\t\t\t= x1e80100_usb3_uniphy_rx_tbl,\n+\t.rx_tbl_num\t\t= ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),\n+\t.pcs_tbl\t\t= x1e80100_usb3_uniphy_pcs_tbl,\n+\t.pcs_tbl_num\t\t= ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),\n+\t.pcs_usb_tbl\t\t= x1e80100_usb3_uniphy_pcs_usb_tbl,\n+\t.pcs_usb_tbl_num\t= ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),\n+\t.vreg_list\t\t= qmp_phy_vreg_l,\n+\t.num_vregs\t\t= ARRAY_SIZE(qmp_phy_vreg_l),\n+\t.regs\t\t\t= qmp_v7_usb3phy_regs_layout,\n+};\n+\n+static int qmp_usb_serdes_init(struct qmp_usb *qmp)\n+{\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tvoid __iomem *serdes = qmp->serdes;\n+\tconst struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;\n+\tint serdes_tbl_num = cfg->serdes_tbl_num;\n+\n+\tqmp_configure(qmp->dev, serdes, serdes_tbl, serdes_tbl_num);\n+\n+\treturn 0;\n+}\n+\n+static int qmp_usb_init(struct phy *phy)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(phy->dev);\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tvoid __iomem *pcs = qmp->pcs;\n+\tint ret;\n+\n+\tret = reset_assert_bulk(qmp->resets);\n+\tif (ret) {\n+\t\tdev_err(qmp->dev, \"reset assert failed\\n\");\n+\t\tgoto err_disable_regulators;\n+\t}\n+\n+\tudelay(200);\n+\n+\tret = reset_deassert_bulk(qmp->resets);\n+\tif (ret) {\n+\t\tdev_err(qmp->dev, \"reset deassert failed\\n\");\n+\t\tgoto err_disable_regulators;\n+\t}\n+\n+\tudelay(200);\n+\n+\tret = clk_enable_bulk(&qmp->clks);\n+\tif (ret)\n+\t\tgoto err_assert_reset;\n+\n+\tqphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);\n+\n+\treturn 0;\n+\n+err_assert_reset:\n+\treset_deassert_bulk(qmp->resets);\n+err_disable_regulators:\n+\n+\treturn ret;\n+}\n+\n+static int qmp_usb_exit(struct phy *phy)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(phy->dev);\n+\n+\treset_assert_bulk(qmp->resets);\n+\n+\tclk_disable_bulk(&qmp->clks);\n+\n+\treturn 0;\n+}\n+\n+static int qmp_usb_power_on(struct phy *phy)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(phy->dev);\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tvoid __iomem *tx = qmp->tx;\n+\tvoid __iomem *rx = qmp->rx;\n+\tvoid __iomem *pcs = qmp->pcs;\n+\tvoid __iomem *pcs_usb = qmp->pcs_usb;\n+\tvoid __iomem *status;\n+\tunsigned int val;\n+\tint ret;\n+\n+\tqmp_usb_serdes_init(qmp);\n+\n+\tret = clk_prepare_enable(qmp->pipe_clk);\n+\tif (ret) {\n+\t\tdev_err(qmp->dev, \"pipe_clk enable failed err=%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Tx, Rx, and PCS configurations */\n+\tqmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);\n+\tqmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);\n+\n+\tqmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);\n+\n+\tif (pcs_usb)\n+\t\tqmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);\n+\n+\tif (cfg->has_pwrdn_delay)\n+\t\tudelay(20);\n+\n+\t/* Pull PHY out of reset state */\n+\tqphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);\n+\n+\t/* start SerDes and Phy-Coding-Sublayer */\n+\tqphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);\n+\n+\tstatus = pcs + cfg->regs[QPHY_PCS_STATUS];\n+\tret = readl_poll_timeout(status, val, !(val & PHYSTATUS),\n+\t\t\t\t PHY_INIT_COMPLETE_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(qmp->dev, \"phy initialization timed-out\\n\");\n+\t\tgoto err_disable_pipe_clk;\n+\t}\n+\n+\treturn 0;\n+\n+err_disable_pipe_clk:\n+\tclk_disable_unprepare(qmp->pipe_clk);\n+\n+\treturn ret;\n+}\n+\n+static int qmp_usb_power_off(struct phy *phy)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(phy->dev);\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\n+\tclk_disable_unprepare(qmp->pipe_clk);\n+\n+\t/* PHY reset */\n+\tqphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);\n+\n+\t/* stop SerDes and Phy-Coding-Sublayer */\n+\tqphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],\n+\t\t SERDES_START | PCS_START);\n+\n+\t/* Put PHY into POWER DOWN state: active low */\n+\tqphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],\n+\t\t SW_PWRDN);\n+\n+\treturn 0;\n+}\n+\n+static int qmp_usb_enable(struct phy *phy)\n+{\n+\tint ret;\n+\n+\tret = qmp_usb_init(phy);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = qmp_usb_power_on(phy);\n+\tif (ret)\n+\t\tqmp_usb_exit(phy);\n+\n+\treturn ret;\n+}\n+\n+static int qmp_usb_disable(struct phy *phy)\n+{\n+\tint ret;\n+\n+\tret = qmp_usb_power_off(phy);\n+\tif (ret)\n+\t\treturn ret;\n+\treturn qmp_usb_exit(phy);\n+}\n+\n+static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(phy->dev);\n+\n+\tqmp->mode = mode;\n+\n+\treturn 0;\n+}\n+\n+static const struct phy_ops qmp_usb_phy_ops = {\n+\t.init\t\t= qmp_usb_enable,\n+\t.exit\t\t= qmp_usb_disable,\n+\t.set_mode\t= qmp_usb_set_mode,\n+};\n+\n+static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)\n+{\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tvoid __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;\n+\tvoid __iomem *pcs_misc = qmp->pcs_misc;\n+\tu32 intr_mask;\n+\n+\tif (qmp->mode == PHY_MODE_USB_HOST_SS ||\n+\t qmp->mode == PHY_MODE_USB_DEVICE_SS)\n+\t\tintr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;\n+\telse\n+\t\tintr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;\n+\n+\t/* Clear any pending interrupts status */\n+\tqphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);\n+\t/* Writing 1 followed by 0 clears the interrupt */\n+\tqphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);\n+\n+\tqphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],\n+\t\t ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);\n+\n+\t/* Enable required PHY autonomous mode interrupts */\n+\tqphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);\n+\n+\t/* Enable i/o clamp_n for autonomous mode */\n+\tif (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])\n+\t\tqphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);\n+}\n+\n+static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)\n+{\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tvoid __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;\n+\tvoid __iomem *pcs_misc = qmp->pcs_misc;\n+\n+\t/* Disable i/o clamp_n on resume for normal mode */\n+\tif (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])\n+\t\tqphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);\n+\n+\tqphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],\n+\t\t ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);\n+\n+\tqphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);\n+\t/* Writing 1 followed by 0 clears the interrupt */\n+\tqphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);\n+}\n+\n+static int qmp_usb_reset_init(struct qmp_usb *qmp,\n+\t\t\t const char *const *reset_list,\n+\t\t\t int num_resets)\n+{\n+\tstruct udevice *dev = qmp->dev;\n+\tint ret;\n+\n+\tqmp->num_resets = num_resets;\n+\n+\tqmp->resets = devm_reset_bulk_get_optional(dev);\n+\tif (IS_ERR_OR_NULL(qmp->resets)) {\n+\t\tret = PTR_ERR(qmp->resets);\n+\t\tdev_err(dev, \"failed to get resets %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int qmp_usb_clk_init(struct qmp_usb *qmp)\n+{\n+\tstruct udevice *dev = qmp->dev;\n+\tint ret;\n+\n+\tret = clk_get_bulk(dev, &qmp->clks);\n+\n+\tif (!ret)\n+\t\tqmp->num_clks = qmp->clks.count;\n+\n+\treturn ret;\n+}\n+\n+static int qmp_usb_parse_dt(struct qmp_usb *qmp)\n+{\n+\tconst struct qmp_phy_cfg *cfg = qmp->cfg;\n+\tconst struct qmp_usb_offsets *offs = cfg->offsets;\n+\tstruct udevice *dev = qmp->dev;\n+\tvoid __iomem *base;\n+\tint ret;\n+\n+\tif (!offs)\n+\t\treturn -EINVAL;\n+\n+\tbase = (void __iomem *)dev_read_addr(dev);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tqmp->serdes = base + offs->serdes;\n+\tqmp->pcs = base + offs->pcs;\n+\tif (offs->pcs_usb)\n+\t\tqmp->pcs_usb = base + offs->pcs_usb;\n+\tif (offs->pcs_misc)\n+\t\tqmp->pcs_misc = base + offs->pcs_misc;\n+\tqmp->tx = base + offs->tx;\n+\tqmp->rx = base + offs->rx;\n+\n+\tret = qmp_usb_clk_init(qmp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tqmp->pipe_clk = devm_clk_get(dev, \"pipe\");\n+\tif (IS_ERR(qmp->pipe_clk)) {\n+\t\tdev_err(dev, \"failed to get pipe clock (%ld)\\n\",\n+\t\t\tPTR_ERR(qmp->pipe_clk));\n+\t\treturn ret;\n+\t}\n+\n+\tret = qmp_usb_reset_init(qmp, usb3phy_reset_l,\n+\t\t\t\t ARRAY_SIZE(usb3phy_reset_l));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int qmp_usb_probe(struct udevice *dev)\n+{\n+\tstruct qmp_usb *qmp = dev_get_priv(dev);\n+\tint ret;\n+\n+\tqmp->dev = dev;\n+\tdev_set_drvdata(dev, qmp);\n+\n+\tqmp->cfg = (struct qmp_phy_cfg *)dev_get_driver_data(dev);\n+\tif (!qmp->cfg)\n+\t\treturn -EINVAL;\n+\n+\tret = qmp_usb_parse_dt(qmp);\n+\n+\tif (ret)\n+\t\tgoto err_node_put;\n+\n+err_node_put:\n+\treturn ret;\n+}\n+\n+static const struct udevice_id qmp_usb_phy_ids[] = {\n+\t{\n+\t\t.compatible = \"qcom,ipq5424-qmp-usb3-phy\",\n+\t\t.data = (ulong)&ipq9574_usb3phy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,ipq6018-qmp-usb3-phy\",\n+\t\t.data = (ulong)&ipq6018_usb3phy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,ipq8074-qmp-usb3-phy\",\n+\t\t.data = (ulong)&ipq8074_usb3phy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,ipq9574-qmp-usb3-phy\",\n+\t\t.data = (ulong)&ipq9574_usb3phy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,msm8996-qmp-usb3-phy\",\n+\t\t.data = (ulong)&msm8996_usb3phy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,qcs8300-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&qcs8300_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,qdu1000-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&qdu1000_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sa8775p-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sa8775p_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sc8180x-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sm8150_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sc8280xp-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sc8280xp_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sdm845-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&qmp_v3_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sdx55-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sdx55_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sdx65-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sdx65_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sdx75-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sdx75_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sm8150-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sm8150_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sm8250-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sm8250_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,sm8350-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&sm8350_usb3_uniphy_cfg,\n+\t}, {\n+\t\t.compatible = \"qcom,x1e80100-qmp-usb3-uni-phy\",\n+\t\t.data = (ulong)&x1e80100_usb3_uniphy_cfg,\n+\t},\n+\t{ },\n+};\n+\n+U_BOOT_DRIVER(qmp_usb_phy) = {\n+\t.name\t\t= \"qcom-qmp-usb-phy\",\n+\t.id\t\t= UCLASS_PHY,\n+\t.of_match\t= qmp_usb_phy_ids,\n+\t.ops\t\t= &qmp_usb_phy_ops,\n+\t.probe\t\t= qmp_usb_probe,\n+\t.priv_auto\t= sizeof(struct qmp_usb),\n+};\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp.h b/drivers/phy/qcom/phy-qcom-qmp.h\nindex 99f4d447caf..f9c9a4714fc 100644\n--- a/drivers/phy/qcom/phy-qcom-qmp.h\n+++ b/drivers/phy/qcom/phy-qcom-qmp.h\n@@ -112,4 +112,19 @@\n #define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS\t\t0x0e0\n #define QSERDES_V6_DP_PHY_STATUS\t\t\t0x0e4\n \n+/* QPHY_PCS_STATUS bit */\n+#define PHYSTATUS\t\t\t\tBIT(6)\n+#define PHYSTATUS_4_20\t\t\t\tBIT(7)\n+\n+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */\n+#define ARCVR_DTCT_EN\t\t\t\tBIT(0)\n+#define ALFPS_DTCT_EN\t\t\t\tBIT(1)\n+#define ARCVR_DTCT_EVENT_SEL\t\t\tBIT(4)\n+\n+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */\n+#define IRQ_CLEAR\t\t\t\tBIT(0)\n+\n+/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */\n+#define CLAMP_EN\t\t\t\tBIT(0) /* enables i/o clamp_n */\n+\n #endif\n", "prefixes": [ "RESEND", "v2", "3/6" ] }