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GET /api/1.0/patches/2175384/?format=api
{ "id": 2175384, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175384/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217212018.93320-5-gustavo.romero@linaro.org>", "date": "2025-12-17T21:20:16", "name": "[v2,4/6] system/physmem: Rename cpu_address_space_init", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b0f2b3c19d132de58e9a4e22cfb3c2911e6bd295", "submitter": { "id": 82513, "url": "http://patchwork.ozlabs.org/api/1.0/people/82513/?format=api", "name": "Gustavo Romero", "email": "gustavo.romero@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217212018.93320-5-gustavo.romero@linaro.org/mbox/", "series": [ { "id": 485770, "url": "http://patchwork.ozlabs.org/api/1.0/series/485770/?format=api", "date": "2025-12-17T21:20:12", "name": "system/physmem: Enhance the Address Space API", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485770/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175384/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=yiTbWMmN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWmwV42b7z1xpw\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 08:22:34 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vVyxO-0000A6-DS; Wed, 17 Dec 2025 16:21:14 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gustavo.romero@linaro.org>)\n id 1vVyxJ-0008Tw-S4\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 16:21:11 -0500", "from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <gustavo.romero@linaro.org>)\n id 1vVyxG-0004ch-OC\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 16:21:08 -0500", "by mail-pf1-x431.google.com with SMTP id\n d2e1a72fcca58-7aa2170adf9so5105738b3a.0\n for <qemu-devel@nongnu.org>; Wed, 17 Dec 2025 13:21:06 -0800 (PST)", "from gromero0.. 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helo=mail-pf1-x431.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Rename cpu_address_space_init to cpu_address_space_add in preparation\nfor the forthcoming addition of a new cpu_address_space_init.\n\nSigned-off-by: Gustavo Romero <gustavo.romero@linaro.org>\n---\n include/exec/cpu-common.h | 6 +++---\n stubs/cpu-destroy-address-spaces.c | 2 +-\n system/cpus.c | 2 +-\n system/physmem.c | 4 ++--\n target/arm/cpu.c | 16 ++++++++--------\n target/arm/cpu.h | 2 +-\n target/i386/kvm/kvm-cpu.c | 2 +-\n target/i386/kvm/kvm.c | 4 ++--\n target/i386/tcg/system/tcg-cpu.c | 4 ++--\n 9 files changed, 21 insertions(+), 21 deletions(-)", "diff": "diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h\nindex e0be4ee2b8..126f645354 100644\n--- a/include/exec/cpu-common.h\n+++ b/include/exec/cpu-common.h\n@@ -102,7 +102,7 @@ size_t qemu_ram_pagesize(RAMBlock *block);\n size_t qemu_ram_pagesize_largest(void);\n \n /**\n- * cpu_address_space_init:\n+ * cpu_address_space_add:\n * @cpu: CPU to add this address space to\n * @asidx: integer index of this address space\n * @prefix: prefix to be used as name of address space\n@@ -120,8 +120,8 @@ size_t qemu_ram_pagesize_largest(void);\n *\n * Note that with KVM only one address space is supported.\n */\n-void cpu_address_space_init(CPUState *cpu, int asidx,\n- const char *prefix, MemoryRegion *mr);\n+void cpu_address_space_add(CPUState *cpu, int asidx,\n+ const char *prefix, MemoryRegion *mr);\n /**\n * cpu_destroy_address_spaces:\n * @cpu: CPU for which address spaces need to be destroyed\ndiff --git a/stubs/cpu-destroy-address-spaces.c b/stubs/cpu-destroy-address-spaces.c\nindex dc6813f5bd..a86e8d4db1 100644\n--- a/stubs/cpu-destroy-address-spaces.c\n+++ b/stubs/cpu-destroy-address-spaces.c\n@@ -5,7 +5,7 @@\n \n /*\n * user-mode CPUs never create address spaces with\n- * cpu_address_space_init(), so the cleanup function doesn't\n+ * cpu_address_space_add(), so the cleanup function doesn't\n * need to do anything. We need this stub because cpu-common.c\n * is built-once so it can't #ifndef CONFIG_USER around the\n * call; the real function is in physmem.c which is system-only.\ndiff --git a/system/cpus.c b/system/cpus.c\nindex ef2d2f241f..fa9deafa29 100644\n--- a/system/cpus.c\n+++ b/system/cpus.c\n@@ -719,7 +719,7 @@ void qemu_init_vcpu(CPUState *cpu)\n * give it the default one.\n */\n cpu->num_ases = 1;\n- cpu_address_space_init(cpu, 0, \"cpu-memory\", cpu->memory);\n+ cpu_address_space_add(cpu, 0, \"cpu-memory\", cpu->memory);\n }\n \n /* accelerators all implement the AccelOpsClass */\ndiff --git a/system/physmem.c b/system/physmem.c\nindex c9869e4049..4a0c1b74f1 100644\n--- a/system/physmem.c\n+++ b/system/physmem.c\n@@ -775,8 +775,8 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,\n \n #endif /* CONFIG_TCG */\n \n-void cpu_address_space_init(CPUState *cpu, int asidx,\n- const char *prefix, MemoryRegion *mr)\n+void cpu_address_space_add(CPUState *cpu, int asidx,\n+ const char *prefix, MemoryRegion *mr)\n {\n CPUAddressSpace *newas;\n AddressSpace *as = g_new0(AddressSpace, 1);\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 1640b20b4d..1902c510f9 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1681,7 +1681,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n *\n * Catch all the cases which might cause us to create more than one\n * address space for the CPU (otherwise we will assert() later in\n- * cpu_address_space_init()).\n+ * cpu_address_space_add()).\n */\n if (arm_feature(env, ARM_FEATURE_M)) {\n error_setg(errp,\n@@ -2158,22 +2158,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n cs->num_ases = 1 + has_secure;\n }\n \n- cpu_address_space_init(cs, ARMASIdx_NS, \"cpu-memory\", cs->memory);\n+ cpu_address_space_add(cs, ARMASIdx_NS, \"cpu-memory\", cs->memory);\n \n if (has_secure) {\n if (!cpu->secure_memory) {\n cpu->secure_memory = cs->memory;\n }\n- cpu_address_space_init(cs, ARMASIdx_S, \"cpu-secure-memory\",\n- cpu->secure_memory);\n+ cpu_address_space_add(cs, ARMASIdx_S, \"cpu-secure-memory\",\n+ cpu->secure_memory);\n }\n \n if (cpu->tag_memory != NULL) {\n- cpu_address_space_init(cs, ARMASIdx_TagNS, \"cpu-tag-memory\",\n- cpu->tag_memory);\n+ cpu_address_space_add(cs, ARMASIdx_TagNS, \"cpu-tag-memory\",\n+ cpu->tag_memory);\n if (has_secure) {\n- cpu_address_space_init(cs, ARMASIdx_TagS, \"cpu-tag-memory\",\n- cpu->secure_tag_memory);\n+ cpu_address_space_add(cs, ARMASIdx_TagS, \"cpu-tag-memory\",\n+ cpu->secure_tag_memory);\n }\n }\n \ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 00f5af0fcd..f68552945e 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -2330,7 +2330,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);\n \n #define TYPE_ARM_HOST_CPU \"host-\" TYPE_ARM_CPU\n \n-/* Indexes used when registering address spaces with cpu_address_space_init */\n+/* Indexes used when registering address spaces with cpu_address_space_add */\n typedef enum ARMASIdx {\n ARMASIdx_NS = 0,\n ARMASIdx_S = 1,\ndiff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c\nindex 9c25b55839..a6d94d0620 100644\n--- a/target/i386/kvm/kvm-cpu.c\n+++ b/target/i386/kvm/kvm-cpu.c\n@@ -99,7 +99,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)\n * initialized at register_smram_listener() after machine init done.\n */\n cs->num_ases = x86_machine_is_smm_enabled(X86_MACHINE(current_machine)) ? 2 : 1;\n- cpu_address_space_init(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n+ cpu_address_space_add(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n \n return true;\n }\ndiff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c\nindex 60c7981138..dcc7e5eeae 100644\n--- a/target/i386/kvm/kvm.c\n+++ b/target/i386/kvm/kvm.c\n@@ -2744,14 +2744,14 @@ static void register_smram_listener(Notifier *n, void *unused)\n &smram_address_space, X86ASIdx_SMM, \"kvm-smram\");\n \n CPU_FOREACH(cpu) {\n- cpu_address_space_init(cpu, X86ASIdx_SMM, \"cpu-smm\", &smram_as_root);\n+ cpu_address_space_add(cpu, X86ASIdx_SMM, \"cpu-smm\", &smram_as_root);\n }\n }\n \n /* It should only be called in cpu's hotplug callback */\n void kvm_smm_cpu_address_space_init(X86CPU *cpu)\n {\n- cpu_address_space_init(CPU(cpu), X86ASIdx_SMM, \"cpu-smm\", &smram_as_root);\n+ cpu_address_space_add(CPU(cpu), X86ASIdx_SMM, \"cpu-smm\", &smram_as_root);\n }\n \n static void *kvm_msr_energy_thread(void *data)\ndiff --git a/target/i386/tcg/system/tcg-cpu.c b/target/i386/tcg/system/tcg-cpu.c\nindex 7255862c24..231a4bdf55 100644\n--- a/target/i386/tcg/system/tcg-cpu.c\n+++ b/target/i386/tcg/system/tcg-cpu.c\n@@ -74,8 +74,8 @@ bool tcg_cpu_realizefn(CPUState *cs, Error **errp)\n memory_region_set_enabled(cpu->cpu_as_mem, true);\n \n cs->num_ases = 2;\n- cpu_address_space_init(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n- cpu_address_space_init(cs, X86ASIdx_SMM, \"cpu-smm\", cpu->cpu_as_root);\n+ cpu_address_space_add(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n+ cpu_address_space_add(cs, X86ASIdx_SMM, \"cpu-smm\", cpu->cpu_as_root);\n \n /* ... SMRAM with higher priority, linked from /machine/smram. */\n cpu->machine_done.notify = tcg_cpu_machine_done;\n", "prefixes": [ "v2", "4/6" ] }