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{ "id": 2175319, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175319/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217190018.487429-4-rdapp@ventanamicro.com>", "date": "2025-12-17T19:00:17", "name": "[v3,3/4] RISC-V: Add VLS modes to autovec iterators.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "515e904fffb23581bb85fca613223b044db45bb2", "submitter": { "id": 86205, "url": "http://patchwork.ozlabs.org/api/1.0/people/86205/?format=api", "name": "Robin Dapp", "email": "rdapp.gcc@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251217190018.487429-4-rdapp@ventanamicro.com/mbox/", "series": [ { "id": 485748, "url": "http://patchwork.ozlabs.org/api/1.0/series/485748/?format=api", "date": "2025-12-17T19:00:18", "name": "VLS-related stuff.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485748/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175319/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=k6+L3R9q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=k6+L3R9q", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "sourceware.org; spf=pass smtp.mailfrom=gmail.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=209.85.208.41" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWjs45kdSz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 06:04:24 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 9AD414BA2E21\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 19:04:22 +0000 (GMT)", "from mail-ed1-f41.google.com (mail-ed1-f41.google.com\n [209.85.208.41])\n by sourceware.org (Postfix) with ESMTPS id CC5C44BA2E29\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 19:00:25 +0000 (GMT)", "by mail-ed1-f41.google.com with SMTP id\n 4fb4d7f45d1cf-640ca678745so11490851a12.2\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 11:00:25 -0800 (PST)", "from x1c10.dc1.ventanamicro.com\n (ip-149-172-150-237.um42.pools.vodafone-ip.de. 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autovec iterators.", "Date": "Wed, 17 Dec 2025 20:00:17 +0100", "Message-ID": "<20251217190018.487429-4-rdapp@ventanamicro.com>", "X-Mailer": "git-send-email 2.51.1", "In-Reply-To": "<20251217190018.487429-1-rdapp@ventanamicro.com>", "References": "<20251217190018.487429-1-rdapp@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "In order to allow more VLS vectorization, add more VLS modes to the\nautovec expanders, as well as some missing VLS modes that I encountered while\ntesting.\n\ngcc/ChangeLog:\n\n\t* config/riscv/autovec.md: Ditto.\n\t* config/riscv/autovec-opt.md: Add VLS modes.\n\t* config/riscv/vector-crypto.md: Ditto.\n\t* config/riscv/vector-iterators.md: Ditto.\n\t* config/riscv/vector.md (@pred_ffs<VB:mode><P:mode>): Ditto.\n\t(@pred_ffs<VB_VLS:mode><P:mode>): Ditto.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c:\n\tAdjust test expectation.\n\t* gcc.target/riscv/rvv/autovec/param-autovec-mode.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto.\n---\n gcc/config/riscv/autovec-opt.md | 22 +--\n gcc/config/riscv/autovec.md | 163 +++++++++--------\n gcc/config/riscv/vector-crypto.md | 172 +++++++++---------\n gcc/config/riscv/vector-iterators.md | 134 +++++++++++++-\n gcc/config/riscv/vector.md | 114 ++++++------\n .../autovec/gather-scatter/strided_store-2.c | 3 +-\n .../riscv/rvv/autovec/param-autovec-mode.c | 2 +-\n .../riscv/rvv/autovec/partial/select_vl-2.c | 4 +-\n .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 5 +-\n .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 5 +-\n 10 files changed, 373 insertions(+), 251 deletions(-)", "diff": "diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md\nindex 40627fac91c..3ebce87562b 100644\n--- a/gcc/config/riscv/autovec-opt.md\n+++ b/gcc/config/riscv/autovec-opt.md\n@@ -37,17 +37,17 @@\n ;; -----------------------------------------------------------------------------\n \n (define_split\n- [(set (match_operand:VB 0 \"register_operand\")\n-\t(if_then_else:VB\n-\t (unspec:VB\n-\t [(match_operand:VB 1 \"vector_all_trues_mask_operand\")\n+ [(set (match_operand:VB_VLS 0 \"register_operand\")\n+\t(if_then_else:VB_VLS\n+\t (unspec:VB_VLS\n+\t [(match_operand:VB_VLS 1 \"vector_all_trues_mask_operand\")\n \t (match_operand 4 \"vector_length_operand\")\n \t (match_operand 5 \"const_int_operand\")\n \t (match_operand 6 \"const_int_operand\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VB 3 \"vector_move_operand\")\n-\t (match_operand:VB 2 \"vector_undef_operand\")))]\n+\t (match_operand:VB_VLS 3 \"vector_move_operand\")\n+\t (match_operand:VB_VLS 2 \"vector_undef_operand\")))]\n \"TARGET_VECTOR\"\n [(const_int 0)]\n {\n@@ -1447,11 +1447,11 @@ (define_insn_and_split \"*cond_len_widen_reduc_plus_scal_<mode>\"\n \n ;; Combine neg + vfsgnj to vfsgnjn\n (define_insn_and_split \"*copysign<mode>_neg\"\n- [(set (match_operand:VF 0 \"register_operand\")\n- (neg:VF\n- (unspec:VF [\n- (match_operand:VF 1 \"register_operand\")\n- (match_operand:VF 2 \"register_operand\")\n+ [(set (match_operand:V_VLSF 0 \"register_operand\")\n+ (neg:V_VLSF\n+ (unspec:V_VLSF [\n+ (match_operand:V_VLSF 1 \"register_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n ] UNSPEC_VCOPYSIGN)))]\n \"TARGET_VECTOR && can_create_pseudo_p ()\"\n \"#\"\ndiff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md\nindex 8ff3f55ffc4..f887c62c6c3 100644\n--- a/gcc/config/riscv/autovec.md\n+++ b/gcc/config/riscv/autovec.md\n@@ -23,10 +23,10 @@\n ;; =========================================================================\n \n (define_expand \"mask_len_load<mode><vm>\"\n- [(match_operand:V 0 \"register_operand\")\n- (match_operand:V 1 \"memory_operand\")\n+ [(match_operand:V_VLS 0 \"register_operand\")\n+ (match_operand:V_VLS 1 \"memory_operand\")\n (match_operand:<VM> 2 \"vector_mask_operand\")\n- (match_operand:V 3 \"maskload_else_operand\")\n+ (match_operand:V_VLS 3 \"maskload_else_operand\")\n (match_operand 4 \"autovec_length_operand\")\n (match_operand 5 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -36,8 +36,8 @@ (define_expand \"mask_len_load<mode><vm>\"\n })\n \n (define_expand \"mask_len_store<mode><vm>\"\n- [(match_operand:V 0 \"memory_operand\")\n- (match_operand:V 1 \"register_operand\")\n+ [(match_operand:V_VLS 0 \"memory_operand\")\n+ (match_operand:V_VLS 1 \"register_operand\")\n (match_operand:<VM> 2 \"vector_mask_operand\")\n (match_operand 3 \"autovec_length_operand\")\n (match_operand 4 \"const_0_operand\")]\n@@ -440,8 +440,8 @@ (define_expand \"vec_init<mode>qi\"\n \n ;; Slide an RVV vector left and insert a scalar into element 0.\n (define_expand \"vec_shl_insert_<mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n- (match_operand:VI 1 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n+ (match_operand:V_VLSI 1 \"register_operand\")\n (match_operand:<VEL> 2 \"reg_or_0_operand\")]\n \"TARGET_VECTOR\"\n {\n@@ -452,8 +452,8 @@ (define_expand \"vec_shl_insert_<mode>\"\n })\n \n (define_expand \"vec_shl_insert_<mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n- (match_operand:VF 1 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n+ (match_operand:V_VLSF 1 \"register_operand\")\n (match_operand:<VEL> 2 \"register_operand\")]\n \"TARGET_VECTOR\"\n {\n@@ -622,10 +622,10 @@ (define_insn_and_split \"vcond_mask_<mode><vm>\"\n )\n \n (define_expand \"vcond_mask_len_<mode>\"\n- [(match_operand:V 0 \"register_operand\")\n+ [(match_operand:V_VLS 0 \"register_operand\")\n (match_operand:<VM> 1 \"nonmemory_operand\")\n- (match_operand:V 2 \"nonmemory_operand\")\n- (match_operand:V 3 \"autovec_else_operand\")\n+ (match_operand:V_VLS 2 \"nonmemory_operand\")\n+ (match_operand:V_VLS 3 \"autovec_else_operand\")\n (match_operand 4 \"autovec_length_operand\")\n (match_operand 5 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1730,11 +1730,11 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_int_unop:VI\n- (match_operand:VI 2 \"register_operand\"))\n- (match_operand:VI 3 \"autovec_else_operand\")\n+ (any_int_unop:V_VLSI\n+ (match_operand:V_VLSI 2 \"register_operand\"))\n+ (match_operand:V_VLSI 3 \"autovec_else_operand\")\n (match_operand 4 \"autovec_length_operand\")\n (match_operand 5 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1765,11 +1765,11 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_float_unop_nofrm:VF\n- (match_operand:VF 2 \"register_operand\"))\n- (match_operand:VF 3 \"autovec_else_operand\")\n+ (any_float_unop_nofrm:V_VLSF\n+ (match_operand:V_VLSF 2 \"register_operand\"))\n+ (match_operand:V_VLSF 3 \"autovec_else_operand\")\n (match_operand 4 \"autovec_length_operand\")\n (match_operand 5 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1801,12 +1801,12 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_shift:VI\n- (match_operand:VI 2 \"register_operand\")\n- (match_operand:VI 3 \"vector_shift_operand\"))\n- (match_operand:VI 4 \"autovec_else_operand\")\n+ (any_shift:V_VLSI\n+ (match_operand:V_VLSI 2 \"register_operand\")\n+ (match_operand:V_VLSI 3 \"vector_shift_operand\"))\n+ (match_operand:V_VLSI 4 \"autovec_else_operand\")\n (match_operand 5 \"autovec_length_operand\")\n (match_operand 6 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1839,12 +1839,12 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_int_binop_no_shift:VI\n- (match_operand:VI 2 \"<binop_rhs1_predicate>\")\n- (match_operand:VI 3 \"<binop_rhs2_predicate>\"))\n- (match_operand:VI 4 \"autovec_else_operand\")\n+ (any_int_binop_no_shift:V_VLSI\n+ (match_operand:V_VLSI 2 \"<binop_rhs1_predicate>\")\n+ (match_operand:V_VLSI 3 \"<binop_rhs2_predicate>\"))\n+ (match_operand:V_VLSI 4 \"autovec_else_operand\")\n (match_operand 5 \"autovec_length_operand\")\n (match_operand 6 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1877,12 +1877,12 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_float_binop:VF\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\"))\n- (match_operand:VF 4 \"autovec_else_operand\")\n+ (any_float_binop:V_VLSF\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\"))\n+ (match_operand:V_VLSF 4 \"autovec_else_operand\")\n (match_operand 5 \"autovec_length_operand\")\n (match_operand 6 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1913,12 +1913,12 @@ (define_expand \"cond_<optab><mode>\"\n })\n \n (define_expand \"cond_len_<optab><mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (any_float_binop_nofrm:VF\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\"))\n- (match_operand:VF 4 \"autovec_else_operand\")\n+ (any_float_binop_nofrm:V_VLSF\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\"))\n+ (match_operand:V_VLSF 4 \"autovec_else_operand\")\n (match_operand 5 \"autovec_length_operand\")\n (match_operand 6 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -1943,12 +1943,12 @@ (define_expand \"cond_<ieee_fmaxmin_op><mode>\"\n })\n \n (define_expand \"cond_len_<ieee_fmaxmin_op><mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (unspec:VF\n- [(match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\")] UNSPEC_VFMAXMIN)\n- (match_operand:VF 4 \"autovec_else_operand\")\n+ (unspec:V_VLSF\n+ [(match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\")] UNSPEC_VFMAXMIN)\n+ (match_operand:V_VLSF 4 \"autovec_else_operand\")\n (match_operand 5 \"autovec_length_operand\")\n (match_operand 6 \"const_0_operand\")]\n \"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode)\"\n@@ -2002,12 +2002,12 @@ (define_expand \"cond_fma<mode>\"\n })\n \n (define_expand \"cond_len_fma<mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VI 2 \"register_operand\")\n- (match_operand:VI 3 \"register_operand\")\n- (match_operand:VI 4 \"register_operand\")\n- (match_operand:VI 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSI 2 \"register_operand\")\n+ (match_operand:V_VLSI 3 \"register_operand\")\n+ (match_operand:V_VLSI 4 \"register_operand\")\n+ (match_operand:V_VLSI 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2032,12 +2032,12 @@ (define_expand \"cond_fnma<mode>\"\n })\n \n (define_expand \"cond_len_fnma<mode>\"\n- [(match_operand:VI 0 \"register_operand\")\n+ [(match_operand:V_VLSI 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VI 2 \"register_operand\")\n- (match_operand:VI 3 \"register_operand\")\n- (match_operand:VI 4 \"register_operand\")\n- (match_operand:VI 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSI 2 \"register_operand\")\n+ (match_operand:V_VLSI 3 \"register_operand\")\n+ (match_operand:V_VLSI 4 \"register_operand\")\n+ (match_operand:V_VLSI 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2069,12 +2069,12 @@ (define_expand \"cond_fma<mode>\"\n })\n \n (define_expand \"cond_len_fma<mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\")\n- (match_operand:VF 4 \"register_operand\")\n- (match_operand:VF 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\")\n+ (match_operand:V_VLSF 4 \"register_operand\")\n+ (match_operand:V_VLSF 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2099,12 +2099,12 @@ (define_expand \"cond_fnma<mode>\"\n })\n \n (define_expand \"cond_len_fnma<mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\")\n- (match_operand:VF 4 \"register_operand\")\n- (match_operand:VF 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\")\n+ (match_operand:V_VLSF 4 \"register_operand\")\n+ (match_operand:V_VLSF 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2129,12 +2129,12 @@ (define_expand \"cond_fms<mode>\"\n })\n \n (define_expand \"cond_len_fms<mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\")\n- (match_operand:VF 4 \"register_operand\")\n- (match_operand:VF 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\")\n+ (match_operand:V_VLSF 4 \"register_operand\")\n+ (match_operand:V_VLSF 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2159,12 +2159,12 @@ (define_expand \"cond_fnms<mode>\"\n })\n \n (define_expand \"cond_len_fnms<mode>\"\n- [(match_operand:VF 0 \"register_operand\")\n+ [(match_operand:V_VLSF 0 \"register_operand\")\n (match_operand:<VM> 1 \"vector_mask_operand\")\n- (match_operand:VF 2 \"register_operand\")\n- (match_operand:VF 3 \"register_operand\")\n- (match_operand:VF 4 \"register_operand\")\n- (match_operand:VF 5 \"autovec_else_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n+ (match_operand:V_VLSF 3 \"register_operand\")\n+ (match_operand:V_VLSF 4 \"register_operand\")\n+ (match_operand:V_VLSF 5 \"autovec_else_operand\")\n (match_operand 6 \"autovec_length_operand\")\n (match_operand 7 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n@@ -2450,7 +2450,7 @@ (define_insn_and_split \"fold_left_plus_<mode>\"\n (define_insn_and_split \"mask_len_fold_left_plus_<mode>\"\n [(set (match_operand:<VEL> 0 \"register_operand\")\n (unspec:<VEL> [\n- (match_operand:VF 2 \"register_operand\")\n+ (match_operand:V_VLSF 2 \"register_operand\")\n (match_operand:<VEL> 1 \"register_operand\")\n (match_operand:<VM> 3 \"vector_mask_operand\")\n (match_operand 4 \"autovec_length_operand\")\n@@ -2486,6 +2486,9 @@ (define_insn_and_split \"mask_len_fold_left_plus_<mode>\"\n ;; - vfmv.f.s\n ;; -------------------------------------------------------------------------\n \n+;; If this is available for VLS modes we sometimes don't fall back to\n+;; non-partial accesses, thus missing a vectorization opportunity.\n+;; See PR122938.\n (define_expand \"len_fold_extract_last_<mode>\"\n [(match_operand:<VEL> 0 \"register_operand\")\n (match_operand:<VEL> 1 \"register_operand\")\n@@ -3066,10 +3069,10 @@ (define_expand \"<cbranch_optab><mode>\"\n ;; - vrol.vv vror.vv\n ;; -------------------------------------------------------------------------\n (define_expand \"v<bitmanip_optab><mode>3\"\n- [(set (match_operand:VI 0 \"register_operand\")\n-\t(bitmanip_rotate:VI\n-\t (match_operand:VI 1 \"register_operand\")\n-\t (match_operand:VI 2 \"register_operand\")))]\n+ [(set (match_operand:V_VLSI 0 \"register_operand\")\n+\t(bitmanip_rotate:V_VLSI\n+\t (match_operand:V_VLSI 1 \"register_operand\")\n+\t (match_operand:V_VLSI 2 \"register_operand\")))]\n \"TARGET_ZVBB || TARGET_ZVKB\"\n {\n riscv_vector::emit_vlmax_insn (code_for_pred_v (<CODE>, <MODE>mode),\ndiff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md\nindex ca3ad4412fe..b3e6804f959 100644\n--- a/gcc/config/riscv/vector-crypto.md\n+++ b/gcc/config/riscv/vector-crypto.md\n@@ -223,8 +223,8 @@ (define_insn \"*pred_vandn<mode>_extended_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_v<bitmanip_optab><mode>\"\n- [(set (match_operand:VI 0 \"register_operand\" \"=vd,vd, vr, vr\")\n- (if_then_else:VI\n+ [(set (match_operand:V_VLSI 0 \"register_operand\" \"=vd,vd, vr, vr\")\n+ (if_then_else:V_VLSI\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm,vm,Wc1,Wc1\")\n (match_operand 5 \"vector_length_operand\" \" rK,rK, rK, rK\")\n@@ -233,18 +233,18 @@ (define_insn \"@pred_v<bitmanip_optab><mode>\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (bitmanip_rotate:VI\n- (match_operand:VI 3 \"register_operand\" \" vr,vr, vr, vr\")\n- (match_operand:VI 4 \"register_operand\" \" vr,vr, vr, vr\"))\n- (match_operand:VI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+ (bitmanip_rotate:V_VLSI\n+ (match_operand:V_VLSI 3 \"register_operand\" \" vr,vr, vr, vr\")\n+ (match_operand:V_VLSI 4 \"register_operand\" \" vr,vr, vr, vr\"))\n+ (match_operand:V_VLSI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_ZVBB || TARGET_ZVKB\"\n \"v<bitmanip_insn>.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"v<bitmanip_insn>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_v<bitmanip_optab><mode>_scalar\"\n- [(set (match_operand:VI 0 \"register_operand\" \"=vd,vd, vr, vr\")\n- (if_then_else:VI\n+ [(set (match_operand:V_VLSI 0 \"register_operand\" \"=vd,vd, vr, vr\")\n+ (if_then_else:V_VLSI\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm,vm,Wc1,Wc1\")\n (match_operand 5 \"vector_length_operand\" \" rK,rK, rK, rK\")\n@@ -253,18 +253,18 @@ (define_insn \"@pred_v<bitmanip_optab><mode>_scalar\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (bitmanip_rotate:VI\n- (match_operand:VI 3 \"register_operand\" \" vr,vr, vr, vr\")\n+ (bitmanip_rotate:V_VLSI\n+ (match_operand:V_VLSI 3 \"register_operand\" \" vr,vr, vr, vr\")\n (match_operand 4 \"pmode_register_operand\" \" r, r, r, r\"))\n- (match_operand:VI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+ (match_operand:V_VLSI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_ZVBB || TARGET_ZVKB\"\n \"v<bitmanip_insn>.vx\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"v<bitmanip_insn>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"*pred_vror<mode>_scalar\"\n- [(set (match_operand:VI 0 \"register_operand\" \"=vd,vd, vr,vr\")\n- (if_then_else:VI\n+ [(set (match_operand:V_VLSI 0 \"register_operand\" \"=vd,vd, vr,vr\")\n+ (if_then_else:V_VLSI\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm,vm,Wc1,Wc1\")\n (match_operand 5 \"vector_length_operand\" \" rK,rK, rK, rK\")\n@@ -273,10 +273,10 @@ (define_insn \"*pred_vror<mode>_scalar\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (rotatert:VI\n- (match_operand:VI 3 \"register_operand\" \" vr,vr, vr, vr\")\n+ (rotatert:V_VLSI\n+ (match_operand:V_VLSI 3 \"register_operand\" \" vr,vr, vr, vr\")\n (match_operand 4 \"const_csr_operand\" \" K, K, K, K\"))\n- (match_operand:VI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+ (match_operand:V_VLSI 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_ZVBB || TARGET_ZVKB\"\n \"vror.vi\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vror\")\n@@ -365,8 +365,8 @@ (define_insn \"@pred_v<bitmanip_optab><mode>\"\n ;; vclmul.vv vclmul.vx\n ;; vclmulh.vv vclmulh.vx\n (define_insn \"@pred_vclmul<h><mode>\"\n- [(set (match_operand:VI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n- (if_then_else:VI_D\n+ [(set (match_operand:V_VLSI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n+ (if_then_else:V_VLSI_D\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \"vm,Wc1,vm,Wc1\")\n (match_operand 5 \"vector_length_operand\" \"rK, rK,rK, rK\")\n@@ -375,10 +375,10 @@ (define_insn \"@pred_vclmul<h><mode>\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VI_D\n- [(match_operand:VI_D 3 \"register_operand\" \"vr, vr,vr, vr\")\n- (match_operand:VI_D 4 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n- (match_operand:VI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n+ (unspec:V_VLSI_D\n+ [(match_operand:V_VLSI_D 3 \"register_operand\" \"vr, vr,vr, vr\")\n+ (match_operand:V_VLSI_D 4 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n+ (match_operand:V_VLSI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n \"TARGET_ZVBC\"\n \"vclmul<h>.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vclmul<h>\")\n@@ -386,8 +386,8 @@ (define_insn \"@pred_vclmul<h><mode>\"\n \n ;; Deal with SEW = 64 in RV32 system.\n (define_expand \"@pred_vclmul<h><mode>_scalar\"\n- [(set (match_operand:VI_D 0 \"register_operand\")\n- (if_then_else:VI_D\n+ [(set (match_operand:V_VLSI_D 0 \"register_operand\")\n+ (if_then_else:V_VLSI_D\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\")\n (match_operand 5 \"vector_length_operand\")\n@@ -396,11 +396,11 @@ (define_expand \"@pred_vclmul<h><mode>_scalar\"\n (match_operand 8 \"const_int_operand\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VI_D\n- [(vec_duplicate:VI_D\n+ (unspec:V_VLSI_D\n+ [(vec_duplicate:V_VLSI_D\n (match_operand:<VEL> 4 \"register_operand\"))\n- (match_operand:VI_D 3 \"register_operand\")] UNSPEC_CLMUL_VC)\n- (match_operand:VI_D 2 \"vector_merge_operand\")))]\n+ (match_operand:V_VLSI_D 3 \"register_operand\")] UNSPEC_CLMUL_VC)\n+ (match_operand:V_VLSI_D 2 \"vector_merge_operand\")))]\n \"TARGET_ZVBC\"\n {\n if (riscv_vector::sew64_scalar_helper (\n@@ -419,8 +419,8 @@ (define_expand \"@pred_vclmul<h><mode>_scalar\"\n })\n \n (define_insn \"*pred_vclmul<h><mode>_scalar\"\n- [(set (match_operand:VI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n- (if_then_else:VI_D\n+ [(set (match_operand:V_VLSI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n+ (if_then_else:V_VLSI_D\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \"vm,Wc1,vm,Wc1\")\n (match_operand 5 \"vector_length_operand\" \"rK, rK,rK, rK\")\n@@ -429,19 +429,19 @@ (define_insn \"*pred_vclmul<h><mode>_scalar\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VI_D\n- [(vec_duplicate:VI_D\n+ (unspec:V_VLSI_D\n+ [(vec_duplicate:V_VLSI_D\n (match_operand:<VEL> 4 \"reg_or_0_operand\" \"rJ, rJ,rJ, rJ\"))\n- (match_operand:VI_D 3 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n- (match_operand:VI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n+ (match_operand:V_VLSI_D 3 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n+ (match_operand:V_VLSI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n \"TARGET_ZVBC\"\n \"vclmul<h>.vx\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vclmul<h>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"*pred_vclmul<h><mode>_extend_scalar\"\n- [(set (match_operand:VI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n- (if_then_else:VI_D\n+ [(set (match_operand:V_VLSI_D 0 \"register_operand\" \"=vd,vr,vd, vr\")\n+ (if_then_else:V_VLSI_D\n (unspec:<VM>\n [(match_operand:<VM> 1 \"vector_mask_operand\" \"vm,Wc1,vm,Wc1\")\n (match_operand 5 \"vector_length_operand\" \"rK, rK,rK, rK\")\n@@ -450,12 +450,12 @@ (define_insn \"*pred_vclmul<h><mode>_extend_scalar\"\n (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VI_D\n- [(vec_duplicate:VI_D\n+ (unspec:V_VLSI_D\n+ [(vec_duplicate:V_VLSI_D\n \t (sign_extend:<VEL>\n (match_operand:<VSUBEL> 4 \"reg_or_0_operand\" \" rJ, rJ,rJ, rJ\")))\n- (match_operand:VI_D 3 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n- (match_operand:VI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n+ (match_operand:V_VLSI_D 3 \"register_operand\" \"vr, vr,vr, vr\")] UNSPEC_CLMUL_VC)\n+ (match_operand:V_VLSI_D 2 \"vector_merge_operand\" \"vu, vu, 0, 0\")))]\n \"TARGET_ZVBC\"\n \"vclmul<h>.vx\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vclmul<h>\")\n@@ -487,17 +487,17 @@ (define_insn \"@pred_v<vv_ins1_name><mode>\"\n ;; vaesef.[vv,vs] vaesem.[vv,vs] vaesdf.[vv,vs] vaesdm.[vv,vs]\n ;; vsm4r.[vv,vs]\n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type><mode>\"\n- [(set (match_operand:VSI 0 \"register_operand\" \"=vr\")\n- (if_then_else:VSI\n+ [(set (match_operand:V_VLSI_S 0 \"register_operand\" \"=vr\")\n+ (if_then_else:V_VLSI_S\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \" rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VSI\n- [(match_operand:VSI 1 \"register_operand\" \" 0\")\n- (match_operand:VSI 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:V_VLSI_S\n+ [(match_operand:V_VLSI_S 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED || TARGET_ZVKG\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -505,17 +505,17 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type><mode>\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x1<mode>_scalar\"\n- [(set (match_operand:VSI 0 \"register_operand\" \"=&vr\")\n- (if_then_else:VSI\n+ [(set (match_operand:V_VLSI_S 0 \"register_operand\" \"=&vr\")\n+ (if_then_else:V_VLSI_S\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \" rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VSI\n- [(match_operand:VSI 1 \"register_operand\" \" 0\")\n- (match_operand:VSI 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:V_VLSI_S\n+ [(match_operand:V_VLSI_S 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -523,17 +523,17 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x1<mode>_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x2<mode>_scalar\"\n- [(set (match_operand:<VSIX2> 0 \"register_operand\" \"=&vr\")\n- (if_then_else:<VSIX2>\n+ [(set (match_operand:<V_VLSI_S_X2> 0 \"register_operand\" \"=&vr\")\n+ (if_then_else:<V_VLSI_S_X2>\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \"rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:<VSIX2>\n- [(match_operand:<VSIX2> 1 \"register_operand\" \" 0\")\n- (match_operand:VLMULX2_SI 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:<V_VLSI_S_X2>\n+ [(match_operand:<V_VLSI_S_X2> 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S_LMULX2 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -541,17 +541,17 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x2<mode>_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar\"\n- [(set (match_operand:<VSIX4> 0 \"register_operand\" \"=&vr\")\n- (if_then_else:<VSIX4>\n+ [(set (match_operand:<V_VLSI_S_X4> 0 \"register_operand\" \"=&vr\")\n+ (if_then_else:<V_VLSI_S_X4>\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \" rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:<VSIX4>\n- [(match_operand:<VSIX4> 1 \"register_operand\" \" 0\")\n- (match_operand:VLMULX4_SI 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:<V_VLSI_S_X4>\n+ [(match_operand:<V_VLSI_S_X4> 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S_LMULX4 2 \"register_operand\" \"vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -559,17 +559,17 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar\"\n- [(set (match_operand:<VSIX8> 0 \"register_operand\" \"=&vr\")\n- (if_then_else:<VSIX8>\n+ [(set (match_operand:<V_VLSI_S_X8> 0 \"register_operand\" \"=&vr\")\n+ (if_then_else:<V_VLSI_S_X8>\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \" rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:<VSIX8>\n- [(match_operand:<VSIX8> 1 \"register_operand\" \" 0\")\n- (match_operand:VLMULX8_SI 2 \"register_operand\" \" vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:<V_VLSI_S_X8>\n+ [(match_operand:<V_VLSI_S_X8> 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S_LMULX8 2 \"register_operand\" \" vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -577,17 +577,17 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar\"\n- [(set (match_operand:<VSIX16> 0 \"register_operand\" \"=&vr\")\n- (if_then_else:<VSIX16>\n+ [(set (match_operand:<V_VLSI_S_X16> 0 \"register_operand\" \"=&vr\")\n+ (if_then_else:<V_VLSI_S_X16>\n (unspec:<VM>\n [(match_operand 3 \"vector_length_operand\" \" rK\")\n (match_operand 4 \"const_int_operand\" \" i\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:<VSIX16>\n- [(match_operand:<VSIX16> 1 \"register_operand\" \" 0\")\n- (match_operand:VLMULX16_SI 2 \"register_operand\" \" vr\")] UNSPEC_CRYPTO_VV)\n+ (unspec:<V_VLSI_S_X16>\n+ [(match_operand:<V_VLSI_S_X16> 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S_LMULX16 2 \"register_operand\" \" vr\")] UNSPEC_CRYPTO_VV)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vv_ins_name>.<ins_type>\\t%0,%2\"\n@@ -596,18 +596,18 @@ (define_insn \"@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar\"\n \n ;; vaeskf1.vi vsm4k.vi\n (define_insn \"@pred_crypto_vi<vi_ins_name><mode>_scalar\"\n- [(set (match_operand:VSI 0 \"register_operand\" \"=vr, vr\")\n- (if_then_else:VSI\n+ [(set (match_operand:V_VLSI_S 0 \"register_operand\" \"=vr, vr\")\n+ (if_then_else:V_VLSI_S\n (unspec:<VM>\n [(match_operand 4 \"vector_length_operand\" \"rK, rK\")\n (match_operand 5 \"const_int_operand\" \" i, i\")\n (match_operand 6 \"const_int_operand\" \" i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VSI\n- [(match_operand:VSI 2 \"register_operand\" \"vr, vr\")\n+ (unspec:V_VLSI_S\n+ [(match_operand:V_VLSI_S 2 \"register_operand\" \"vr, vr\")\n (match_operand 3 \"const_int_operand\" \" i, i\")] UNSPEC_CRYPTO_VI)\n- (match_operand:VSI 1 \"vector_merge_operand\" \"vu, 0\")))]\n+ (match_operand:V_VLSI_S 1 \"vector_merge_operand\" \"vu, 0\")))]\n \"TARGET_ZVKNED || TARGET_ZVKSED\"\n \"v<vi_ins_name>.vi\\t%0,%2,%3\"\n [(set_attr \"type\" \"v<vi_ins_name>\")\n@@ -615,17 +615,17 @@ (define_insn \"@pred_crypto_vi<vi_ins_name><mode>_scalar\"\n \n ;; vaeskf2.vi vsm3c.vi\n (define_insn \"@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar\"\n- [(set (match_operand:VSI 0 \"register_operand\" \"=vr\")\n- (if_then_else:VSI\n+ [(set (match_operand:V_VLSI_S 0 \"register_operand\" \"=vr\")\n+ (if_then_else:V_VLSI_S\n (unspec:<VM>\n [(match_operand 4 \"vector_length_operand\" \"rK\")\n (match_operand 5 \"const_int_operand\" \" i\")\n (match_operand 6 \"const_int_operand\" \" i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VSI\n- [(match_operand:VSI 1 \"register_operand\" \" 0\")\n- (match_operand:VSI 2 \"register_operand\" \"vr\")\n+ (unspec:V_VLSI_S\n+ [(match_operand:V_VLSI_S 1 \"register_operand\" \" 0\")\n+ (match_operand:V_VLSI_S 2 \"register_operand\" \"vr\")\n (match_operand 3 \"const_int_operand\" \" i\")] UNSPEC_CRYPTO_VI1)\n (match_dup 1)))]\n \"TARGET_ZVKNED || TARGET_ZVKSH\"\n@@ -636,18 +636,18 @@ (define_insn \"@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar\"\n ;; zvksh instructions patterns.\n ;; vsm3me.vv\n (define_insn \"@pred_vsm3me<mode>\"\n- [(set (match_operand:VSI 0 \"register_operand\" \"=vr, vr\")\n- (if_then_else:VSI\n+ [(set (match_operand:V_VLSI_S 0 \"register_operand\" \"=vr, vr\")\n+ (if_then_else:V_VLSI_S\n (unspec:<VM>\n [(match_operand 4 \"vector_length_operand\" \" rK, rK\")\n (match_operand 5 \"const_int_operand\" \" i, i\")\n (match_operand 6 \"const_int_operand\" \" i, i\")\n (reg:SI VL_REGNUM)\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n- (unspec:VSI\n- [(match_operand:VSI 2 \"register_operand\" \" vr, vr\")\n- (match_operand:VSI 3 \"register_operand\" \" vr, vr\")] UNSPEC_VSM3ME)\n- (match_operand:VSI 1 \"vector_merge_operand\" \" vu, 0\")))]\n+ (unspec:V_VLSI_S\n+ [(match_operand:V_VLSI_S 2 \"register_operand\" \" vr, vr\")\n+ (match_operand:V_VLSI_S 3 \"register_operand\" \" vr, vr\")] UNSPEC_VSM3ME)\n+ (match_operand:V_VLSI_S 1 \"vector_merge_operand\" \" vu, 0\")))]\n \"TARGET_ZVKSH\"\n \"vsm3me.vv\\t%0,%2,%3\"\n [(set_attr \"type\" \"vsm3me\")\ndiff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md\nindex b6282607ceb..878c7ed9db7 100644\n--- a/gcc/config/riscv/vector-iterators.md\n+++ b/gcc/config/riscv/vector-iterators.md\n@@ -845,6 +845,32 @@ (define_mode_iterator VI_QH [\n RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI \"TARGET_VECTOR_ELEN_64\")\n \n RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1QI \"riscv_vector::vls_mode_valid_p (V1QImode)\")\n+ (V2QI \"riscv_vector::vls_mode_valid_p (V2QImode)\")\n+ (V4QI \"riscv_vector::vls_mode_valid_p (V4QImode)\")\n+ (V8QI \"riscv_vector::vls_mode_valid_p (V8QImode)\")\n+ (V16QI \"riscv_vector::vls_mode_valid_p (V16QImode)\")\n+ (V32QI \"riscv_vector::vls_mode_valid_p (V32QImode)\")\n+ (V64QI \"riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64\")\n+ (V128QI \"riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128\")\n+ (V256QI \"riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256\")\n+ (V512QI \"riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512\")\n+ (V1024QI \"riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024\")\n+ (V2048QI \"riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048\")\n+ (V4096QI \"riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096\")\n+ (V1HI \"riscv_vector::vls_mode_valid_p (V1HImode)\")\n+ (V2HI \"riscv_vector::vls_mode_valid_p (V2HImode)\")\n+ (V4HI \"riscv_vector::vls_mode_valid_p (V4HImode)\")\n+ (V8HI \"riscv_vector::vls_mode_valid_p (V8HImode)\")\n+ (V16HI \"riscv_vector::vls_mode_valid_p (V16HImode)\")\n+ (V32HI \"riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64\")\n+ (V64HI \"riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128\")\n+ (V128HI \"riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256\")\n+ (V256HI \"riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512\")\n+ (V512HI \"riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024\")\n+ (V1024HI \"riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048\")\n+ (V2048HI \"riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096\")\n ])\n \n (define_mode_iterator VI_QHS [\n@@ -5852,40 +5878,128 @@ (define_mode_iterator VLS_AVL_REG [\n (V2048BI \"riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048\")\n (V4096BI \"riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096\")])\n \n-(define_mode_iterator VSI [\n+(define_mode_iterator V_VLSI_S [\n RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1SI \"riscv_vector::vls_mode_valid_p (V1SImode)\")\n+ (V2SI \"riscv_vector::vls_mode_valid_p (V2SImode)\")\n+ (V4SI \"riscv_vector::vls_mode_valid_p (V4SImode)\")\n+ (V8SI \"riscv_vector::vls_mode_valid_p (V8SImode)\")\n+ (V16SI \"riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64\")\n+ (V32SI \"riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128\")\n+ (V64SI \"riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256\")\n+ (V128SI \"riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512\")\n+ (V256SI \"riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024\")\n+ (V512SI \"riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048\")\n+ (V1024SI \"riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096\")\n ])\n \n-(define_mode_iterator VLMULX2_SI [\n+(define_mode_iterator V_VLSI_S_LMULX2 [\n RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1SI \"riscv_vector::vls_mode_valid_p (V1SImode)\")\n+ (V2SI \"riscv_vector::vls_mode_valid_p (V2SImode)\")\n+ (V4SI \"riscv_vector::vls_mode_valid_p (V4SImode)\")\n+ (V8SI \"riscv_vector::vls_mode_valid_p (V8SImode)\")\n+ (V16SI \"riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64\")\n+ (V32SI \"riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128\")\n+ (V64SI \"riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256\")\n+ (V128SI \"riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512\")\n+ (V256SI \"riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024\")\n+ (V512SI \"riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048\")\n ])\n \n-(define_mode_iterator VLMULX4_SI [\n+(define_mode_iterator V_VLSI_S_LMULX4 [\n RVVM2SI RVVM1SI (RVVMF2SI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1SI \"riscv_vector::vls_mode_valid_p (V1SImode)\")\n+ (V2SI \"riscv_vector::vls_mode_valid_p (V2SImode)\")\n+ (V4SI \"riscv_vector::vls_mode_valid_p (V4SImode)\")\n+ (V8SI \"riscv_vector::vls_mode_valid_p (V8SImode)\")\n+ (V16SI \"riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64\")\n+ (V32SI \"riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128\")\n+ (V64SI \"riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256\")\n+ (V128SI \"riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512\")\n+ (V256SI \"riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024\")\n ])\n \n-(define_mode_iterator VLMULX8_SI [\n+(define_mode_iterator V_VLSI_S_LMULX8 [\n RVVM1SI (RVVMF2SI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1SI \"riscv_vector::vls_mode_valid_p (V1SImode)\")\n+ (V2SI \"riscv_vector::vls_mode_valid_p (V2SImode)\")\n+ (V4SI \"riscv_vector::vls_mode_valid_p (V4SImode)\")\n+ (V8SI \"riscv_vector::vls_mode_valid_p (V8SImode)\")\n+ (V16SI \"riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64\")\n+ (V32SI \"riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128\")\n+ (V64SI \"riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256\")\n+ (V128SI \"riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512\")\n ])\n \n-(define_mode_iterator VLMULX16_SI [\n+(define_mode_iterator V_VLSI_S_LMULX16 [\n (RVVMF2SI \"TARGET_VECTOR_ELEN_64\")\n+\n+ (V1SI \"riscv_vector::vls_mode_valid_p (V1SImode)\")\n+ (V2SI \"riscv_vector::vls_mode_valid_p (V2SImode)\")\n+ (V4SI \"riscv_vector::vls_mode_valid_p (V4SImode)\")\n+ (V8SI \"riscv_vector::vls_mode_valid_p (V8SImode)\")\n+ (V16SI \"riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64\")\n+ (V32SI \"riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128\")\n+ (V64SI \"riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256\")\n ])\n \n-(define_mode_attr VSIX2 [\n- (RVVM8SI \"RVVM8SI\") (RVVM4SI \"RVVM8SI\") (RVVM2SI \"RVVM4SI\") (RVVM1SI \"RVVM2SI\") (RVVMF2SI \"RVVM1SI\")\n+(define_mode_attr V_VLSI_S_X2 [\n+ (RVVM4SI \"RVVM8SI\") (RVVM2SI \"RVVM4SI\") (RVVM1SI \"RVVM2SI\") (RVVMF2SI \"RVVM1SI\")\n+\n+ (V1SI \"V2SI\")\n+ (V2SI \"V4SI\")\n+ (V4SI \"V8SI\")\n+ (V8SI \"V16SI\")\n+ (V16SI \"V32SI\")\n+ (V32SI \"V64SI\")\n+ (V64SI \"V128SI\")\n+ (V128SI \"V256SI\")\n+ (V256SI \"V512SI\")\n+ (V512SI \"V1024SI\")\n ])\n \n-(define_mode_attr VSIX4 [\n+(define_mode_attr V_VLSI_S_X4 [\n (RVVM2SI \"RVVM8SI\") (RVVM1SI \"RVVM4SI\") (RVVMF2SI \"RVVM2SI\")\n+\n+ (V1SI \"V4SI\")\n+ (V2SI \"V8SI\")\n+ (V4SI \"V16SI\")\n+ (V8SI \"V32SI\")\n+ (V16SI \"V64SI\")\n+ (V32SI \"V128SI\")\n+ (V64SI \"V256SI\")\n+ (V128SI \"V512SI\")\n+ (V256SI \"V1024SI\")\n ])\n \n-(define_mode_attr VSIX8 [\n+(define_mode_attr V_VLSI_S_X8 [\n (RVVM1SI \"RVVM8SI\") (RVVMF2SI \"RVVM4SI\")\n+\n+ (V1SI \"V8SI\")\n+ (V2SI \"V16SI\")\n+ (V4SI \"V32SI\")\n+ (V8SI \"V64SI\")\n+ (V16SI \"V128SI\")\n+ (V32SI \"V256SI\")\n+ (V64SI \"V512SI\")\n+ (V128SI \"V1024SI\")\n ])\n \n-(define_mode_attr VSIX16 [\n+(define_mode_attr V_VLSI_S_X16 [\n (RVVMF2SI \"RVVM8SI\")\n+\n+ (V1SI \"V16SI\")\n+ (V2SI \"V32SI\")\n+ (V4SI \"V64SI\")\n+ (V8SI \"V128SI\")\n+ (V16SI \"V256SI\")\n+ (V32SI \"V512SI\")\n+ (V64SI \"V1024SI\")\n ])\n \n (define_mode_iterator VLS_HAS_HALF [\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex fb23f49c603..8175fada642 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -1033,15 +1033,15 @@ (define_attr \"frm_mode\" \"\"\n ;; -----------------------------------------------------------------\n \n (define_insn \"@vundefined<mode>\"\n- [(set (match_operand:V 0 \"register_operand\" \"=vr\")\n-\t(unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]\n+ [(set (match_operand:V_VLS 0 \"register_operand\" \"=vr\")\n+\t(unspec:V_VLS [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]\n \"TARGET_VECTOR\"\n \"\"\n [(set_attr \"type\" \"vector\")])\n \n (define_insn \"@vundefined<mode>\"\n- [(set (match_operand:VB 0 \"register_operand\" \"=vr\")\n-\t(unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]\n+ [(set (match_operand:VB_VLS 0 \"register_operand\" \"=vr\")\n+\t(unspec:VB_VLS [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]\n \"TARGET_VECTOR\"\n \"\"\n [(set_attr \"type\" \"vector\")])\n@@ -1054,7 +1054,7 @@ (define_insn \"@vundefined<mode>\"\n [(set_attr \"type\" \"vector\")])\n \n (define_expand \"@vreinterpret<mode>\"\n- [(set (match_operand:V 0 \"register_operand\")\n+ [(set (match_operand:V_VLS 0 \"register_operand\")\n \t(match_operand 1 \"vector_any_register_operand\"))]\n \"TARGET_VECTOR\"\n {\n@@ -1974,15 +1974,15 @@ (define_insn_and_split \"*pred_mov<mode>\"\n ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include\n ;; memory operand as input which will produce inferior codegen.\n (define_insn \"@pred_store<mode>\"\n- [(set (match_operand:V 0 \"memory_operand\" \"+m\")\n-\t(if_then_else:V\n+ [(set (match_operand:V_VLS 0 \"memory_operand\" \"+m\")\n+\t(if_then_else:V_VLS\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \"vmWc1\")\n \t (match_operand 3 \"vector_length_operand\" \" rvl\")\n \t (match_operand 4 \"const_int_operand\" \" i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:V 2 \"register_operand\" \" vr\")\n+\t (match_operand:V_VLS 2 \"register_operand\" \" vr\")\n \t (match_dup 0)))]\n \"TARGET_VECTOR\"\n \"vse<sew>.v\\t%2,%0%p1\"\n@@ -6260,14 +6260,14 @@ (define_insn \"@pred_popcount<VB_VLS:mode><P:mode>\"\n [(set_attr \"type\" \"vmpop\")\n (set_attr \"mode\" \"<VB_VLS:MODE>\")])\n \n-(define_insn \"@pred_ffs<VB:mode><P:mode>\"\n+(define_insn \"@pred_ffs<VB_VLS:mode><P:mode>\"\n [(set (match_operand:P 0 \"register_operand\" \"=r\")\n \t(plus:P\n \t (ffs:P\n-\t (unspec:VB\n-\t [(and:VB\n-\t (match_operand:VB 1 \"vector_mask_operand\" \"vmWc1\")\n-\t (match_operand:VB 2 \"register_operand\" \" vr\"))\n+\t (unspec:VB_VLS\n+\t [(and:VB_VLS\n+\t (match_operand:VB_VLS 1 \"vector_mask_operand\" \"vmWc1\")\n+\t (match_operand:VB_VLS 2 \"register_operand\" \" vr\"))\n \t (match_operand 3 \"vector_length_operand\" \" rvl\")\n \t (match_operand 4 \"const_int_operand\" \" i\")\n \t (reg:SI VL_REGNUM)\n@@ -6276,29 +6276,29 @@ (define_insn \"@pred_ffs<VB:mode><P:mode>\"\n \"TARGET_VECTOR\"\n \"vfirst.m\\t%0,%2%p1\"\n [(set_attr \"type\" \"vmffs\")\n- (set_attr \"mode\" \"<VB:MODE>\")])\n+ (set_attr \"mode\" \"<VB_VLS:MODE>\")])\n \n (define_insn \"@pred_<misc_op><mode>\"\n- [(set (match_operand:VB 0 \"register_operand\" \"=&vr, &vr\")\n-\t(if_then_else:VB\n-\t (unspec:VB\n-\t [(match_operand:VB 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n+ [(set (match_operand:VB_VLS 0 \"register_operand\" \"=&vr, &vr\")\n+\t(if_then_else:VB_VLS\n+\t (unspec:VB_VLS\n+\t [(match_operand:VB_VLS 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n \t (match_operand 4 \"vector_length_operand\" \" rvl, rvl\")\n \t (match_operand 5 \"const_int_operand\" \" i, i\")\n \t (match_operand 6 \"const_int_operand\" \" i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:VB\n-\t [(match_operand:VB 3 \"register_operand\" \" vr, vr\")] VMISC)\n-\t (match_operand:VB 2 \"vector_merge_operand\" \" vu, 0\")))]\n+\t (unspec:VB_VLS\n+\t [(match_operand:VB_VLS 3 \"register_operand\" \" vr, vr\")] VMISC)\n+\t (match_operand:VB_VLS 2 \"vector_merge_operand\" \" vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vm<misc_op>.m\\t%0,%3%p1\"\n [(set_attr \"type\" \"vmsfs\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_iota<mode>\"\n- [(set (match_operand:VI 0 \"register_operand\" \"=&vr, &vr\")\n-\t(if_then_else:VI\n+ [(set (match_operand:V_VLSI 0 \"register_operand\" \"=&vr, &vr\")\n+\t(if_then_else:V_VLSI\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n \t (match_operand 4 \"vector_length_operand\" \" rvl, rvl\")\n@@ -6307,9 +6307,9 @@ (define_insn \"@pred_iota<mode>\"\n \t (match_operand 7 \"const_int_operand\" \" i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:VI\n+\t (unspec:V_VLSI\n \t [(match_operand:<VM> 3 \"register_operand\" \" vr, vr\")] UNSPEC_VIOTA)\n-\t (match_operand:VI 2 \"vector_merge_operand\" \" vu, 0\")))]\n+\t (match_operand:V_VLSI 2 \"vector_merge_operand\" \" vu, 0\")))]\n \"TARGET_VECTOR\"\n \"viota.m\\t%0,%3%p1\"\n [(set_attr \"type\" \"vmiota\")\n@@ -6547,8 +6547,8 @@ (define_insn \"@pred_<copysign><mode>\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_ncopysign<mode>\"\n- [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n-\t(if_then_else:VF\n+ [(set (match_operand:V_VLSF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n+\t(if_then_else:V_VLSF\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1\")\n \t (match_operand 5 \"vector_length_operand\" \"rvl,rvl,rvl,rvl\")\n@@ -6557,11 +6557,11 @@ (define_insn \"@pred_ncopysign<mode>\"\n \t (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (neg:VF\n-\t (unspec:VF\n-\t [(match_operand:VF 3 \"register_operand\" \" vr, vr, vr, vr\")\n-\t (match_operand:VF 4 \"register_operand\" \" vr, vr, vr, vr\")] UNSPEC_VCOPYSIGN))\n-\t (match_operand:VF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+\t (neg:V_VLSF\n+\t (unspec:V_VLSF\n+\t [(match_operand:V_VLSF 3 \"register_operand\" \" vr, vr, vr, vr\")\n+\t (match_operand:V_VLSF 4 \"register_operand\" \" vr, vr, vr, vr\")] UNSPEC_VCOPYSIGN))\n+\t (match_operand:V_VLSF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vfsgnjn.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfsgnj\")\n@@ -6589,8 +6589,8 @@ (define_insn \"@pred_<copysign><mode>_scalar\"\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_ncopysign<mode>_scalar\"\n- [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n-\t(if_then_else:VF\n+ [(set (match_operand:V_VLSF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n+\t(if_then_else:V_VLSF\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1\")\n \t (match_operand 5 \"vector_length_operand\" \"rvl,rvl,rvl,rvl\")\n@@ -6599,12 +6599,12 @@ (define_insn \"@pred_ncopysign<mode>_scalar\"\n \t (match_operand 8 \"const_int_operand\" \" i, i, i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (neg:VF\n-\t (unspec:VF\n-\t [(match_operand:VF 3 \"register_operand\" \" vr, vr, vr, vr\")\n-\t (vec_duplicate:VF\n+\t (neg:V_VLSF\n+\t (unspec:V_VLSF\n+\t [(match_operand:V_VLSF 3 \"register_operand\" \" vr, vr, vr, vr\")\n+\t (vec_duplicate:V_VLSF\n \t\t (match_operand:<VEL> 4 \"register_operand\" \" f, f, f, f\"))] UNSPEC_VCOPYSIGN))\n-\t (match_operand:VF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+\t (match_operand:V_VLSF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vfsgnjn.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfsgnj\")\n@@ -7175,8 +7175,8 @@ (define_insn \"@pred_<optab><mode>\"\n (set (attr \"avl_type_idx\") (const_int 7))])\n \n (define_insn \"@pred_<misc_op><mode>\"\n- [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n-\t(if_then_else:VF\n+ [(set (match_operand:V_VLSF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n+\t(if_then_else:V_VLSF\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1\")\n \t (match_operand 4 \"vector_length_operand\" \"rvl,rvl,rvl,rvl\")\n@@ -7185,17 +7185,17 @@ (define_insn \"@pred_<misc_op><mode>\"\n \t (match_operand 7 \"const_int_operand\" \" i, i, i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:VF\n-\t [(match_operand:VF 3 \"register_operand\" \" vr, vr, vr, vr\")] VFMISC)\n-\t (match_operand:VF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+\t (unspec:V_VLSF\n+\t [(match_operand:V_VLSF 3 \"register_operand\" \" vr, vr, vr, vr\")] VFMISC)\n+\t (match_operand:V_VLSF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vf<misc_op>.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"<float_insn_type>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"@pred_<misc_frm_op><mode>\"\n- [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n-\t(if_then_else:VF\n+ [(set (match_operand:V_VLSF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n+\t(if_then_else:V_VLSF\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1\")\n \t (match_operand 4 \"vector_length_operand\" \"rvl,rvl,rvl,rvl\")\n@@ -7206,9 +7206,9 @@ (define_insn \"@pred_<misc_frm_op><mode>\"\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)\n \t (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:VF\n-\t [(match_operand:VF 3 \"register_operand\" \" vr, vr, vr, vr\")] VFMISC_FRM)\n-\t (match_operand:VF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n+\t (unspec:V_VLSF\n+\t [(match_operand:V_VLSF 3 \"register_operand\" \" vr, vr, vr, vr\")] VFMISC_FRM)\n+\t (match_operand:V_VLSF 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vf<misc_frm_op>.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"<float_frm_insn_type>\")\n@@ -7228,7 +7228,7 @@ (define_insn \"@pred_class<mode>\"\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n \t (unspec:<VCONVERT>\n-\t [(match_operand:VF 3 \"register_operand\" \" vr, vr, vr, vr\")] UNSPEC_VFCLASS)\n+\t [(match_operand:V_VLSF 3 \"register_operand\" \" vr, vr, vr, vr\")] UNSPEC_VFCLASS)\n \t (match_operand:<VCONVERT> 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))]\n \"TARGET_VECTOR\"\n \"vfclass.v\\t%0,%3%p1\"\n@@ -8552,8 +8552,8 @@ (define_insn \"read_vldi_zero_extend\"\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"@pred_fault_load<mode>\"\n- [(set (match_operand:V 0 \"register_operand\" \"=vd, vd, vr, vr\")\n-\t(if_then_else:V\n+ [(set (match_operand:V_VLS 0 \"register_operand\" \"=vd, vd, vr, vr\")\n+\t(if_then_else:V_VLS\n \t (unspec:<VM>\n \t [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm, Wc1, Wc1\")\n \t (match_operand 4 \"vector_length_operand\" \" rvl, rvl, rvl, rvl\")\n@@ -8562,17 +8562,17 @@ (define_insn \"@pred_fault_load<mode>\"\n \t (match_operand 7 \"const_int_operand\" \" i, i, i, i\")\n \t (reg:SI VL_REGNUM)\n \t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:V\n-\t [(match_operand:V 3 \"memory_operand\" \" m, m, m, m\")] UNSPEC_VLEFF)\n-\t (match_operand:V 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))\n+\t (unspec:V_VLS\n+\t [(match_operand:V_VLS 3 \"memory_operand\" \" m, m, m, m\")] UNSPEC_VLEFF)\n+\t (match_operand:V_VLS 2 \"vector_merge_operand\" \" vu, 0, vu, 0\")))\n (set (reg:SI VL_REGNUM)\n \t (unspec:SI\n-\t [(if_then_else:V\n+\t [(if_then_else:V_VLS\n \t (unspec:<VM>\n \t\t[(match_dup 1) (match_dup 4) (match_dup 5)\n \t\t (match_dup 6) (match_dup 7)\n \t\t (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (unspec:V [(match_dup 3)] UNSPEC_VLEFF)\n+\t (unspec:V_VLS [(match_dup 3)] UNSPEC_VLEFF)\n \t (match_dup 2))] UNSPEC_MODIFY_VL))]\n \"TARGET_VECTOR\"\n \"vle<sew>ff.v\\t%0,%3%p1\"\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c\nindex 4acac8f7efd..6b46c4f782e 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c\n@@ -40,6 +40,7 @@\n \n TEST_ALL (TEST_LOOP)\n \n-/* { dg-final { scan-tree-dump-times \" \\.MASK_LEN_STRIDED_STORE \" 44 \"optimized\" } } */\n+/* { dg-final { scan-tree-dump-times \" \\.MASK_LEN_STRIDED_STORE \" 44 \"optimized\" { target { no-opts \"-mrvv-max-lmul=dynamic\" \"-mrvv-max-lmul=m8\" } } } } */\n+/* { dg-final { scan-tree-dump-times \" \\.MASK_LEN_STRIDED_STORE \" 49 \"optimized\" { target { any-opts \"-mrvv-max-lmul=dynamic\" \"-mrvv-max-lmul=m8\" } } } } */\n /* { dg-final { scan-tree-dump-not \" \\.SCATTER_STORE\" \"optimized\" } } */\n /* { dg-final { scan-tree-dump-not \" \\.MASK_SCATTER_STORE\" \"optimized\" } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c\nindex 1ee7eb32e37..56038428626 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c\n@@ -13,4 +13,4 @@ foo (int *a, int *b, int n)\n }\n \n /* { dg-final { scan-tree-dump \"Choosing vector mode V4QI\" \"vect\" } } */\n-/* { dg-final { scan-tree-dump \"Choosing epilogue vector mode RVVM1SI\" \"vect\" } } */\n+/* { dg-final { scan-tree-dump \"operating on partial vectors.\" \"vect\" } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c\nindex a96e6ffa315..eb4ca624cd4 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c\n@@ -6,12 +6,10 @@\n \n /*\n ** foo:\n-**\tvsetivli\\t[a-x0-9]+,\\s*8,\\s*e(8?|16?|32?|64),\\s*m(1?|2?|4?|8?|f2?|f4?|f8),\\s*t[au],\\s*m[au]\n+** vsetivli\\tzero,\\s*4,\\s*e(8?|16?|32?|64),\\s*m(1?|2?|4?|8?|f2?|f4?|f8),\\s*t[au],\\s*m[au]\n **\t...\n **\tvle32\\.v\\tv[0-9]+,0\\([a-x0-9]+\\)\n **\t...\n-**\tvsetvli\\tzero,\\s*[a-x0-9]+,\\s*e(8?|16?|32?|64),\\s*m(1?|2?|4?|8?|f2?|f4?|f8),\\s*t[au],\\s*m[au]\n-**\t...\n **\tvle32\\.v\\tv[0-9]+,0\\([a-x0-9]+\\)\n **\t...\n */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c\nindex 58c30e87bfc..7ba1239adc2 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c\n@@ -3,4 +3,7 @@\n \n #include \"template-1.h\"\n \n-/* { dg-final { scan-tree-dump-times \"vectorized 1 loops in function\" 6 \"vect\" } } */\n+/* With length-control for VLS modes we don't vectorize foo4 anymore.\n+ That's due to a very tight costing decision in the small loop.\n+ Therefore expect 5 instead of 6 vectorized loops. */\n+/* { dg-final { scan-tree-dump-times \"vectorized 1 loops in function\" 5 \"vect\" } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c\nindex 35da49d13d7..e09b3989684 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c\n@@ -3,4 +3,7 @@\n \n #include \"template-1.h\"\n \n-/* { dg-final { scan-tree-dump-times \"vectorized 1 loops in function\" 5 \"vect\" } } */\n+/* Same as in zve64d-1.c we don't vectorize foo4 anymore due to an\n+ unfortunately tight costing decision. Therefore expect 4 instead of 5\n+ vectorized loops. */\n+/* { dg-final { scan-tree-dump-times \"vectorized 1 loops in function\" 4 \"vect\" } } */\n", "prefixes": [ "v3", "3/4" ] }