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GET /api/1.0/patches/2175317/?format=api
{ "id": 2175317, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175317/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217190018.487429-3-rdapp@ventanamicro.com>", "date": "2025-12-17T19:00:16", "name": "[v3,2/4] RISC-V: Rename vector-mode related functions.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "93e1196b96e532d73e1675a022cc46c9c0cc2794", "submitter": { "id": 86205, "url": "http://patchwork.ozlabs.org/api/1.0/people/86205/?format=api", "name": "Robin Dapp", "email": "rdapp.gcc@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20251217190018.487429-3-rdapp@ventanamicro.com/mbox/", "series": [ { "id": 485748, "url": "http://patchwork.ozlabs.org/api/1.0/series/485748/?format=api", "date": "2025-12-17T19:00:18", "name": "VLS-related stuff.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485748/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175317/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=Gp70FPwt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=Gp70FPwt", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "sourceware.org; spf=pass smtp.mailfrom=gmail.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=209.85.208.42" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWjnz2kWdz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 06:01:43 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 5C54A4BA2E2A\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 19:01:41 +0000 (GMT)", "from mail-ed1-f42.google.com (mail-ed1-f42.google.com\n [209.85.208.42])\n by sourceware.org (Postfix) with ESMTPS id D69BB4BA2E22\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 19:00:24 +0000 (GMT)", "by mail-ed1-f42.google.com with SMTP id\n 4fb4d7f45d1cf-640c6577120so9098937a12.1\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 11:00:24 -0800 (PST)", "from x1c10.dc1.ventanamicro.com\n (ip-149-172-150-237.um42.pools.vodafone-ip.de. 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related functions.", "Date": "Wed, 17 Dec 2025 20:00:16 +0100", "Message-ID": "<20251217190018.487429-3-rdapp@ventanamicro.com>", "X-Mailer": "git-send-email 2.51.1", "In-Reply-To": "<20251217190018.487429-1-rdapp@ventanamicro.com>", "References": "<20251217190018.487429-1-rdapp@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch just performs renaming from e.g.\n riscv_v_ext_vector_mode_p to\n riscv_vector_mode_p\nand similar.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-avlprop.cc (pass_avlprop::execute):\n\t* config/riscv/riscv-protos.h (riscv_v_ext_vector_mode_p):\n\t(riscv_v_ext_tuple_mode_p): Rename.\n\t(riscv_v_ext_vls_mode_p): Ditto.\n\t(riscv_vla_mode_p): To new name.\n\t(riscv_tuple_mode_p): Ditto.\n\t(riscv_vls_mode_p): Ditto.\n\t* config/riscv/riscv-selftests.cc (run_const_vector_selftests):\n\tUse new name.\n\t(BROADCAST_TEST): Ditto.\n\t* config/riscv/riscv-v.cc (imm_avl_p): Ditto.\n\t(legitimize_move): Ditto.\n\t(get_vlmul): Ditto.\n\t(get_vlmax_rtx): Ditto.\n\t(get_nf): Ditto.\n\t(get_subpart_mode): Ditto.\n\t(get_ratio): Ditto.\n\t(get_mask_mode): Ditto.\n\t(get_vector_mode): Ditto.\n\t(get_tuple_mode): Ditto.\n\t(can_find_related_mode_p): Ditto.\n\t(cmp_lmul_le_one): Ditto.\n\t(cmp_lmul_gt_one): Ditto.\n\t(vls_mode_valid_p): Ditto.\n\t* config/riscv/riscv-vector-builtins-bases.cc: Ditto.\n\t* config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher): Ditto.\n\t(register_builtin_type): Ditto.\n\t* config/riscv/riscv-vector-costs.cc (max_number_of_live_regs):\n\tDitto.\n\t(compute_estimated_lmul): Ditto.\n\t(costs::costs): Ditto.\n\t(costs::better_main_loop_than_p): Ditto.\n\t(costs::adjust_stmt_cost): Ditto.\n\t* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): Ditto.\n\t(riscv_vla_mode_p): Ditto.\n\t(riscv_v_ext_tuple_mode_p): Ditto.\n\t(riscv_tuple_mode_p): Ditto.\n\t(riscv_v_ext_vls_mode_p): Ditto.\n\t(riscv_vls_mode_p): Ditto.\n\t(riscv_v_ext_mode_p): Ditto.\n\t(riscv_vector_mode_p): Ditto.\n\t(riscv_v_adjust_nunits): Ditto.\n\t(riscv_v_adjust_bytesize): Ditto.\n\t(riscv_classify_address): Ditto.\n\t(riscv_legitimate_address_p): Ditto.\n\t(riscv_address_insns): Ditto.\n\t(riscv_const_insns): Ditto.\n\t(riscv_legitimize_move): Ditto.\n\t(riscv_binary_cost): Ditto.\n\t(riscv_rtx_costs): Ditto.\n\t(riscv_pass_vls_aggregate_in_gpr): Ditto.\n\t(riscv_get_vector_arg): Ditto.\n\t(riscv_pass_vls_in_vr): Ditto.\n\t(riscv_get_arg_info): Ditto.\n\t(riscv_pass_by_reference): Ditto.\n\t(riscv_vector_required_min_vlen): Ditto.\n\t(riscv_get_v_regno_alignment): Ditto.\n\t(riscv_print_operand): Ditto.\n\t(riscv_secondary_memory_needed): Ditto.\n\t(riscv_hard_regno_nregs): Ditto.\n\t(riscv_hard_regno_mode_ok): Ditto.\n\t(riscv_modes_tieable_p): Ditto.\n\t(riscv_can_change_mode_class): Ditto.\n\t(riscv_vector_mode_supported_p): Ditto.\n\t(riscv_regmode_natural_size): Ditto.\n\t(riscv_get_mask_mode): Ditto.\n\t(riscv_vectorize_preferred_vector_alignment): Ditto.\n\t(riscv_vectorize_vec_perm_const): Ditto.\n\t(get_common_costs): Ditto.\n\t(riscv_preferred_else_value): Ditto.\n---\n gcc/config/riscv/riscv-avlprop.cc | 2 +-\n gcc/config/riscv/riscv-protos.h | 6 +-\n gcc/config/riscv/riscv-selftests.cc | 8 +-\n gcc/config/riscv/riscv-v.cc | 48 ++++----\n .../riscv/riscv-vector-builtins-bases.cc | 12 +-\n gcc/config/riscv/riscv-vector-builtins.cc | 4 +-\n gcc/config/riscv/riscv-vector-costs.cc | 22 ++--\n gcc/config/riscv/riscv.cc | 104 +++++++++---------\n 8 files changed, 104 insertions(+), 102 deletions(-)", "diff": "diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc\nindex a42764ec9ca..64d8229bb1e 100644\n--- a/gcc/config/riscv/riscv-avlprop.cc\n+++ b/gcc/config/riscv/riscv-avlprop.cc\n@@ -580,7 +580,7 @@ pass_avlprop::execute (function *fn)\n \t\t not all NF registers. Therefore divide the mode size by NF\n \t\t to obtain the proper AVL. */\n \t int nf = 1;\n-\t if (riscv_v_ext_tuple_mode_p (vtype_mode))\n+\t if (riscv_tuple_mode_p (vtype_mode))\n \t\tnf = get_nf (vtype_mode);\n \t rtx new_avl = gen_int_mode\n \t (GET_MODE_NUNITS (vtype_mode).to_constant () / nf, Pmode);\ndiff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h\nindex abf9df77891..e3911c49c50 100644\n--- a/gcc/config/riscv/riscv-protos.h\n+++ b/gcc/config/riscv/riscv-protos.h\n@@ -169,9 +169,9 @@ extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);\n extern bool riscv_gpr_save_operation_p (rtx);\n extern void riscv_reinit (void);\n extern poly_uint64 riscv_regmode_natural_size (machine_mode);\n-extern bool riscv_v_ext_vector_mode_p (machine_mode);\n-extern bool riscv_v_ext_tuple_mode_p (machine_mode);\n-extern bool riscv_v_ext_vls_mode_p (machine_mode);\n+extern bool riscv_vla_mode_p (machine_mode);\n+extern bool riscv_tuple_mode_p (machine_mode);\n+extern bool riscv_vls_mode_p (machine_mode);\n extern int riscv_get_v_regno_alignment (machine_mode);\n extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);\n extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);\ndiff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.cc\nindex d8cc2858541..1e91d2d6de6 100644\n--- a/gcc/config/riscv/riscv-selftests.cc\n+++ b/gcc/config/riscv/riscv-selftests.cc\n@@ -258,7 +258,7 @@ run_const_vector_selftests (void)\n \n FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n \t{\n \t for (const HOST_WIDE_INT &val : worklist)\n \t {\n@@ -282,7 +282,7 @@ run_const_vector_selftests (void)\n \n FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n \t{\n \t scalar_mode inner_mode = GET_MODE_INNER (mode);\n \t REAL_VALUE_TYPE f = REAL_VALUE_ATOF (\"0.2928932\", inner_mode);\n@@ -303,7 +303,7 @@ run_const_vector_selftests (void)\n FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_BOOL)\n {\n /* Test vmset.m. */\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n \t{\n \t start_sequence ();\n \t rtx dest = gen_reg_rtx (mode);\n@@ -330,7 +330,7 @@ run_broadcast_selftests (void)\n #define BROADCAST_TEST(MODE_CLASS) \\\n FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) \\\n { \\\n- if (riscv_v_ext_vector_mode_p (mode)) \\\n+ if (riscv_vla_mode_p (mode))\t\t\t\t\t \\\n \t{ \\\n \t rtx_insn *insn; \\\n \t rtx src; \\\ndiff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex ae8db718b80..e519211d691 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -67,7 +67,7 @@ imm_avl_p (machine_mode mode)\n registers. Therefore divide the mode size by NF before checking if it is\n in range. */\n int nf = 1;\n- if (riscv_v_ext_tuple_mode_p (mode))\n+ if (riscv_tuple_mode_p (mode))\n nf = get_nf (mode);\n \n return nunits.is_constant ()\n@@ -329,7 +329,7 @@ public:\n bool vls_p = false;\n if (m_vlmax_p)\n {\n-\tif (riscv_v_ext_vls_mode_p (vtype_mode))\n+\tif (riscv_vls_mode_p (vtype_mode))\n \t {\n \t /* VLS modes always set VSETVL by\n \t \"vsetvl zero, rs1/imm\". */\n@@ -1894,7 +1894,7 @@ legitimize_move (rtx dest, rtx *srcp)\n return true;\n }\n \n- if (riscv_v_ext_vls_mode_p (mode))\n+ if (riscv_vls_mode_p (mode))\n {\n if (GET_MODE_NUNITS (mode).to_constant () <= 31)\n \t{\n@@ -2002,7 +2002,7 @@ get_vlmul (machine_mode mode)\n /* For VLS modes, the vlmul should be dynamically\n calculated since we need to adjust VLMUL according\n to TARGET_MIN_VLEN. */\n- if (riscv_v_ext_vls_mode_p (mode))\n+ if (riscv_vls_mode_p (mode))\n {\n int size = GET_MODE_BITSIZE (mode).to_constant ();\n int inner_size = GET_MODE_BITSIZE (GET_MODE_INNER (mode));\n@@ -2063,7 +2063,7 @@ get_vlmul (machine_mode mode)\n rtx\n get_vlmax_rtx (machine_mode mode)\n {\n- gcc_assert (riscv_v_ext_vector_mode_p (mode));\n+ gcc_assert (riscv_vla_mode_p (mode));\n return gen_int_mode (GET_MODE_NUNITS (mode), Pmode);\n }\n \n@@ -2072,7 +2072,7 @@ unsigned int\n get_nf (machine_mode mode)\n {\n /* We don't allow non-tuple modes go through this function. */\n- gcc_assert (riscv_v_ext_tuple_mode_p (mode));\n+ gcc_assert (riscv_tuple_mode_p (mode));\n return mode_vtype_infos.nf[mode];\n }\n \n@@ -2083,7 +2083,7 @@ machine_mode\n get_subpart_mode (machine_mode mode)\n {\n /* We don't allow non-tuple modes go through this function. */\n- gcc_assert (riscv_v_ext_tuple_mode_p (mode));\n+ gcc_assert (riscv_tuple_mode_p (mode));\n return mode_vtype_infos.subpart_mode[mode];\n }\n \n@@ -2091,7 +2091,7 @@ get_subpart_mode (machine_mode mode)\n unsigned int\n get_ratio (machine_mode mode)\n {\n- if (riscv_v_ext_vls_mode_p (mode))\n+ if (riscv_vls_mode_p (mode))\n {\n unsigned int sew = get_sew (mode);\n vlmul_type vlmul = get_vlmul (mode);\n@@ -2168,11 +2168,12 @@ machine_mode\n get_mask_mode (machine_mode mode)\n {\n poly_int64 nunits = GET_MODE_NUNITS (mode);\n- if (riscv_v_ext_tuple_mode_p (mode))\n+ if (riscv_tuple_mode_p (mode))\n {\n unsigned int nf = get_nf (mode);\n nunits = exact_div (nunits, nf);\n }\n+\n return get_vector_mode (BImode, nunits).require ();\n }\n \n@@ -2213,11 +2214,12 @@ get_vector_mode (scalar_mode inner_mode, poly_uint64 nunits)\n else\n mclass = MODE_VECTOR_INT;\n machine_mode mode;\n+\n FOR_EACH_MODE_IN_CLASS (mode, mclass)\n if (inner_mode == GET_MODE_INNER (mode)\n \t&& known_eq (nunits, GET_MODE_NUNITS (mode))\n-\t&& (riscv_v_ext_vector_mode_p (mode)\n-\t || riscv_v_ext_vls_mode_p (mode)))\n+\t&& (riscv_vla_mode_p (mode)\n+\t || riscv_vls_mode_p (mode)))\n return mode;\n return opt_machine_mode ();\n }\n@@ -2234,7 +2236,7 @@ get_tuple_mode (machine_mode subpart_mode, unsigned int nf)\n FOR_EACH_MODE_IN_CLASS (mode, mclass)\n if (inner_mode == GET_MODE_INNER (mode)\n \t&& known_eq (nunits, GET_MODE_NUNITS (mode))\n-\t&& riscv_v_ext_tuple_mode_p (mode)\n+\t&& riscv_tuple_mode_p (mode)\n \t&& get_subpart_mode (mode) == subpart_mode)\n return mode;\n return opt_machine_mode ();\n@@ -3056,11 +3058,11 @@ can_find_related_mode_p (machine_mode vector_mode, scalar_mode element_mode,\n {\n if (!autovec_use_vlmax_p ())\n return false;\n- if (riscv_v_ext_vector_mode_p (vector_mode)\n+ if (riscv_vla_mode_p (vector_mode)\n && multiple_p (BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL,\n \t\t GET_MODE_SIZE (element_mode), nunits))\n return true;\n- if (riscv_v_ext_vls_mode_p (vector_mode)\n+ if (riscv_vls_mode_p (vector_mode)\n && multiple_p ((TARGET_MIN_VLEN * TARGET_MAX_LMUL) / BITS_PER_UNIT,\n \t\t GET_MODE_SIZE (element_mode), nunits))\n return true;\n@@ -5109,9 +5111,9 @@ expand_fold_extract_last (rtx *ops)\n bool\n cmp_lmul_le_one (machine_mode mode)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n return known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);\n- else if (riscv_v_ext_vls_mode_p (mode))\n+ else if (riscv_vls_mode_p (mode))\n return known_le (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN);\n return false;\n }\n@@ -5120,9 +5122,9 @@ cmp_lmul_le_one (machine_mode mode)\n bool\n cmp_lmul_gt_one (machine_mode mode)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n return known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);\n- else if (riscv_v_ext_vls_mode_p (mode))\n+ else if (riscv_vls_mode_p (mode))\n return known_gt (GET_MODE_BITSIZE (mode), TARGET_MIN_VLEN);\n return false;\n }\n@@ -5196,14 +5198,14 @@ cmp_lmul_gt_one (machine_mode mode)\n Then we can have the condition for VLS mode in fixed-vlmax, aka:\n PRECISION (VLSmode) < VLEN / (64 / PRECISION(VLS_inner_mode)). */\n bool\n-vls_mode_valid_p (machine_mode vls_mode, bool allow_up_to_lmul_8)\n+vls_mode_valid_p (machine_mode mode, bool allow_up_to_lmul_8)\n {\n if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)\n return false;\n \n if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)\n {\n- if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL)\n+ if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)\n \treturn true;\n if (allow_up_to_lmul_8)\n \treturn true;\n@@ -5216,16 +5218,16 @@ vls_mode_valid_p (machine_mode vls_mode, bool allow_up_to_lmul_8)\n \t with size = 128 bits, we will end up with multiple ICEs in\n \t middle-end generic codes. */\n return !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,\n-\t\t\t GET_MODE_PRECISION (vls_mode));\n+\t\t\t GET_MODE_PRECISION (mode));\n }\n \n if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)\n {\n- machine_mode inner_mode = GET_MODE_INNER (vls_mode);\n+ machine_mode inner_mode = GET_MODE_INNER (mode);\n int precision = GET_MODE_PRECISION (inner_mode).to_constant ();\n int min_vlmax_bitsize = TARGET_MIN_VLEN / (64 / precision);\n \n- return GET_MODE_PRECISION (vls_mode).to_constant () < min_vlmax_bitsize;\n+ return GET_MODE_PRECISION (mode).to_constant () < min_vlmax_bitsize;\n }\n \n return false;\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 15866d18342..b5867a0b448 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -1830,7 +1830,7 @@ public:\n tree rhs_tuple = gimple_call_arg (f.call, 0);\n /* LMUL > 1 non-tuple vector types are not structure,\n we can't use __val[index] to set the subpart. */\n- if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (TREE_TYPE (rhs_tuple))))\n+ if (!riscv_tuple_mode_p (TYPE_MODE (TREE_TYPE (rhs_tuple))))\n return NULL;\n tree index = gimple_call_arg (f.call, 1);\n tree rhs_vector = gimple_call_arg (f.call, 2);\n@@ -1861,7 +1861,7 @@ public:\n if (!e.target)\n return NULL_RTX;\n rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));\n- gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));\n+ gcc_assert (riscv_vla_mode_p (GET_MODE (dest)));\n rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));\n rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 2));\n poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (src));\n@@ -1884,7 +1884,7 @@ public:\n tree rhs_tuple = gimple_call_arg (f.call, 0);\n /* LMUL > 1 non-tuple vector types are not structure,\n we can't use __val[index] to get the subpart. */\n- if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (TREE_TYPE (rhs_tuple))))\n+ if (!riscv_tuple_mode_p (TYPE_MODE (TREE_TYPE (rhs_tuple))))\n return NULL;\n tree index = gimple_call_arg (f.call, 1);\n tree field = tuple_type_field (TREE_TYPE (rhs_tuple));\n@@ -1900,7 +1900,7 @@ public:\n if (!e.target)\n return NULL_RTX;\n rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));\n- gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));\n+ gcc_assert (riscv_vla_mode_p (GET_MODE (src)));\n rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));\n poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (e.target));\n rtx subreg\n@@ -1918,7 +1918,7 @@ public:\n tree lhs_type = TREE_TYPE (f.lhs);\n /* LMUL > 1 non-tuple vector types are not structure,\n we can't use __val[index] to set the subpart. */\n- if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (lhs_type)))\n+ if (!riscv_tuple_mode_p (TYPE_MODE (lhs_type)))\n return NULL;\n \n /* Replace the call with a clobber of the result (to prevent it from\n@@ -1949,7 +1949,7 @@ public:\n {\n if (!e.target)\n return NULL_RTX;\n- gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (e.target)));\n+ gcc_assert (riscv_vla_mode_p (GET_MODE (e.target)));\n unsigned int nargs = call_expr_nargs (e.exp);\n for (unsigned int i = 0; i < nargs; i++)\n {\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex f92e94b781d..c1392395697 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -3679,7 +3679,7 @@ rvv_switcher::rvv_switcher (bool pollute_flags)\n memcpy (m_old_have_regs_of_mode, have_regs_of_mode,\n \t sizeof (have_regs_of_mode));\n for (int i = 0; i < NUM_MACHINE_MODES; ++i)\n- if (riscv_v_ext_vector_mode_p ((machine_mode) i))\n+ if (riscv_vla_mode_p ((machine_mode) i))\n have_regs_of_mode[i] = true;\n \n /* Not necessary to adjust mode and register type if we don't pollute\n@@ -3770,7 +3770,7 @@ register_builtin_type (vector_type_index type, tree eltype, machine_mode mode)\n Ideally, we should report error message more friendly instead of\n reporting \"unknown\" type. Support more friendly error message in\n the future. */\n- if (!riscv_v_ext_vector_mode_p (mode))\n+ if (!riscv_vla_mode_p (mode))\n return;\n \n tree vectype = build_vector_type_for_mode (eltype, mode);\ndiff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc\nindex 27ced61e815..4b7e0888ae3 100644\n--- a/gcc/config/riscv/riscv-vector-costs.cc\n+++ b/gcc/config/riscv/riscv-vector-costs.cc\n@@ -545,7 +545,7 @@ max_number_of_live_regs (loop_vec_info loop_vinfo, const basic_block bb,\n {\n machine_mode mode = TYPE_MODE (TREE_TYPE (t));\n if (!lookup_vector_type_attribute (TREE_TYPE (t))\n-\t && !riscv_v_ext_vls_mode_p (mode))\n+\t && !riscv_vls_mode_p (mode))\n \tcontinue;\n \n gimple *def = SSA_NAME_DEF_STMT (t);\n@@ -624,7 +624,7 @@ compute_estimated_lmul (loop_vec_info loop_vinfo, machine_mode mode)\n {\n gcc_assert (GET_MODE_BITSIZE (mode).is_constant ());\n int regno_alignment = riscv_get_v_regno_alignment (loop_vinfo->vector_mode);\n- if (riscv_v_ext_vls_mode_p (loop_vinfo->vector_mode))\n+ if (riscv_vls_mode_p (loop_vinfo->vector_mode))\n return regno_alignment;\n else\n {\n@@ -895,7 +895,7 @@ costs::costs (vec_info *vinfo, bool costing_for_scalar)\n {\n if (costing_for_scalar)\n m_cost_type = SCALAR_COST;\n- else if (riscv_v_ext_vector_mode_p (vinfo->vector_mode))\n+ else if (riscv_vla_mode_p (vinfo->vector_mode))\n m_cost_type = VLA_VECTOR_COST;\n else\n m_cost_type = VLS_VECTOR_COST;\n@@ -1043,7 +1043,7 @@ costs::better_main_loop_than_p (const vector_costs *uncast_other) const\n \t\t\t \" it has unexpected spills\\n\");\n \t return true;\n \t}\n- else if (riscv_v_ext_vector_mode_p (other_loop_vinfo->vector_mode))\n+ else if (riscv_vla_mode_p (other_loop_vinfo->vector_mode))\n \t{\n \t if (LOOP_VINFO_NITERS_KNOWN_P (other_loop_vinfo))\n \t {\n@@ -1137,43 +1137,43 @@ costs::adjust_stmt_cost (enum vect_cost_for_stmt kind, loop_vec_info loop,\n \t\t switch (group_size)\n \t\t {\n \t\t case 2:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_2;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_2;\n \t\t break;\n \t\t case 3:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_3;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_3;\n \t\t break;\n \t\t case 4:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_4;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_4;\n \t\t break;\n \t\t case 5:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_5;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_5;\n \t\t break;\n \t\t case 6:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_6;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_6;\n \t\t break;\n \t\t case 7:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_7;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_7;\n \t\t break;\n \t\t case 8:\n-\t\t if (riscv_v_ext_vector_mode_p (loop->vector_mode))\n+\t\t if (riscv_vla_mode_p (loop->vector_mode))\n \t\t\tstmt_cost += costs->vla->segment_permute_8;\n \t\t else\n \t\t\tstmt_cost += costs->vls->segment_permute_8;\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 96519c96a2b..4fe2717a3f6 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -2241,7 +2241,7 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode,\n whereas 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */\n \n bool\n-riscv_v_ext_vector_mode_p (machine_mode mode)\n+riscv_vla_mode_p (machine_mode mode)\n {\n #define ENTRY(MODE, REQUIREMENT, ...) \\\n case MODE##mode: \\\n@@ -2259,7 +2259,7 @@ riscv_v_ext_vector_mode_p (machine_mode mode)\n /* Return true if mode is the RVV enabled tuple mode. */\n \n bool\n-riscv_v_ext_tuple_mode_p (machine_mode mode)\n+riscv_tuple_mode_p (machine_mode mode)\n {\n #define TUPLE_ENTRY(MODE, REQUIREMENT, ...) \\\n case MODE##mode: \\\n@@ -2277,7 +2277,7 @@ riscv_v_ext_tuple_mode_p (machine_mode mode)\n /* Return true if mode is the RVV enabled vls mode. */\n \n bool\n-riscv_v_ext_vls_mode_p (machine_mode mode)\n+riscv_vls_mode_p (machine_mode mode)\n {\n #define VLS_ENTRY(MODE, REQUIREMENT) \\\n case MODE##mode: \\\n@@ -2298,10 +2298,10 @@ riscv_v_ext_vls_mode_p (machine_mode mode)\n 3. RVV vls mode. */\n \n static bool\n-riscv_v_ext_mode_p (machine_mode mode)\n+riscv_vector_mode_p (machine_mode mode)\n {\n- return riscv_v_ext_vector_mode_p (mode) || riscv_v_ext_tuple_mode_p (mode)\n-\t || riscv_v_ext_vls_mode_p (mode);\n+ return riscv_vla_mode_p (mode) || riscv_tuple_mode_p (mode)\n+\t || riscv_vls_mode_p (mode);\n }\n \n static unsigned\n@@ -2346,7 +2346,7 @@ poly_int64\n riscv_v_adjust_nunits (machine_mode mode, int scale)\n {\n gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL);\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n {\n if (TARGET_MIN_VLEN == 32)\n \tscale = scale / 2;\n@@ -2361,7 +2361,7 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)\n poly_int64\n riscv_v_adjust_nunits (machine_mode mode, bool fractional_p, int lmul, int nf)\n {\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n {\n scalar_mode smode = GET_MODE_INNER (mode);\n int size = GET_MODE_SIZE (smode);\n@@ -2381,7 +2381,7 @@ riscv_v_adjust_nunits (machine_mode mode, bool fractional_p, int lmul, int nf)\n poly_int64\n riscv_v_adjust_bytesize (machine_mode mode, int scale)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n {\n if (TARGET_XTHEADVECTOR)\n \treturn BYTES_PER_RISCV_VECTOR;\n@@ -2430,7 +2430,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x,\n \n case PLUS:\n /* RVV load/store disallow any offset. */\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n \treturn false;\n \n info->type = ADDRESS_REG;\n@@ -2441,7 +2441,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x,\n \n case LO_SUM:\n /* RVV load/store disallow LO_SUM. */\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n \treturn false;\n \n info->type = ADDRESS_LO_SUM;\n@@ -2476,7 +2476,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x,\n \t | vs1r.v v24,0(a0)\t\t\t\t\t |\n \t +----------------------------------------------------------+\n \t This behavior will benefit the underlying RVV auto vectorization. */\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n \treturn x == const0_rtx;\n \n /* Small-integer addresses don't occur very often, but they\n@@ -2497,7 +2497,7 @@ riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p,\n {\n /* Disallow RVV modes base address.\n E.g. (mem:SI (subreg:DI (reg:V1DI 155) 0). */\n- if (SUBREG_P (x) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (x))))\n+ if (SUBREG_P (x) && riscv_vector_mode_p (GET_MODE (SUBREG_REG (x))))\n return false;\n struct riscv_address_info addr;\n \n@@ -2570,7 +2570,7 @@ riscv_address_insns (rtx x, machine_mode mode, bool might_split_p)\n \n /* BLKmode is used for single unaligned loads and stores and should\n not count as a multiword mode. */\n- if (!riscv_v_ext_vector_mode_p (mode) && mode != BLKmode && might_split_p)\n+ if (!riscv_vla_mode_p (mode) && mode != BLKmode && might_split_p)\n n += (GET_MODE_SIZE (mode).to_constant () + UNITS_PER_WORD - 1) / UNITS_PER_WORD;\n \n if (addr.type == ADDRESS_LO_SUM)\n@@ -2628,7 +2628,7 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)\n \t out range of [-16, 15].\n \t - 3. const series vector.\n \t ...etc. */\n-\tif (riscv_v_ext_mode_p (GET_MODE (x)))\n+\tif (riscv_vector_mode_p (GET_MODE (x)))\n \t {\n \t rtx elt;\n \t if (const_vec_duplicate_p (x, &elt))\n@@ -3786,7 +3786,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)\n (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))\n Since RVV mode and scalar mode are in different REG_CLASS,\n we need to explicitly move data from V_REGS to GR_REGS by scalar move. */\n- if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src))))\n+ if (SUBREG_P (src) && riscv_vector_mode_p (GET_MODE (SUBREG_REG (src))))\n {\n machine_mode vmode = GET_MODE (SUBREG_REG (src));\n unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();\n@@ -4053,7 +4053,7 @@ riscv_immediate_operand_p (int code, HOST_WIDE_INT x)\n static int\n riscv_binary_cost (rtx x, int single_insns, int double_insns)\n {\n- if (!riscv_v_ext_mode_p (GET_MODE (x))\n+ if (!riscv_vector_mode_p (GET_MODE (x))\n && riscv_2x_xlen_mode_p (GET_MODE (x)))\n return COSTS_N_INSNS (double_insns);\n return COSTS_N_INSNS (single_insns);\n@@ -4107,7 +4107,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN\n {\n /* TODO: We set RVV instruction cost as 1 by default.\n Cost Model need to be well analyzed and supported in the future. */\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n {\n int gr2vr_cost = get_gr2vr_cost ();\n int fr2vr_cost = get_fr2vr_cost ();\n@@ -6404,7 +6404,7 @@ static rtx\n riscv_pass_vls_aggregate_in_gpr (struct riscv_arg_info *info, machine_mode mode,\n \t\t\t\t unsigned gpr_base)\n {\n- gcc_assert (riscv_v_ext_vls_mode_p (mode));\n+ gcc_assert (riscv_vls_mode_p (mode));\n \n unsigned count = 0;\n unsigned regnum = 0;\n@@ -6475,7 +6475,7 @@ static rtx\n riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n \t\t machine_mode mode, bool return_p, bool vls_p = false)\n {\n- gcc_assert (riscv_v_ext_mode_p (mode));\n+ gcc_assert (riscv_vector_mode_p (mode));\n \n info->mr_offset = cum->num_mrs;\n if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)\n@@ -6502,7 +6502,7 @@ riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n register to pass. Just call TARGET_HARD_REGNO_NREGS for the number\n information. */\n int nregs = riscv_hard_regno_nregs (V_ARG_FIRST, mode);\n- int LMUL = riscv_v_ext_tuple_mode_p (mode)\n+ int LMUL = riscv_tuple_mode_p (mode)\n \t ? nregs / riscv_vector::get_nf (mode)\n \t : nregs;\n int arg_reg_start = V_ARG_FIRST - V_REG_FIRST;\n@@ -6672,7 +6672,7 @@ static rtx\n riscv_pass_vls_in_vr (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n \t\t machine_mode mode, bool return_p)\n {\n- gcc_assert (riscv_v_ext_vls_mode_p (mode));\n+ gcc_assert (riscv_vls_mode_p (mode));\n \n unsigned int abi_vlen = riscv_get_cc_abi_vlen (cum->variant_cc);\n unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();\n@@ -6789,7 +6789,7 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n info->fpr_offset = cum->num_fprs;\n \n /* Passed by reference when the scalable vector argument is anonymous. */\n- if (riscv_v_ext_mode_p (mode) && !named)\n+ if (riscv_vector_mode_p (mode) && !named)\n return NULL_RTX;\n \n if (named)\n@@ -6855,12 +6855,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n \t}\n \n /* For scalable vector argument. */\n- if (riscv_vector_type_p (type) && riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_type_p (type) && riscv_vector_mode_p (mode))\n \treturn riscv_get_vector_arg (info, cum, mode, return_p);\n \n if (riscv_vls_cc_p (cum->variant_cc))\n \t{\n-\t if (riscv_v_ext_vls_mode_p (mode))\n+\t if (riscv_vls_mode_p (mode))\n \t return riscv_pass_vls_in_vr (info, cum, mode, return_p);\n \n \t rtx ret = riscv_pass_aggregate_in_vr (info, cum, type, return_p);\n@@ -6869,7 +6869,7 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,\n \t}\n \n /* For vls mode aggregated in gpr (for non-VLS-CC). */\n- if (riscv_v_ext_vls_mode_p (mode))\n+ if (riscv_vls_mode_p (mode))\n \treturn riscv_pass_vls_aggregate_in_gpr (info, mode, gpr_base);\n }\n \n@@ -7018,7 +7018,7 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)\n \treturn false;\n \n /* Don't pass by reference if we can use general register(s) for vls. */\n- if (info.num_gprs && riscv_v_ext_vls_mode_p (arg.mode))\n+ if (info.num_gprs && riscv_vls_mode_p (arg.mode))\n \treturn false;\n \n /* Don't pass by reference if we can use vector register groups. */\n@@ -7029,7 +7029,7 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)\n /* Passed by reference when:\n 1. The scalable vector argument is anonymous.\n 2. Args cannot be passed through vector registers. */\n- if (riscv_v_ext_mode_p (arg.mode))\n+ if (riscv_vector_mode_p (arg.mode))\n return true;\n \n /* Pass by reference if the data do not fit in two integer registers. */\n@@ -7169,7 +7169,7 @@ riscv_vector_required_min_vlen (const_tree type)\n {\n machine_mode mode = TYPE_MODE (type);\n \n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n return TARGET_MIN_VLEN;\n \n int element_bitsize = riscv_vector_element_bitsize (type);\n@@ -7771,7 +7771,7 @@ riscv_get_v_regno_alignment (machine_mode mode)\n but for mask vector register, register numbers can be any number. */\n int lmul = 1;\n machine_mode rvv_mode = mode;\n- if (riscv_v_ext_vls_mode_p (rvv_mode))\n+ if (riscv_vls_mode_p (rvv_mode))\n {\n int size = GET_MODE_BITSIZE (rvv_mode).to_constant ();\n if (size < TARGET_MIN_VLEN)\n@@ -7779,7 +7779,7 @@ riscv_get_v_regno_alignment (machine_mode mode)\n else\n \treturn size / TARGET_MIN_VLEN;\n }\n- if (riscv_v_ext_tuple_mode_p (rvv_mode))\n+ if (riscv_tuple_mode_p (rvv_mode))\n rvv_mode = riscv_vector::get_subpart_mode (rvv_mode);\n poly_int64 size = GET_MODE_SIZE (rvv_mode);\n if (known_gt (size, UNITS_PER_V_REG))\n@@ -7841,7 +7841,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)\n \t 1. If the operand is VECTOR REG, we print 'v'(vnsrl.wv).\n \t 2. If the operand is CONST_INT/CONST_VECTOR, we print 'i'(vnsrl.wi).\n \t 3. If the operand is SCALAR REG, we print 'x'(vnsrl.wx). */\n-\tif (riscv_v_ext_mode_p (mode))\n+\tif (riscv_vector_mode_p (mode))\n \t {\n \t if (REG_P (op))\n \t asm_fprintf (file, \"v\");\n@@ -7890,7 +7890,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)\n \tbreak;\n }\n case 'm': {\n-\tif (riscv_v_ext_mode_p (mode))\n+\tif (riscv_vector_mode_p (mode))\n \t {\n \t /* Calculate lmul according to mode and print the value. */\n \t int lmul = riscv_get_v_regno_alignment (mode);\n@@ -10594,7 +10594,7 @@ riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,\n {\n bool class1_is_fpr = class1 == FP_REGS || class1 == RVC_FP_REGS;\n bool class2_is_fpr = class2 == FP_REGS || class2 == RVC_FP_REGS;\n- return (!riscv_v_ext_mode_p (mode)\n+ return (!riscv_vector_mode_p (mode)\n \t && GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD\n \t && (class1_is_fpr != class2_is_fpr)\n \t && !TARGET_XTHEADFMV\n@@ -10638,7 +10638,7 @@ riscv_register_move_cost (machine_mode mode,\n static unsigned int\n riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)\n {\n- if (riscv_v_ext_vector_mode_p (mode))\n+ if (riscv_vla_mode_p (mode))\n {\n /* Handle fractional LMUL, it only occupy part of vector register but\n \t still need one vector register to hold. */\n@@ -10649,7 +10649,7 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)\n }\n \n /* For tuple modes, the number of register = NF * LMUL. */\n- if (riscv_v_ext_tuple_mode_p (mode))\n+ if (riscv_tuple_mode_p (mode))\n {\n unsigned int nf = riscv_vector::get_nf (mode);\n machine_mode subpart_mode = riscv_vector::get_subpart_mode (mode);\n@@ -10665,7 +10665,7 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)\n }\n \n /* For VLS modes, we allocate registers according to TARGET_MIN_VLEN. */\n- if (riscv_v_ext_vls_mode_p (mode))\n+ if (riscv_vls_mode_p (mode))\n {\n int size = GET_MODE_BITSIZE (mode).to_constant ();\n if (size < TARGET_MIN_VLEN)\n@@ -10700,7 +10700,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)\n \n if (GP_REG_P (regno))\n {\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n \treturn false;\n \n /* Zilsd require load/store with even-odd reg pair. */\n@@ -10712,7 +10712,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)\n }\n else if (FP_REG_P (regno))\n {\n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n \treturn false;\n \n if (!FP_REG_P (regno + nregs - 1))\n@@ -10731,7 +10731,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)\n }\n else if (V_REG_P (regno))\n {\n- if (!riscv_v_ext_mode_p (mode))\n+ if (!riscv_vector_mode_p (mode))\n \treturn false;\n \n if (!V_REG_P (regno + nregs - 1))\n@@ -10774,7 +10774,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n /* We don't allow different REG_CLASS modes tieable since it\n will cause ICE in register allocation (RA).\n E.g. V2SI and DI are not tieable. */\n- if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2))\n+ if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n return false;\n return (mode1 == mode2\n \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n@@ -12987,7 +12987,7 @@ riscv_can_change_mode_class (machine_mode from, machine_mode to,\n we cannot, statically, determine which part of it to extract.\n Therefore prevent that. */\n if (reg_classes_intersect_p (V_REGS, rclass)\n- && riscv_v_ext_vls_mode_p (from)\n+ && riscv_vls_mode_p (from)\n && !ordered_p (BITS_PER_RISCV_VECTOR, GET_MODE_PRECISION (from)))\n return false;\n \n@@ -13342,7 +13342,7 @@ static bool\n riscv_vector_mode_supported_p (machine_mode mode)\n {\n if (TARGET_VECTOR)\n- return riscv_v_ext_mode_p (mode);\n+ return riscv_vector_mode_p (mode);\n \n return false;\n }\n@@ -13385,16 +13385,16 @@ riscv_regmode_natural_size (machine_mode mode)\n /* ??? For now, only do this for variable-width RVV registers.\n Doing it for constant-sized registers breaks lower-subreg.c. */\n \n- if (riscv_v_ext_mode_p (mode))\n+ if (riscv_vector_mode_p (mode))\n {\n poly_uint64 size = GET_MODE_SIZE (mode);\n- if (riscv_v_ext_tuple_mode_p (mode))\n+ if (riscv_tuple_mode_p (mode))\n \t{\n \t size = GET_MODE_SIZE (riscv_vector::get_subpart_mode (mode));\n \t if (known_lt (size, BYTES_PER_RISCV_VECTOR))\n \t return size;\n \t}\n- else if (riscv_v_ext_vector_mode_p (mode))\n+ else if (riscv_vla_mode_p (mode))\n \t{\n \t /* RVV mask modes always consume a single register. */\n \t if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)\n@@ -13402,7 +13402,7 @@ riscv_regmode_natural_size (machine_mode mode)\n \t}\n if (!size.is_constant ())\n \treturn BYTES_PER_RISCV_VECTOR;\n- else if (!riscv_v_ext_vls_mode_p (mode))\n+ else if (!riscv_vls_mode_p (mode))\n \t/* For -march=rv64gc_zve32f, the natural vector register size\n \t is 32bits which is smaller than scalar register size, so we\n \t return minimum size between vector register size and scalar\n@@ -13480,7 +13480,7 @@ riscv_support_vector_misalignment (machine_mode mode, int misalignment,\n static opt_machine_mode\n riscv_get_mask_mode (machine_mode mode)\n {\n- if (TARGET_VECTOR && riscv_v_ext_mode_p (mode))\n+ if (TARGET_VECTOR && riscv_vector_mode_p (mode))\n return riscv_vector::get_mask_mode (mode);\n \n return default_get_mask_mode (mode);\n@@ -13677,7 +13677,7 @@ riscv_preferred_simd_mode (scalar_mode mode)\n static poly_uint64\n riscv_vectorize_preferred_vector_alignment (const_tree type)\n {\n- if (riscv_v_ext_mode_p (TYPE_MODE (type)))\n+ if (riscv_vector_mode_p (TYPE_MODE (type)))\n return TYPE_ALIGN (TREE_TYPE (type));\n return TYPE_ALIGN (type);\n }\n@@ -14052,7 +14052,7 @@ riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,\n \t\t\t\trtx target, rtx op0, rtx op1,\n \t\t\t\tconst vec_perm_indices &sel)\n {\n- if (TARGET_VECTOR && riscv_v_ext_mode_p (vmode))\n+ if (TARGET_VECTOR && riscv_vector_mode_p (vmode))\n return riscv_vector::expand_vec_perm_const (vmode, op_mode, target, op0,\n \t\t\t\t\t\top1, sel);\n \n@@ -14071,7 +14071,7 @@ get_common_costs (const cpu_vector_cost *costs, tree vectype)\n {\n gcc_assert (costs);\n \n- if (vectype && riscv_v_ext_vls_mode_p (TYPE_MODE (vectype)))\n+ if (vectype && riscv_vls_mode_p (TYPE_MODE (vectype)))\n return costs->vls;\n return costs->vla;\n }\n@@ -14211,7 +14211,7 @@ static tree\n riscv_preferred_else_value (unsigned ifn, tree vectype, unsigned int nops,\n \t\t\t tree *ops)\n {\n- if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))\n+ if (riscv_vector_mode_p (TYPE_MODE (vectype)))\n {\n tree tmp_var = create_tmp_var (vectype);\n TREE_NO_WARNING (tmp_var) = 1;\n", "prefixes": [ "v3", "2/4" ] }