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put:
Update a patch.

GET /api/1.0/patches/2175295/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2175295,
    "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175295/?format=api",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20251217151609.3162665-18-den@valinux.co.jp>",
    "date": "2025-12-17T15:15:51",
    "name": "[RFC,v3,17/35] dmaengine: dw-edma: Add helper func to retrieve register base and size",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "9bb09941d5013ece7634fa90e664796754b1ff73",
    "submitter": {
        "id": 91573,
        "url": "http://patchwork.ozlabs.org/api/1.0/people/91573/?format=api",
        "name": "Koichiro Den",
        "email": "den@valinux.co.jp"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217151609.3162665-18-den@valinux.co.jp/mbox/",
    "series": [
        {
            "id": 485709,
            "url": "http://patchwork.ozlabs.org/api/1.0/series/485709/?format=api",
            "date": "2025-12-17T15:15:53",
            "name": "NTB transport backed by endpoint DW eDMA",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/485709/mbox/"
        }
    ],
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2175295/checks/",
    "tags": {},
    "headers": {
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        "From": "Koichiro Den <den@valinux.co.jp>",
        "To": "Frank.Li@nxp.com,\n\tdave.jiang@intel.com,\n\tntb@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdmaengine@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tnetdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org",
        "Cc": "mani@kernel.org,\n\tkwilczynski@kernel.org,\n\tkishon@kernel.org,\n\tbhelgaas@google.com,\n\tcorbet@lwn.net,\n\tgeert+renesas@glider.be,\n\tmagnus.damm@gmail.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tvkoul@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tjdmason@kudzu.us,\n\tallenbh@gmail.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\tBasavaraj.Natikar@amd.com,\n\tShyam-sundar.S-k@amd.com,\n\tkurt.schwemmer@microsemi.com,\n\tlogang@deltatee.com,\n\tjingoohan1@gmail.com,\n\tlpieralisi@kernel.org,\n\tutkarsh02t@gmail.com,\n\tjbrunet@baylibre.com,\n\tdlemoal@kernel.org,\n\tarnd@arndb.de,\n\telfring@users.sourceforge.net,\n\tden@valinux.co.jp",
        "Subject": "[RFC PATCH v3 17/35] dmaengine: dw-edma: Add helper func to retrieve\n register base and size",
        "Date": "Thu, 18 Dec 2025 00:15:51 +0900",
        "Message-ID": "<20251217151609.3162665-18-den@valinux.co.jp>",
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    },
    "content": "Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA\nregister block through a memory window.\n\nAdd a helper function that returns the physical base and size for a\ngiven DesignWare EP controller.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\n .../pci/controller/dwc/pcie-designware-ep.c   |  1 +\n drivers/pci/controller/dwc/pcie-designware.c  | 25 +++++++++++++++++++\n include/linux/dma/edma.h                      | 24 ++++++++++++++++++\n 3 files changed, 50 insertions(+)",
    "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 9480aebaa32a..46d18e7945db 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -12,6 +12,7 @@\n #include <linux/platform_device.h>\n \n #include \"pcie-designware.h\"\n+#include <linux/dma/edma.h>\n #include <linux/pci-epc.h>\n #include <linux/pci-epf.h>\n \ndiff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 75fc8b767fcc..1de88df7b1af 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)\n \t\t\tpci->edma.reg_base = devm_ioremap_resource(pci->dev, res);\n \t\t\tif (IS_ERR(pci->edma.reg_base))\n \t\t\t\treturn PTR_ERR(pci->edma.reg_base);\n+\t\t\tpci->edma.reg_phys = res->start;\n+\t\t\tpci->edma.reg_size = resource_size(res);\n \t\t} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {\n \t\t\tpci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma.reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma.reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;\n \t\t}\n \t}\n \n@@ -1204,3 +1208,24 @@ resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,\n \n \treturn cpu_phys_addr - reg_addr;\n }\n+\n+int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t *sz)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci;\n+\n+\tif (!ep)\n+\t\treturn -ENODEV;\n+\n+\tpci = to_dw_pcie_from_ep(ep);\n+\tif (!pci->edma.reg_base || !pci->edma.reg_phys)\n+\t\treturn -ENODEV;\n+\n+\tif (phys)\n+\t\t*phys = pci->edma.reg_phys;\n+\tif (sz)\n+\t\t*sz = pci->edma.reg_size;\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(dw_edma_get_reg_window);\ndiff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h\nindex 3080747689f6..11d6eeb19fff 100644\n--- a/include/linux/dma/edma.h\n+++ b/include/linux/dma/edma.h\n@@ -11,6 +11,7 @@\n \n #include <linux/device.h>\n #include <linux/dmaengine.h>\n+#include <linux/pci-epc.h>\n \n #define EDMA_MAX_WR_CH                                  8\n #define EDMA_MAX_RD_CH                                  8\n@@ -60,6 +61,27 @@ enum dw_edma_chip_flags {\n \tDW_EDMA_CHIP_LOCAL\t= BIT(0),\n };\n \n+#if IS_REACHABLE(CONFIG_PCIE_DW)\n+/**\n+ * dw_edma_get_reg_window - get eDMA register base and size\n+ *\n+ * @epc: the EPC device with which the eDMA instance is integrated\n+ * @phys: the output parameter that returns the register base address\n+ * @sz: the output parameter that returns the register space size\n+ *\n+ * Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA\n+ * register block through a memory window. This helper returns the physical\n+ * base and size for a given DesignWare EP controller.\n+ */\n+int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t *sz);\n+#else\n+static inline int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,\n+\t\t\t\t\t size_t *sz)\n+{\n+\treturn -ENODEV;\n+}\n+#endif /* CONFIG_PCIE_DW */\n+\n /**\n  * struct dw_edma_chip - representation of DesignWare eDMA controller hardware\n  * @dev:\t\t struct device of the eDMA controller\n@@ -85,6 +107,8 @@ struct dw_edma_chip {\n \tu32\t\t\tflags;\n \n \tvoid __iomem\t\t*reg_base;\n+\tphys_addr_t\t\treg_phys;\n+\tsize_t\t\t\treg_size;\n \n \tu16\t\t\tll_wr_cnt;\n \tu16\t\t\tll_rd_cnt;\n",
    "prefixes": [
        "RFC",
        "v3",
        "17/35"
    ]
}