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GET /api/1.0/patches/2175277/?format=api
{ "id": 2175277, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175277/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217151609.3162665-19-den@valinux.co.jp>", "date": "2025-12-17T15:15:52", "name": "[RFC,v3,18/35] dmaengine: dw-edma: Add per-channel interrupt routing mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6eba18645352b7fbcf577e60867706d1a4aff108", "submitter": { "id": 91573, "url": "http://patchwork.ozlabs.org/api/1.0/people/91573/?format=api", "name": "Koichiro Den", "email": "den@valinux.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217151609.3162665-19-den@valinux.co.jp/mbox/", "series": [ { "id": 485709, "url": "http://patchwork.ozlabs.org/api/1.0/series/485709/?format=api", "date": "2025-12-17T15:15:53", "name": "NTB transport backed by endpoint DW eDMA", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485709/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175277/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43226-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=LxOESZ29;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n 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bh=6YYcrDuPtoMFX/JbuSd1wp5KoLwbFTSYKMRD/fEs81Y=;\n b=LxOESZ29NKdX9KORMCmsarUSnN6JiXE/xhvjf3j4qz3broUxgF5gmOAr3ZFWXKPi6r9BPJBJkdt4QR6M3ZTo+8b9BtvlLvocPa/Jq/vNfB/dAGoI3lGbJn1vnx7rae2qh4J+JVW434FbASnIcVwQi3jh/CytyYIZaL+5Z/snjC0=", "From": "Koichiro Den <den@valinux.co.jp>", "To": "Frank.Li@nxp.com,\n\tdave.jiang@intel.com,\n\tntb@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdmaengine@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tnetdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Cc": "mani@kernel.org,\n\tkwilczynski@kernel.org,\n\tkishon@kernel.org,\n\tbhelgaas@google.com,\n\tcorbet@lwn.net,\n\tgeert+renesas@glider.be,\n\tmagnus.damm@gmail.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tvkoul@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tjdmason@kudzu.us,\n\tallenbh@gmail.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\tBasavaraj.Natikar@amd.com,\n\tShyam-sundar.S-k@amd.com,\n\tkurt.schwemmer@microsemi.com,\n\tlogang@deltatee.com,\n\tjingoohan1@gmail.com,\n\tlpieralisi@kernel.org,\n\tutkarsh02t@gmail.com,\n\tjbrunet@baylibre.com,\n\tdlemoal@kernel.org,\n\tarnd@arndb.de,\n\telfring@users.sourceforge.net,\n\tden@valinux.co.jp", "Subject": "[RFC PATCH v3 18/35] dmaengine: dw-edma: Add per-channel interrupt\n routing mode", "Date": "Thu, 18 Dec 2025 00:15:52 +0900", "Message-ID": "<20251217151609.3162665-19-den@valinux.co.jp>", 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"X-OriginatorOrg": "valinux.co.jp", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bf9b95bd-280f-484c-3c47-08de3d7f4119", "X-MS-Exchange-CrossTenant-AuthSource": "TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Dec 2025 15:16:29.6291\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "7a57bee8-f73d-4c5f-a4f7-d72c91c8c111", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n g1tGRkTKsicqlTOeeAZgtzHZgLW21KhBOQtn4Tu/WMXD4iPRL9BTNnPf5K4YuHr5v6bR2xlcq4QhQ7CqKsX3Ug==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "TYCP286MB2863" }, "content": "DesignWare eDMA linked-list mode supports both local and remote\ncompletion interrupts (LIE/RIE). For remote eDMA users, we need to\ndecide per-channel whether completion should be handled locally,\nremotely, or both.\n\nIntroduce a per-channel interrupt routing mode and export a small API to\nconfigure/query it. Update v0 programming so that RIE and local\ndone/abort interrupt masking follow the selected mode. The default mode\nkeeps the original behavior, so unless the new APIs are explicitly used,\nno functional changes.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\n drivers/dma/dw-edma/dw-edma-core.c | 49 +++++++++++++++++++++++++++\n drivers/dma/dw-edma/dw-edma-core.h | 2 ++\n drivers/dma/dw-edma/dw-edma-v0-core.c | 26 +++++++++-----\n include/linux/dma/edma.h | 46 +++++++++++++++++++++++++\n 4 files changed, 115 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c\nindex 1b935da65d05..0bceca2d56c5 100644\n--- a/drivers/dma/dw-edma/dw-edma-core.c\n+++ b/drivers/dma/dw-edma/dw-edma-core.c\n@@ -765,6 +765,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)\n \t\tchan->configured = false;\n \t\tchan->request = EDMA_REQ_NONE;\n \t\tchan->status = EDMA_ST_IDLE;\n+\t\tchan->irq_mode = DW_EDMA_CH_IRQ_DEFAULT;\n \n \t\tif (chan->dir == EDMA_DIR_WRITE)\n \t\t\tchan->ll_max = (chip->ll_region_wr[chan->id].sz / EDMA_LL_SZ);\n@@ -1059,6 +1060,54 @@ int dw_edma_remove(struct dw_edma_chip *chip)\n }\n EXPORT_SYMBOL_GPL(dw_edma_remove);\n \n+int dw_edma_chan_irq_config(struct dma_chan *dchan,\n+\t\t\t enum dw_edma_ch_irq_mode mode)\n+{\n+\tstruct dw_edma_chan *chan;\n+\n+\t/* Only LOCAL/REMOTE bits are valid. Zero keeps legacy behaviour. */\n+\tif (mode & ~(DW_EDMA_CH_IRQ_LOCAL | DW_EDMA_CH_IRQ_REMOTE))\n+\t\treturn -EINVAL;\n+\n+\tif (!dchan || !dchan->device ||\n+\t dchan->device->device_prep_slave_sg_config != dw_edma_device_prep_slave_sg_config)\n+\t\treturn -ENODEV;\n+\n+\tchan = dchan2dw_edma_chan(dchan);\n+\tif (!chan)\n+\t\treturn -ENODEV;\n+\n+\tchan->irq_mode = mode;\n+\n+\tdev_vdbg(chan->dw->chip->dev, \"Channel: %s[%u] set irq_mode=%u\\n\",\n+\t\t str_write_read(chan->dir == EDMA_DIR_WRITE),\n+\t\t chan->id, mode);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(dw_edma_chan_irq_config);\n+\n+bool dw_edma_chan_ignore_irq(struct dma_chan *dchan)\n+{\n+\tstruct dw_edma_chan *chan;\n+\tstruct dw_edma *dw;\n+\n+\tif (!dchan || !dchan->device ||\n+\t dchan->device->device_prep_slave_sg_config != dw_edma_device_prep_slave_sg_config)\n+\t\treturn false;\n+\n+\tchan = dchan2dw_edma_chan(dchan);\n+\tif (!chan)\n+\t\treturn false;\n+\n+\tdw = chan->dw;\n+\tif (dw->chip->flags & DW_EDMA_CHIP_LOCAL)\n+\t\treturn chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE;\n+\telse\n+\t\treturn chan->irq_mode == DW_EDMA_CH_IRQ_LOCAL;\n+}\n+EXPORT_SYMBOL_GPL(dw_edma_chan_ignore_irq);\n+\n MODULE_LICENSE(\"GPL v2\");\n MODULE_DESCRIPTION(\"Synopsys DesignWare eDMA controller core driver\");\n MODULE_AUTHOR(\"Gustavo Pimentel <gustavo.pimentel@synopsys.com>\");\ndiff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h\nindex 71894b9e0b15..8458d676551a 100644\n--- a/drivers/dma/dw-edma/dw-edma-core.h\n+++ b/drivers/dma/dw-edma/dw-edma-core.h\n@@ -81,6 +81,8 @@ struct dw_edma_chan {\n \n \tstruct msi_msg\t\t\tmsi;\n \n+\tenum dw_edma_ch_irq_mode\tirq_mode;\n+\n \tenum dw_edma_request\t\trequest;\n \tenum dw_edma_status\t\tstatus;\n \tu8\t\t\t\tconfigured;\ndiff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c\nindex b75fdaffad9a..42a254eb9379 100644\n--- a/drivers/dma/dw-edma/dw-edma-v0-core.c\n+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c\n@@ -256,8 +256,10 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,\n \tfor_each_set_bit(pos, &val, total) {\n \t\tchan = &dw->chan[pos + off];\n \n-\t\tdw_edma_v0_core_clear_done_int(chan);\n-\t\tdone(chan);\n+\t\tif (!dw_edma_chan_ignore_irq(&chan->vc.chan)) {\n+\t\t\tdw_edma_v0_core_clear_done_int(chan);\n+\t\t\tdone(chan);\n+\t\t}\n \n \t\tret = IRQ_HANDLED;\n \t}\n@@ -267,8 +269,10 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,\n \tfor_each_set_bit(pos, &val, total) {\n \t\tchan = &dw->chan[pos + off];\n \n-\t\tdw_edma_v0_core_clear_abort_int(chan);\n-\t\tabort(chan);\n+\t\tif (!dw_edma_chan_ignore_irq(&chan->vc.chan)) {\n+\t\t\tdw_edma_v0_core_clear_abort_int(chan);\n+\t\t\tabort(chan);\n+\t\t}\n \n \t\tret = IRQ_HANDLED;\n \t}\n@@ -331,7 +335,8 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)\n \t\tj--;\n \t\tif (!j) {\n \t\t\tcontrol |= DW_EDMA_V0_LIE;\n-\t\t\tif (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))\n+\t\t\tif (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) &&\n+\t\t\t chan->irq_mode != DW_EDMA_CH_IRQ_LOCAL)\n \t\t\t\tcontrol |= DW_EDMA_V0_RIE;\n \t\t}\n \n@@ -407,10 +412,15 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n \t\t\t\tbreak;\n \t\t\t}\n \t\t}\n-\t\t/* Interrupt unmask - done, abort */\n+\t\t/* Interrupt mask/unmask - done, abort */\n \t\ttmp = GET_RW_32(dw, chan->dir, int_mask);\n-\t\ttmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));\n-\t\ttmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));\n+\t\tif (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) {\n+\t\t\ttmp |= FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));\n+\t\t\ttmp |= FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));\n+\t\t} else {\n+\t\t\ttmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));\n+\t\t\ttmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));\n+\t\t}\n \t\tSET_RW_32(dw, chan->dir, int_mask, tmp);\n \t\t/* Linked list error */\n \t\ttmp = GET_RW_32(dw, chan->dir, linked_list_err_en);\ndiff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h\nindex 11d6eeb19fff..8c1b1d25fa44 100644\n--- a/include/linux/dma/edma.h\n+++ b/include/linux/dma/edma.h\n@@ -61,6 +61,40 @@ enum dw_edma_chip_flags {\n \tDW_EDMA_CHIP_LOCAL\t= BIT(0),\n };\n \n+/*\n+ * enum dw_edma_ch_irq_mode - per-channel interrupt routing control\n+ * @DW_EDMA_CH_IRQ_DEFAULT: LIE=1/RIE=1, local interrupt unmasked\n+ * @DW_EDMA_CH_IRQ_LOCAL: LIE=1/RIE=0\n+ * @DW_EDMA_CH_IRQ_REMOTE: LIE=1/RIE=1, local interrupt masked\n+ *\n+ * Some implementations require using LIE=1/RIE=1 with the local interrupt\n+ * masked to generate a remote-only interrupt (rather than LIE=0/RIE=1).\n+ * See the DesignWare endpoint databook 5.40, \"Hint\" below \"Figure 8-22\n+ * Write Interrupt Generation\".\n+ */\n+enum dw_edma_ch_irq_mode {\n+\tDW_EDMA_CH_IRQ_DEFAULT\t= 0,\n+\tDW_EDMA_CH_IRQ_LOCAL,\n+\tDW_EDMA_CH_IRQ_REMOTE,\n+};\n+\n+/**\n+ * dw_edma_chan_irq_config - configure per-channel interrupt routing\n+ * @chan: DMA channel obtained from dma_request_channel()\n+ * @mode: interrupt routing mode\n+ *\n+ * Returns 0 on success, -EINVAL for invalid @mode, or -ENODEV if @chan does\n+ * not belong to the DesignWare eDMA driver.\n+ */\n+int dw_edma_chan_irq_config(struct dma_chan *chan,\n+\t\t\t enum dw_edma_ch_irq_mode mode);\n+\n+/**\n+ * dw_edma_chan_ignore_irq - tell whether local IRQ handling should be ignored\n+ * @chan: DMA channel obtained from dma_request_channel()\n+ */\n+bool dw_edma_chan_ignore_irq(struct dma_chan *chan);\n+\n #if IS_REACHABLE(CONFIG_PCIE_DW)\n /**\n * dw_edma_get_reg_window - get eDMA register base and size\n@@ -141,4 +175,16 @@ static inline int dw_edma_remove(struct dw_edma_chip *chip)\n }\n #endif /* CONFIG_DW_EDMA */\n \n+#if !IS_ENABLED(CONFIG_DW_EDMA)\n+static inline int dw_edma_chan_irq_config(struct dma_chan *chan,\n+\t\t\t\t\t enum dw_edma_ch_irq_mode mode)\n+{\n+\treturn -ENODEV;\n+}\n+static inline bool dw_edma_chan_ignore_irq(struct dma_chan *chan)\n+{\n+\treturn false;\n+}\n+#endif\n+\n #endif /* _DW_EDMA_H */\n", "prefixes": [ "RFC", "v3", "18/35" ] }