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GET /api/1.0/patches/2175249/?format=api
{ "id": 2175249, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175249/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-dt-bindings-pci-qcom-v2-8-873721599754@oss.qualcomm.com>", "date": "2025-12-17T16:19:14", "name": "[v2,08/12] dt-bindings: PCI: qcom,pcie-ipq4019: Move IPQ4019 to dedicated schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6baefdbe682fcf98b64ff9892005a5fa4177e876", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/1.0/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-dt-bindings-pci-qcom-v2-8-873721599754@oss.qualcomm.com/mbox/", "series": [ { "id": 485718, "url": "http://patchwork.ozlabs.org/api/1.0/series/485718/?format=api", "date": "2025-12-17T16:19:09", "name": "dt-bindings: PCI: qcom: Move remaining devices to dedicated schema", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485718/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175249/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43217-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=dYGWCkDv;\n\tdkim=pass (2048-bit key;\n unprotected) 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"<20251217-dt-bindings-pci-qcom-v2-8-873721599754@oss.qualcomm.com>", "References": "<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "In-Reply-To": "\n <20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=7671;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=fwwvTAHHN2lNGk849hvRPwFvied04vmzzOv5gjzHx/0=;\n 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a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_03,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 bulkscore=0 priorityscore=1501 suspectscore=0 impostorscore=0\n clxscore=1015 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128" }, "content": "Move IPQ4019 PCIe devices from qcom,pcie.yaml binding to a dedicated\nfile to make reviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,pcie-ipq4019.yaml | 146 +++++++++++++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ------\n 2 files changed, 146 insertions(+), 38 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml\nnew file mode 100644\nindex 000000000000..fd6ecd1c43a1\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml\n@@ -0,0 +1,146 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm IPQ4019 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-ipq4019\n+\n+ reg:\n+ maxItems: 4\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: elbi\n+ - const: parf\n+ - const: config\n+\n+ clocks:\n+ maxItems: 3\n+\n+ clock-names:\n+ items:\n+ - const: aux\n+ - const: master_bus # Master AXI clock\n+ - const: slave_bus # Slave AXI clock\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+\n+ resets:\n+ maxItems: 12\n+\n+ reset-names:\n+ items:\n+ - const: axi_m # AXI master reset\n+ - const: axi_s # AXI slave reset\n+ - const: pipe\n+ - const: axi_m_vmid\n+ - const: axi_s_xpu\n+ - const: parf\n+ - const: phy\n+ - const: axi_m_sticky # AXI master sticky reset\n+ - const: pipe_sticky\n+ - const: pwr\n+ - const: ahb\n+ - const: phy_ahb\n+\n+required:\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ pcie@40000000 {\n+ compatible = \"qcom,pcie-ipq4019\";\n+ reg = <0x40000000 0xf1d>,\n+ <0x40000f20 0xa8>,\n+ <0x80000 0x2000>,\n+ <0x40100000 0x1000>;\n+ reg-names = \"dbi\", \"elbi\", \"parf\", \"config\";\n+ ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,\n+ <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;\n+\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <1>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ clocks = <&gcc GCC_PCIE_AHB_CLK>,\n+ <&gcc GCC_PCIE_AXI_M_CLK>,\n+ <&gcc GCC_PCIE_AXI_S_CLK>;\n+ clock-names = \"aux\",\n+ \"master_bus\",\n+ \"slave_bus\";\n+\n+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi\";\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n+ <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n+ <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n+ <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n+\n+ resets = <&gcc PCIE_AXI_M_ARES>,\n+ <&gcc PCIE_AXI_S_ARES>,\n+ <&gcc PCIE_PIPE_ARES>,\n+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,\n+ <&gcc PCIE_AXI_S_XPU_ARES>,\n+ <&gcc PCIE_PARF_XPU_ARES>,\n+ <&gcc PCIE_PHY_ARES>,\n+ <&gcc PCIE_AXI_M_STICKY_ARES>,\n+ <&gcc PCIE_PIPE_STICKY_ARES>,\n+ <&gcc PCIE_PWR_ARES>,\n+ <&gcc PCIE_AHB_ARES>,\n+ <&gcc PCIE_PHY_AHB_ARES>;\n+ reset-names = \"axi_m\",\n+ \"axi_s\",\n+ \"pipe\",\n+ \"axi_m_vmid\",\n+ \"axi_s_xpu\",\n+ \"parf\",\n+ \"phy\",\n+ \"axi_m_sticky\",\n+ \"pipe_sticky\",\n+ \"pwr\",\n+ \"ahb\",\n+ \"phy_ahb\";\n+\n+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\nindex 8ff4c16b31c8..1ff63d7e772a 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n@@ -20,7 +20,6 @@ properties:\n - enum:\n - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n- - qcom,pcie-ipq4019\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064-v2\n - qcom,pcie-ipq9574\n@@ -140,7 +139,6 @@ allOf:\n contains:\n enum:\n - qcom,pcie-apq8064\n- - qcom,pcie-ipq4019\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064v2\n then:\n@@ -258,40 +256,6 @@ allOf:\n items:\n - const: core # Core reset\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-ipq4019\n- then:\n- properties:\n- clocks:\n- minItems: 3\n- maxItems: 3\n- clock-names:\n- items:\n- - const: aux # Auxiliary (AUX) clock\n- - const: master_bus # Master AXI clock\n- - const: slave_bus # Slave AXI clock\n- resets:\n- minItems: 12\n- maxItems: 12\n- reset-names:\n- items:\n- - const: axi_m # AXI master reset\n- - const: axi_s # AXI slave reset\n- - const: pipe # PIPE reset\n- - const: axi_m_vmid # VMID reset\n- - const: axi_s_xpu # XPU reset\n- - const: parf # PARF reset\n- - const: phy # PHY reset\n- - const: axi_m_sticky # AXI sticky reset\n- - const: pipe_sticky # PIPE sticky reset\n- - const: pwr # PWR reset\n- - const: ahb # AHB reset\n- - const: phy_ahb # PHY AHB reset\n-\n - if:\n properties:\n compatible:\n@@ -369,7 +333,6 @@ allOf:\n contains:\n enum:\n - qcom,pcie-apq8064\n- - qcom,pcie-ipq4019\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064v2\n - qcom,pcie-ipq9574\n@@ -428,7 +391,6 @@ allOf:\n enum:\n - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n- - qcom,pcie-ipq4019\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064-v2\n then:\n", "prefixes": [ "v2", "08/12" ] }