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GET /api/1.0/patches/2175246/?format=api
{ "id": 2175246, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175246/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-dt-bindings-pci-qcom-v2-6-873721599754@oss.qualcomm.com>", "date": "2025-12-17T16:19:12", "name": "[v2,06/12] dt-bindings: PCI: qcom,pcie-ipq6018: Move IPQ6018 and IPQ8074 Gen3 to dedicated schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "34a54e011ab28574297e37b87a6a64a49b5fd54d", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/1.0/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-dt-bindings-pci-qcom-v2-6-873721599754@oss.qualcomm.com/mbox/", "series": [ { "id": 485718, "url": "http://patchwork.ozlabs.org/api/1.0/series/485718/?format=api", "date": "2025-12-17T16:19:09", "name": "dt-bindings: PCI: qcom: Move remaining devices to dedicated schema", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485718/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175246/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43215-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=fnAUHClV;\n\tdkim=pass (2048-bit key;\n unprotected) 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"7bit", "Message-Id": "<20251217-dt-bindings-pci-qcom-v2-6-873721599754@oss.qualcomm.com>", "References": "<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "In-Reply-To": "\n <20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=9759;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n 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a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22\n a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_03,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0\n adultscore=0 priorityscore=1501 clxscore=1015 suspectscore=0\n lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001\n definitions=main-2512170128" }, "content": "Move IPQ6018 and IPQ8074 Gen3 (which is the same as in IPQ6018) PCIe\ndevices from qcom,pcie.yaml binding to a dedicated file to make\nreviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n - Disallow legacy/incomplete description with only one interrupt and\n expect exactly nine of them.\n - Do not require power domains on IPQ6018, because old binding already\n does not require them for IPQ8074 Gen3, devices are the same and\n in-tree DTS lacks power domains.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,pcie-ipq6018.yaml | 179 +++++++++++++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 40 -----\n 2 files changed, 179 insertions(+), 40 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml\nnew file mode 100644\nindex 000000000000..6843570eb051\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml\n@@ -0,0 +1,179 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm IPQ6018 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-ipq6018\n+ - qcom,pcie-ipq8074-gen3\n+\n+ reg:\n+ minItems: 5\n+ maxItems: 6\n+\n+ reg-names:\n+ minItems: 5\n+ items:\n+ - const: dbi\n+ - const: elbi\n+ - const: atu\n+ - const: parf\n+ - const: config\n+ - const: mhi\n+\n+ clocks:\n+ maxItems: 5\n+\n+ clock-names:\n+ items:\n+ - const: iface # PCIe to SysNOC BIU clock\n+ - const: axi_m # AXI Master clock\n+ - const: axi_s # AXI Slave clock\n+ - const: axi_bridge\n+ - const: rchng\n+\n+ interrupts:\n+ maxItems: 9\n+\n+ interrupt-names:\n+ items:\n+ - const: msi0\n+ - const: msi1\n+ - const: msi2\n+ - const: msi3\n+ - const: msi4\n+ - const: msi5\n+ - const: msi6\n+ - const: msi7\n+ - const: global\n+\n+ resets:\n+ maxItems: 8\n+\n+ reset-names:\n+ items:\n+ - const: pipe\n+ - const: sleep\n+ - const: sticky # Core sticky reset\n+ - const: axi_m # AXI master reset\n+ - const: axi_s # AXI slave reset\n+ - const: ahb\n+ - const: axi_m_sticky # AXI master sticky reset\n+ - const: axi_s_sticky # AXI slave sticky reset\n+\n+required:\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ #include <dt-bindings/reset/qcom,gcc-ipq6018.h>\n+\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie@20000000 {\n+ compatible = \"qcom,pcie-ipq6018\";\n+ reg = <0x0 0x20000000 0x0 0xf1d>,\n+ <0x0 0x20000f20 0x0 0xa8>,\n+ <0x0 0x20001000 0x0 0x1000>,\n+ <0x0 0x80000 0x0 0x4000>,\n+ <0x0 0x20100000 0x0 0x1000>;\n+ reg-names = \"dbi\", \"elbi\", \"atu\", \"parf\", \"config\";\n+ ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,\n+ <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;\n+\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <1>;\n+ max-link-speed = <3>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,\n+ <&gcc GCC_PCIE0_AXI_M_CLK>,\n+ <&gcc GCC_PCIE0_AXI_S_CLK>,\n+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,\n+ <&gcc PCIE0_RCHNG_CLK>;\n+ clock-names = \"iface\",\n+ \"axi_m\",\n+ \"axi_s\",\n+ \"axi_bridge\",\n+ \"rchng\";\n+\n+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi0\",\n+ \"msi1\",\n+ \"msi2\",\n+ \"msi3\",\n+ \"msi4\",\n+ \"msi5\",\n+ \"msi6\",\n+ \"msi7\",\n+ \"global\";\n+\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n+ <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n+ <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n+ <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n+\n+ phys = <&pcie_phy>;\n+ phy-names = \"pciephy\";\n+\n+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,\n+ <&gcc GCC_PCIE0_SLEEP_ARES>,\n+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,\n+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,\n+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,\n+ <&gcc GCC_PCIE0_AHB_ARES>,\n+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,\n+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;\n+ reset-names = \"pipe\",\n+ \"sleep\",\n+ \"sticky\",\n+ \"axi_m\",\n+ \"axi_s\",\n+ \"ahb\",\n+ \"axi_m_sticky\",\n+ \"axi_s_sticky\";\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+ };\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\nindex b448b8f07f55..780a77f35b34 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n@@ -21,11 +21,9 @@ properties:\n - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n - qcom,pcie-ipq4019\n- - qcom,pcie-ipq6018\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064-v2\n - qcom,pcie-ipq8074\n- - qcom,pcie-ipq8074-gen3\n - qcom,pcie-ipq9574\n - qcom,pcie-msm8996\n - items:\n@@ -164,8 +162,6 @@ allOf:\n compatible:\n contains:\n enum:\n- - qcom,pcie-ipq6018\n- - qcom,pcie-ipq8074-gen3\n - qcom,pcie-ipq9574\n then:\n properties:\n@@ -350,39 +346,6 @@ allOf:\n - const: ahb # AHB Reset\n - const: axi_m_sticky # AXI Master Sticky reset\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-ipq6018\n- - qcom,pcie-ipq8074-gen3\n- then:\n- properties:\n- clocks:\n- minItems: 5\n- maxItems: 5\n- clock-names:\n- items:\n- - const: iface # PCIe to SysNOC BIU clock\n- - const: axi_m # AXI Master clock\n- - const: axi_s # AXI Slave clock\n- - const: axi_bridge # AXI bridge clock\n- - const: rchng\n- resets:\n- minItems: 8\n- maxItems: 8\n- reset-names:\n- items:\n- - const: pipe # PIPE reset\n- - const: sleep # Sleep reset\n- - const: sticky # Core Sticky reset\n- - const: axi_m # AXI Master reset\n- - const: axi_s # AXI Slave reset\n- - const: ahb # AHB Reset\n- - const: axi_m_sticky # AXI Master Sticky reset\n- - const: axi_s_sticky # AXI Slave Sticky reset\n-\n - if:\n properties:\n compatible:\n@@ -443,7 +406,6 @@ allOf:\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064v2\n - qcom,pcie-ipq8074\n- - qcom,pcie-ipq8074-gen3\n - qcom,pcie-ipq9574\n then:\n required:\n@@ -466,9 +428,7 @@ allOf:\n compatible:\n contains:\n enum:\n- - qcom,pcie-ipq6018\n - qcom,pcie-ipq8074\n- - qcom,pcie-ipq8074-gen3\n - qcom,pcie-msm8996\n - qcom,pcie-msm8998\n then:\n", "prefixes": [ "v2", "06/12" ] }