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GET /api/1.0/patches/2175245/?format=api
{ "id": 2175245, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175245/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-dt-bindings-pci-qcom-v2-5-873721599754@oss.qualcomm.com>", "date": "2025-12-17T16:19:11", "name": "[v2,05/12] dt-bindings: PCI: qcom,pcie-ipq5018: Move IPQ5018 to dedicated schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e389d1c3778ba87a6cb5ed09608b179386abc9ec", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/1.0/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-dt-bindings-pci-qcom-v2-5-873721599754@oss.qualcomm.com/mbox/", "series": [ { "id": 485718, "url": "http://patchwork.ozlabs.org/api/1.0/series/485718/?format=api", "date": "2025-12-17T16:19:09", "name": "dt-bindings: PCI: qcom: Move remaining devices to dedicated schema", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485718/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175245/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43214-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=DvfjvJIk;\n\tdkim=pass (2048-bit key;\n unprotected) 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dt-bindings: PCI: qcom,pcie-ipq5018: Move IPQ5018\n to dedicated schema", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251217-dt-bindings-pci-qcom-v2-5-873721599754@oss.qualcomm.com>", "References": "<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "In-Reply-To": "\n <20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=9369;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=MQUR4X4VE6vtHyT8c+tJ7bUFyjg9QuKpuh0a8nl1qFM=;\n b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpQtgAdGs2q9KL4oLnUovLpOSHlYkCYGnvwHFE9\n vghrdhtKGCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaULYAAAKCRDBN2bmhouD\n 1+e1EACC7+ikNoWhbW9ihK7l0nRx9g5UnPFbzDTDaBMC3fTheQosql8IlYH6Dif35RN9WHipQ0I\n xGYSjWct0d94eRnkht+c/doHVHBfvZFqDWDsniBXQTrxaK8MHOIbj4UaKVoIYIv+S7zCa+GWQ7+\n P3dh6/pcY/wKqmlv9GW3IIRHtWUr0TSeEUu9zxvqJGFrGggdrIqdea+Hx9rgACEYmssuoZc8EKo\n tjXrJw1YRqmEKHDDVvALIidSAy9Ye0dRrsSbxIfDofsxtraB/w9Ovuo3LYXHgVv5wZZTNWgmr69\n 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bulkscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128" }, "content": "Move IPQ5018 PCIe devices from qcom,pcie.yaml binding to a dedicated\nfile to make reviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,pcie-ipq5018.yaml | 189 +++++++++++++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ------\n 2 files changed, 189 insertions(+), 50 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml\nnew file mode 100644\nindex 000000000000..20c2c946f474\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml\n@@ -0,0 +1,189 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm IPQ5018 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-ipq5018\n+\n+ reg:\n+ minItems: 5\n+ maxItems: 6\n+\n+ reg-names:\n+ minItems: 5\n+ items:\n+ - const: dbi\n+ - const: elbi\n+ - const: atu\n+ - const: parf\n+ - const: config\n+ - const: mhi\n+\n+ clocks:\n+ maxItems: 6\n+\n+ clock-names:\n+ items:\n+ - const: iface # PCIe to SysNOC BIU clock\n+ - const: axi_m # AXI Master clock\n+ - const: axi_s # AXI Slave clock\n+ - const: ahb\n+ - const: aux\n+ - const: axi_bridge\n+\n+ interrupts:\n+ maxItems: 9\n+\n+ interrupt-names:\n+ items:\n+ - const: msi0\n+ - const: msi1\n+ - const: msi2\n+ - const: msi3\n+ - const: msi4\n+ - const: msi5\n+ - const: msi6\n+ - const: msi7\n+ - const: global\n+\n+ resets:\n+ maxItems: 8\n+\n+ reset-names:\n+ items:\n+ - const: pipe\n+ - const: sleep\n+ - const: sticky # Core sticky reset\n+ - const: axi_m # AXI master reset\n+ - const: axi_s # AXI slave reset\n+ - const: ahb\n+ - const: axi_m_sticky # AXI master sticky reset\n+ - const: axi_s_sticky # AXI slave sticky reset\n+\n+required:\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>\n+\n+ pcie@a0000000 {\n+ compatible = \"qcom,pcie-ipq5018\";\n+ reg = <0xa0000000 0xf1d>,\n+ <0xa0000f20 0xa8>,\n+ <0xa0001000 0x1000>,\n+ <0x00080000 0x3000>,\n+ <0xa0100000 0x1000>,\n+ <0x00083000 0x1000>;\n+ reg-names = \"dbi\",\n+ \"elbi\",\n+ \"atu\",\n+ \"parf\",\n+ \"config\",\n+ \"mhi\";\n+ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,\n+ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;\n+\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <2>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */\n+ max-link-speed = <2>;\n+\n+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,\n+ <&gcc GCC_PCIE0_AXI_M_CLK>,\n+ <&gcc GCC_PCIE0_AXI_S_CLK>,\n+ <&gcc GCC_PCIE0_AHB_CLK>,\n+ <&gcc GCC_PCIE0_AUX_CLK>,\n+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;\n+ clock-names = \"iface\",\n+ \"axi_m\",\n+ \"axi_s\",\n+ \"ahb\",\n+ \"aux\",\n+ \"axi_bridge\";\n+\n+ msi-map = <0x0 &v2m0 0x0 0xff8>;\n+\n+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi0\",\n+ \"msi1\",\n+ \"msi2\",\n+ \"msi3\",\n+ \"msi4\",\n+ \"msi5\",\n+ \"msi6\",\n+ \"msi7\",\n+ \"global\";\n+\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ phys = <&pcie0_phy>;\n+ phy-names = \"pciephy\";\n+\n+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,\n+ <&gcc GCC_PCIE0_SLEEP_ARES>,\n+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,\n+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,\n+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,\n+ <&gcc GCC_PCIE0_AHB_ARES>,\n+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,\n+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;\n+ reset-names = \"pipe\",\n+ \"sleep\",\n+ \"sticky\",\n+ \"axi_m\",\n+ \"axi_s\",\n+ \"ahb\",\n+ \"axi_m_sticky\",\n+ \"axi_s_sticky\";\n+\n+ perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;\n+ wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\nindex db7d91d42af8..b448b8f07f55 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n@@ -21,7 +21,6 @@ properties:\n - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n - qcom,pcie-ipq4019\n- - qcom,pcie-ipq5018\n - qcom,pcie-ipq6018\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064-v2\n@@ -165,7 +164,6 @@ allOf:\n compatible:\n contains:\n enum:\n- - qcom,pcie-ipq5018\n - qcom,pcie-ipq6018\n - qcom,pcie-ipq8074-gen3\n - qcom,pcie-ipq9574\n@@ -300,53 +298,6 @@ allOf:\n - const: ahb # AHB reset\n - const: phy_ahb # PHY AHB reset\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-ipq5018\n- then:\n- properties:\n- clocks:\n- minItems: 6\n- maxItems: 6\n- clock-names:\n- items:\n- - const: iface # PCIe to SysNOC BIU clock\n- - const: axi_m # AXI Master clock\n- - const: axi_s # AXI Slave clock\n- - const: ahb # AHB clock\n- - const: aux # Auxiliary clock\n- - const: axi_bridge # AXI bridge clock\n- resets:\n- minItems: 8\n- maxItems: 8\n- reset-names:\n- items:\n- - const: pipe # PIPE reset\n- - const: sleep # Sleep reset\n- - const: sticky # Core sticky reset\n- - const: axi_m # AXI master reset\n- - const: axi_s # AXI slave reset\n- - const: ahb # AHB reset\n- - const: axi_m_sticky # AXI master sticky reset\n- - const: axi_s_sticky # AXI slave sticky reset\n- interrupts:\n- minItems: 9\n- maxItems: 9\n- interrupt-names:\n- items:\n- - const: msi0\n- - const: msi1\n- - const: msi2\n- - const: msi3\n- - const: msi4\n- - const: msi5\n- - const: msi6\n- - const: msi7\n- - const: global\n-\n - if:\n properties:\n compatible:\n@@ -489,7 +440,6 @@ allOf:\n enum:\n - qcom,pcie-apq8064\n - qcom,pcie-ipq4019\n- - qcom,pcie-ipq5018\n - qcom,pcie-ipq8064\n - qcom,pcie-ipq8064v2\n - qcom,pcie-ipq8074\n", "prefixes": [ "v2", "05/12" ] }