Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175242/?format=api
{ "id": 2175242, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175242/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-dt-bindings-pci-qcom-v2-10-873721599754@oss.qualcomm.com>", "date": "2025-12-17T16:19:16", "name": "[v2,10/12] dt-bindings: PCI: qcom,pcie-apq8064: Move APQ8064 to dedicated schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ea790eba251ea4dac420f4ce6b3cc932899906c7", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/1.0/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-dt-bindings-pci-qcom-v2-10-873721599754@oss.qualcomm.com/mbox/", "series": [ { "id": 485718, "url": "http://patchwork.ozlabs.org/api/1.0/series/485718/?format=api", "date": "2025-12-17T16:19:09", "name": "dt-bindings: PCI: qcom: Move remaining devices to dedicated schema", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485718/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175242/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43219-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Nta7Ousy;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZErA+PcN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-43219-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Nta7Ousy\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"ZErA+PcN\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWfPt6mchz1y0P\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 03:29:06 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 3B2DC3093D90\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 16:21:57 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id C38B734D91B;\n\tWed, 17 Dec 2025 16:19:47 +0000 (UTC)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F80F34D4ED\n\tfor <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 16:19:45 +0000 (UTC)", "from pps.filterd (m0279869.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 5BHCKno13329722\n\tfor <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 16:19:44 GMT", "from mail-qt1-f200.google.com (mail-qt1-f200.google.com\n [209.85.160.200])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b3nkkj7uv-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 16:19:44 +0000 (GMT)", "by mail-qt1-f200.google.com with SMTP id\n d75a77b69052e-4f1dea13d34so106992871cf.1\n for <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 08:19:44 -0800 (PST)", "from [127.0.1.1] ([178.197.218.51])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-b7cfa29be92sm1987868666b.10.2025.12.17.08.19.41\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 17 Dec 2025 08:19:42 -0800 (PST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1765988387; cv=none;\n b=ur07HWDzRyCuU7MtzmwLBWRtDJ69ps6qKJ9kE5JdD8b0xrNDKXNI0rMzsOFY8MsLP0TFaClzrf1OKWsCr9Z87URkgGX6uX6I8pnpI135kn61/L2kyayIHSErkqYzNHs9FuSN7FjKoUwUl70QC0ZyNFjhIcPSvmiy6dxra4Ex3kQ=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1765988387; c=relaxed/simple;\n\tbh=6/HmpwGYfmKbFRr3CJa27+uov7PaOyYXoGw/uFtok4Y=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=Q1bQaHvaE1RQQGEBs2tUYM/2AKzFRNEHf7jXtduL//gOU1KEHYoxcykYP1/b+eMsdwHWn9KhZHXz8hqtD/mpeRrFroc8KX2058lafKPBmbGvBcDSU/nmSifANBiwznoA6BxKVc8GLdQS5pZjOPDH861rVNMHPggj3oTLjEMPLvo=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=oss.qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=Nta7Ousy;\n dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=ZErA+PcN; arc=none smtp.client-ip=205.220.180.131", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n\tqfN46sn+2SyB5Am2UdJ3F20SHbaJMD1DTMLIqCf/oiA=; b=Nta7Ousy6KfGEchU\n\tmr+tjHkjufseqs4S9PDpUoYNTKydOf1KxuKvtaCj84fE8ZHc+MoEUFEn3VayHSvK\n\tdNGrVeBEwTQn6hiOgAMOU5vV4888/SuiAD6tNKNowQcjr2RjZUlxnpShz1+wiJa+\n\tNifgy3GoeFuzgVNRKHMYwNJz/ln2SK5YT3m7UuWhd2yoBM3zD0ud/rGGTL3uHgwF\n\tDB2bNCOphkI7yujI5SFNx9ZQuOYa5OXnpGGyqwGYsHRqu+a28ubOBUB9IaNXORzM\n\t/UGH8DBOKgxiI8OtdknHIVRKrsLqJKE33HedLItYT3JqhmoZlXHe+fzKAwhbQH7l\n\t2YeOWQ==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1765988384; x=1766593184;\n darn=vger.kernel.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to;\n bh=qfN46sn+2SyB5Am2UdJ3F20SHbaJMD1DTMLIqCf/oiA=;\n b=ZErA+PcNA05IzOpeXnCwVvKxqQA84ivnMbfDeaWmvx/w/+w89YA439u1Vb0ZQxu0Zi\n 5ggXfMo8TdlJ3hRF7TVwvj48ocNwbWH28/bAmgY128+mfl3EhGJNe01nJKz8yjB7duLa\n cIdl5Ixorko9RHx1BzO7iuhTEMXwLMXE1AfN2QaxALimevYlxkrMmgtZCDlbD3wRxDvy\n GR2ZbODFOFQgqI4JZPwBC0hrunWWwF02Jr0apfFpdl3GJAyPRd3CHSj7NKarK7rTF+YY\n g5XrZldDjHOaV+V19zNyufo7V7GVxSq64SkWTgRQWBTC7fmTicaq7hE3vDR/J10oGgJh\n f3sQ==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1765988384; x=1766593184;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=qfN46sn+2SyB5Am2UdJ3F20SHbaJMD1DTMLIqCf/oiA=;\n b=amrrQd6vlmdnKijhmPBCrYkzKjT+0eyW8OcSq1rYAXK6DSikFol3dijr3VmTXIrUcJ\n Ma8/r5nTDsnN6nLz5LGA3/gBLkS/5PIcFJihYjGzJZ6d0UbuQpnPJrerSuHoE0pBs1yO\n E586Lcyxfi6Z7zBEcDAP8mfqQrgWl6i/Z41M4OGflTzQB7w7xjhL2yMWTOyPxFNRUTxo\n 1DUdLbgoolDu3toao8ZtNFg2GrgktEtjKLqtlE6QkrJ2zwE9XNXmMWKyqh5CXDVhX41W\n xOrFoQkNo3zzCrXFmSqfAWTOe+EK2bsttpOWsj3WG7kmco1nVlLKdzVSuAbtsBbnkqqi\n 9Djw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCXyz8wy+rsjiOrlCNXbq7EdtasGcjDNYX7KDsodCT3dH6JHZ85+qjE/fbRmlkUaF+IRUhpvSB6ahs0=@vger.kernel.org", "X-Gm-Message-State": "AOJu0YwItaBpEQrAlDbkKmIVZytvVoOWc9TX2ACPyeiWV7qWJkjhWbKo\n\tFEcXDEjFZIHe0Q5DQlqoyE3xF5ZAnous8sD1VPfRJ+B6XGNLy2gRAXrX41un+x2OBxMzRk7IWoe\n\tztGvkdLsRWCCkT49CqlKEn817JQiqxd9wcelqUjNGFioTmVolcVg4rhOGh20pRSI=", "X-Gm-Gg": "AY/fxX7vWumBSB/Kv2P0Te0ExuDH+YwJPDeveN3MeCw2pJS48jOmmDReyb7Gvvb1LR3\n\ts1Lw2ON8g2Cg8vmKPWoQNFKSbAyXqufO5cBFo/jJ/ZTAB0HfmtxRfyOzpk6SfjYsTk7jt058XuF\n\tTXPxHRzjSXR8E3k6BITO4xUu6EDXutMrr8a4Y3W+yYVop4myv+/V6OSeZHumk4n44hT9xd6hwaF\n\tyQS97IKfp/WJw39CSuLQi2t9jr7+d+eFm4n9fMdkdOsehJEEOvU3N5AM0wse/6W1RVXjKKZCX3q\n\tMSi2iN78gPvwnUetbeKsecNybQmYXfjx+dcrYtXb234gFiLsqpBgPLBJIqdpsF530UXJ42F1MAT\n\tGDDoU5+RwSjp8tmWI2eKFlVW6FyP65dmi", "X-Received": [ "by 2002:a05:622a:a13:b0:4f1:b714:5864 with SMTP id\n d75a77b69052e-4f1d0165aaamr269467171cf.0.1765988383427;\n Wed, 17 Dec 2025 08:19:43 -0800 (PST)", "by 2002:a05:622a:a13:b0:4f1:b714:5864 with SMTP id\n d75a77b69052e-4f1d0165aaamr269466541cf.0.1765988382772;\n Wed, 17 Dec 2025 08:19:42 -0800 (PST)" ], "X-Google-Smtp-Source": "\n AGHT+IFzYwoZ5/uoNxipgqR9z4aoS1IJ9ExodTLWNDcXvN6jr8uFmuFNmFUGZM1k3UR4vMHYk24h1Q==", "From": "Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "Date": "Wed, 17 Dec 2025 17:19:16 +0100", "Subject": "[PATCH v2 10/12] dt-bindings: PCI: qcom,pcie-apq8064: Move APQ8064\n to dedicated schema", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20251217-dt-bindings-pci-qcom-v2-10-873721599754@oss.qualcomm.com>", "References": "<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "In-Reply-To": "\n <20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=11184;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=6/HmpwGYfmKbFRr3CJa27+uov7PaOyYXoGw/uFtok4Y=;\n b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpQtgE7j6B/jRRDH3SKstx+rGFj+iW17tShwiVW\n EZXzhg6jeOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaULYBAAKCRDBN2bmhouD\n 14PID/0eoQ6sy8RNZAd6lM63OeyLFWMqgiu+WPwuG9bSjuPoK8HTweF09Nl4JY+3NLxDPVVqFs4\n K5STN+qE5QZBUJdvdtoezGLTcROV6NjyqmfcuxYRN+tb0qYFh06cgZrroDGJX7CKpViq2YV9eUq\n URNbe4uMM9VwgxjHbinWShUYAHjl0Y6Xgmn04h/efu7RS/baJWyvbPePatZZgH3jajTKhmjniZT\n SC2d7Tt5IH20UN4qtHnG+7XN9Mc31vLFa6b2+2b5HgUyL01NzDJqm0MWr5iYjYhhOdWGAiyyuec\n xUDYYLtBRvnvXpKrnGsTuVUOMGSJGqlgMMYsl1eMAQotCfcqw9bjnJC/4EJye0NUhHhwJpN0Sjy\n M62mQvqQRjJp6lLqXV+eizq418DD90MeySBTzSX2PoS8MKAnAea8mfBIEa+lCHlhqV6F/DXog4/\n indpi2gHb1l1LeH6o30Rj34EgszPPCUqvSpL3QkvTqIiUAlaRgvjpLJFeLwsJuHVybvl91L9ZE8\n z/PujA88np7+ZofpBx62tOcmCcoOp+VO/eZ/7ffL6BQh0SwBtdGi8oNVU+xVK8ZSmVc5I2V83AF\n ed2nmHSaGPAR9R6rIjCPGx0iqnNs4G/s0v28dpXLEviw9KBKrK29PXguWPbU+8VOghosMj2WTLT\n rz9he5/3sYQdodg==", "X-Developer-Key": "i=krzysztof.kozlowski@oss.qualcomm.com; a=openpgp;\n fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B", "X-Proofpoint-GUID": "LNC33ZVVXrzoRQsD7WMtIPMZ36YDWRks", "X-Proofpoint-ORIG-GUID": "LNC33ZVVXrzoRQsD7WMtIPMZ36YDWRks", "X-Authority-Analysis": "v=2.4 cv=f/RFxeyM c=1 sm=1 tr=0 ts=6942d820 cx=c_pps\n a=JbAStetqSzwMeJznSMzCyw==:117 a=hmARNUlj3OVxZ3RlbIsQyw==:17\n a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8\n a=-DzKK8azUWmf2IRN-tYA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22\n a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjUxMjE3MDEyOCBTYWx0ZWRfXzOQKeoooWOO3\n MLV2GngpMkff9jk4MAl43S0YX7tGU+pqClzucTwOhHsfUjc3Kag1Sh1yK9l1Q/j1mTavEGffvav\n +CUV4ndcJc6zPdwBUVyWjXaAGnTSdQwP3HDlWe+oGEvXcnqMCY6tSbM9AKWsY4RHZJ1zrE4+CAN\n h3DvhDdfFAVjQDqwBFrHorMfcSABMiHX0oWLsUV+W5Bbjn3KqWn+pgCPRc32c5UI/gn1vMcKgZ5\n JK3UlOmr2vuL6dzf/kYXouzxccA6QTbq/r4ZGue1bvVoGgG8ZaaowQZsKsIdHDWkQGnL9KKIIan\n sMCWOnSRSURFES9RaNPwmdcni55YSBIdEPfK+cdSB6KyqBlot/c9EuJ5KKBiL5f+wPKqsG7XSiI\n Usd0hyhMhu4AdTK3eMSZ/e5HBIaEXg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_03,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015\n priorityscore=1501 malwarescore=0 adultscore=0 bulkscore=0 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128" }, "content": "Move APQ8064 and IPQ8064 PCIe devices from qcom,pcie.yaml binding to a\ndedicated file to make reviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,pcie-apq8064.yaml | 170 +++++++++++++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 127 ---------------\n 2 files changed, 170 insertions(+), 127 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml\nnew file mode 100644\nindex 000000000000..eb5b81d1defc\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml\n@@ -0,0 +1,170 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8064.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm APQ8064/IPQ8064 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-apq8064\n+ - qcom,pcie-ipq8064\n+ - qcom,pcie-ipq8064-v2\n+\n+ reg:\n+ maxItems: 4\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: elbi\n+ - const: parf\n+ - const: config\n+\n+ clocks:\n+ minItems: 3\n+ maxItems: 5\n+\n+ clock-names:\n+ minItems: 3\n+ items:\n+ - const: core # Clocks the pcie hw block\n+ - const: iface # Configuration AHB clock\n+ - const: phy\n+ - const: aux\n+ - const: ref\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+\n+ resets:\n+ minItems: 5\n+ maxItems: 6\n+\n+ reset-names:\n+ minItems: 5\n+ items:\n+ - const: axi\n+ - const: ahb\n+ - const: por\n+ - const: pci\n+ - const: phy\n+ - const: ext\n+\n+ vdda-supply:\n+ description: A phandle to the core analog power supply\n+\n+ vdda_phy-supply:\n+ description: A phandle to the core analog power supply for PHY\n+\n+ vdda_refclk-supply:\n+ description: A phandle to the core analog power supply for IC which generates reference clock\n+\n+required:\n+ - resets\n+ - reset-names\n+ - vdda-supply\n+ - vdda_phy-supply\n+ - vdda_refclk-supply\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - qcom,pcie-apq8064\n+ then:\n+ properties:\n+ clocks:\n+ maxItems: 3\n+ clock-names:\n+ maxItems: 3\n+ resets:\n+ maxItems: 5\n+ reset-names:\n+ maxItems: 5\n+ else:\n+ properties:\n+ clocks:\n+ minItems: 5\n+ clock-names:\n+ minItems: 5\n+ resets:\n+ minItems: 6\n+ reset-names:\n+ minItems: 6\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,gcc-msm8960.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ #include <dt-bindings/reset/qcom,gcc-msm8960.h>\n+\n+ pcie@1b500000 {\n+ compatible = \"qcom,pcie-apq8064\";\n+ reg = <0x1b500000 0x1000>,\n+ <0x1b502000 0x80>,\n+ <0x1b600000 0x100>,\n+ <0x0ff00000 0x100000>;\n+ reg-names = \"dbi\", \"elbi\", \"parf\", \"config\";\n+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */\n+ <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */\n+\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <1>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ clocks = <&gcc PCIE_A_CLK>,\n+ <&gcc PCIE_H_CLK>,\n+ <&gcc PCIE_PHY_REF_CLK>;\n+ clock-names = \"core\", \"iface\", \"phy\";\n+\n+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi\";\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n+ <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n+ <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n+ <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n+\n+ resets = <&gcc PCIE_ACLK_RESET>,\n+ <&gcc PCIE_HCLK_RESET>,\n+ <&gcc PCIE_POR_RESET>,\n+ <&gcc PCIE_PCI_RESET>,\n+ <&gcc PCIE_PHY_RESET>;\n+ reset-names = \"axi\", \"ahb\", \"por\", \"pci\", \"phy\";\n+\n+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;\n+ vdda-supply = <&pm8921_s3>;\n+ vdda_phy-supply = <&pm8921_lvs6>;\n+ vdda_refclk-supply = <&v3p3_fixed>;\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\nindex 5af56911d204..c9b41c2254b1 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n@@ -18,10 +18,7 @@ properties:\n compatible:\n oneOf:\n - enum:\n- - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n- - qcom,pcie-ipq8064\n- - qcom,pcie-ipq8064-v2\n - qcom,pcie-msm8996\n - items:\n - const: qcom,pcie-msm8998\n@@ -78,12 +75,6 @@ properties:\n vdda-supply:\n description: A phandle to the core analog power supply\n \n- vdda_phy-supply:\n- description: A phandle to the core analog power supply for PHY\n-\n- vdda_refclk-supply:\n- description: A phandle to the core analog power supply for IC which generates reference clock\n-\n vddpe-3v3-supply:\n description: A phandle to the PCIe endpoint power supply\n \n@@ -127,26 +118,6 @@ anyOf:\n \n allOf:\n - $ref: /schemas/pci/pci-host-bridge.yaml#\n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8064\n- - qcom,pcie-ipq8064\n- - qcom,pcie-ipq8064v2\n- then:\n- properties:\n- reg:\n- minItems: 4\n- maxItems: 4\n- reg-names:\n- items:\n- - const: dbi # DesignWare PCIe registers\n- - const: elbi # External local bus interface registers\n- - const: parf # Qualcomm specific registers\n- - const: config # PCIe configuration space\n-\n - if:\n properties:\n compatible:\n@@ -168,44 +139,6 @@ allOf:\n - const: config # PCIe configuration space\n - const: mhi # MHI registers\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8064\n- - qcom,pcie-ipq8064\n- - qcom,pcie-ipq8064v2\n- then:\n- properties:\n- clocks:\n- minItems: 3\n- maxItems: 5\n- clock-names:\n- minItems: 3\n- items:\n- - const: core # Clocks the pcie hw block\n- - const: iface # Configuration AHB clock\n- - const: phy # Clocks the pcie PHY block\n- - const: aux # Clocks the pcie AUX block, not on apq8064\n- - const: ref # Clocks the pcie ref block, not on apq8064\n- resets:\n- minItems: 5\n- maxItems: 6\n- reset-names:\n- minItems: 5\n- items:\n- - const: axi # AXI reset\n- - const: ahb # AHB reset\n- - const: por # POR reset\n- - const: pci # PCI reset\n- - const: phy # PHY reset\n- - const: ext # EXT reset, not on apq8064\n- required:\n- - vdda-supply\n- - vdda_phy-supply\n- - vdda_refclk-supply\n-\n - if:\n properties:\n compatible:\n@@ -250,19 +183,6 @@ allOf:\n resets: false\n reset-names: false\n \n- - if:\n- not:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8064\n- - qcom,pcie-ipq8064\n- - qcom,pcie-ipq8064v2\n- then:\n- required:\n- - power-domains\n-\n - if:\n not:\n properties:\n@@ -312,10 +232,7 @@ allOf:\n compatible:\n contains:\n enum:\n- - qcom,pcie-apq8064\n - qcom,pcie-apq8084\n- - qcom,pcie-ipq8064\n- - qcom,pcie-ipq8064-v2\n then:\n properties:\n interrupts:\n@@ -327,50 +244,6 @@ allOf:\n unevaluatedProperties: false\n \n examples:\n- - |\n- #include <dt-bindings/interrupt-controller/arm-gic.h>\n- pcie@1b500000 {\n- compatible = \"qcom,pcie-ipq8064\";\n- reg = <0x1b500000 0x1000>,\n- <0x1b502000 0x80>,\n- <0x1b600000 0x100>,\n- <0x0ff00000 0x100000>;\n- reg-names = \"dbi\", \"elbi\", \"parf\", \"config\";\n- device_type = \"pci\";\n- linux,pci-domain = <0>;\n- bus-range = <0x00 0xff>;\n- num-lanes = <1>;\n- #address-cells = <3>;\n- #size-cells = <2>;\n- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,\n- <0x82000000 0 0 0x08000000 0 0x07e00000>;\n- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;\n- interrupt-names = \"msi\";\n- #interrupt-cells = <1>;\n- interrupt-map-mask = <0 0 0 0x7>;\n- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;\n- clocks = <&gcc 41>,\n- <&gcc 43>,\n- <&gcc 44>,\n- <&gcc 42>,\n- <&gcc 248>;\n- clock-names = \"core\", \"iface\", \"phy\", \"aux\", \"ref\";\n- resets = <&gcc 27>,\n- <&gcc 26>,\n- <&gcc 25>,\n- <&gcc 24>,\n- <&gcc 23>,\n- <&gcc 22>;\n- reset-names = \"axi\", \"ahb\", \"por\", \"pci\", \"phy\", \"ext\";\n- pinctrl-0 = <&pcie_pins_default>;\n- pinctrl-names = \"default\";\n- vdda-supply = <&pm8921_s3>;\n- vdda_phy-supply = <&pm8921_lvs6>;\n- vdda_refclk-supply = <&ext_3p3v>;\n- };\n - |\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n #include <dt-bindings/gpio/gpio.h>\n", "prefixes": [ "v2", "10/12" ] }