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GET /api/1.0/patches/2175240/?format=api
{ "id": 2175240, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175240/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-dt-bindings-pci-qcom-v2-2-873721599754@oss.qualcomm.com>", "date": "2025-12-17T16:19:08", "name": "[v2,02/12] dt-bindings: PCI: qcom,pcie-sdx55: Move SDX55 to dedicated schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "185f57c04d85f7ee05273dbd15db1bcc0a676e6c", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/1.0/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-dt-bindings-pci-qcom-v2-2-873721599754@oss.qualcomm.com/mbox/", "series": [ { "id": 485718, "url": "http://patchwork.ozlabs.org/api/1.0/series/485718/?format=api", "date": "2025-12-17T16:19:09", "name": "dt-bindings: PCI: qcom: Move remaining devices to dedicated schema", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485718/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175240/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43211-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=VROU9UeB;\n\tdkim=pass (2048-bit key;\n unprotected) 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02/12] dt-bindings: PCI: qcom,pcie-sdx55: Move SDX55 to\n dedicated schema", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251217-dt-bindings-pci-qcom-v2-2-873721599754@oss.qualcomm.com>", "References": "<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "In-Reply-To": "\n <20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley 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authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128" }, "content": "Move SDX55 PCIe devices from qcom,pcie.yaml binding to a dedicated file\nto make reviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n - Adding interrupts based on the DTS, which were missing in the\n all-in-one binding.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,pcie-sdx55.yaml | 172 +++++++++++++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------\n 2 files changed, 172 insertions(+), 48 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml\nnew file mode 100644\nindex 000000000000..7f6fd81e7ed0\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml\n@@ -0,0 +1,172 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm SDX55 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-sdx55\n+\n+ reg:\n+ minItems: 5\n+ maxItems: 6\n+\n+ reg-names:\n+ minItems: 5\n+ items:\n+ - const: parf\n+ - const: dbi\n+ - const: elbi\n+ - const: atu\n+ - const: config\n+ - const: mhi\n+\n+ clocks:\n+ maxItems: 7\n+\n+ clock-names:\n+ items:\n+ - const: pipe\n+ - const: aux\n+ - const: cfg\n+ - const: bus_master # Master AXI clock\n+ - const: bus_slave # Slave AXI clock\n+ - const: slave_q2a\n+ - const: sleep\n+\n+ interrupts:\n+ maxItems: 8\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+ - const: msi2\n+ - const: msi3\n+ - const: msi4\n+ - const: msi5\n+ - const: msi6\n+ - const: msi7\n+ - const: msi8\n+\n+ resets:\n+ maxItems: 1\n+\n+ reset-names:\n+ items:\n+ - const: pci\n+\n+required:\n+ - power-domains\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,gcc-sdx55.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ pcie@1c00000 {\n+ compatible = \"qcom,pcie-sdx55\";\n+ reg = <0x01c00000 0x3000>,\n+ <0x40000000 0xf1d>,\n+ <0x40000f20 0xc8>,\n+ <0x40001000 0x1000>,\n+ <0x40100000 0x100000>;\n+ reg-names = \"parf\",\n+ \"dbi\",\n+ \"elbi\",\n+ \"atu\",\n+ \"config\";\n+ ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,\n+ <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;\n+\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <1>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi\",\n+ \"msi2\",\n+ \"msi3\",\n+ \"msi4\",\n+ \"msi5\",\n+ \"msi6\",\n+ \"msi7\",\n+ \"msi8\";\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n+ <0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n+ <0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n+ <0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n+\n+ clocks = <&gcc GCC_PCIE_PIPE_CLK>,\n+ <&gcc GCC_PCIE_AUX_CLK>,\n+ <&gcc GCC_PCIE_CFG_AHB_CLK>,\n+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,\n+ <&gcc GCC_PCIE_SLV_AXI_CLK>,\n+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,\n+ <&gcc GCC_PCIE_SLEEP_CLK>;\n+ clock-names = \"pipe\",\n+ \"aux\",\n+ \"cfg\",\n+ \"bus_master\",\n+ \"bus_slave\",\n+ \"slave_q2a\",\n+ \"sleep\";\n+\n+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;\n+ assigned-clock-rates = <19200000>;\n+\n+ iommu-map = <0x0 &apps_smmu 0x0200 0x1>,\n+ <0x100 &apps_smmu 0x0201 0x1>,\n+ <0x200 &apps_smmu 0x0202 0x1>,\n+ <0x300 &apps_smmu 0x0203 0x1>,\n+ <0x400 &apps_smmu 0x0204 0x1>;\n+\n+ power-domains = <&gcc PCIE_GDSC>;\n+\n+ phys = <&pcie_phy>;\n+ phy-names = \"pciephy\";\n+\n+ resets = <&gcc GCC_PCIE_BCR>;\n+ reset-names = \"pci\";\n+\n+ perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;\n+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\nindex c61930441be0..0e6d11791eec 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n@@ -31,7 +31,6 @@ properties:\n - qcom,pcie-msm8996\n - qcom,pcie-qcs404\n - qcom,pcie-sdm845\n- - qcom,pcie-sdx55\n - items:\n - enum:\n - qcom,pcie-ipq5332\n@@ -210,27 +209,6 @@ allOf:\n - const: config # PCIe configuration space\n - const: mhi # MHI registers\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-sdx55\n- then:\n- properties:\n- reg:\n- minItems: 5\n- maxItems: 6\n- reg-names:\n- minItems: 5\n- items:\n- - const: parf # Qualcomm specific registers\n- - const: dbi # DesignWare PCIe registers\n- - const: elbi # External local bus interface registers\n- - const: atu # ATU address space\n- - const: config # PCIe configuration space\n- - const: mhi # MHI registers\n-\n - if:\n properties:\n compatible:\n@@ -579,32 +557,6 @@ allOf:\n items:\n - const: pci # PCIe core reset\n \n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-sdx55\n- then:\n- properties:\n- clocks:\n- minItems: 7\n- maxItems: 7\n- clock-names:\n- items:\n- - const: pipe # PIPE clock\n- - const: aux # Auxiliary clock\n- - const: cfg # Configuration clock\n- - const: bus_master # Master AXI clock\n- - const: bus_slave # Slave AXI clock\n- - const: slave_q2a # Slave Q2A clock\n- - const: sleep # PCIe Sleep clock\n- resets:\n- maxItems: 1\n- reset-names:\n- items:\n- - const: pci # PCIe core reset\n-\n - if:\n not:\n properties:\n", "prefixes": [ "v2", "02/12" ] }