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GET /api/1.0/patches/2175200/?format=api
{ "id": 2175200, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175200/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217151609.3162665-4-den@valinux.co.jp>", "date": "2025-12-17T15:15:37", "name": "[RFC,v3,03/35] PCI: dwc: ep: Support BAR subrange inbound mapping via address match iATU", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "857382c1907d79fc785505d0134c57172afbb195", "submitter": { "id": 91573, "url": "http://patchwork.ozlabs.org/api/1.0/people/91573/?format=api", "name": "Koichiro Den", "email": "den@valinux.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217151609.3162665-4-den@valinux.co.jp/mbox/", "series": [ { "id": 485709, "url": "http://patchwork.ozlabs.org/api/1.0/series/485709/?format=api", "date": "2025-12-17T15:15:53", "name": "NTB transport backed by endpoint DW eDMA", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485709/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175200/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43176-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=hPgW/alq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n 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bh=TndGji5lg89cVye3iC5pe/TN/3ffkCrfIeu8yWxalNA=;\n b=hPgW/alqqa98WBiHqjMh8aDaTcCc+Y1Ziim0QRJdHjnvWyWIz1OoEQUlpdPO5LBbQumdrGFV+55P4n868OXMgL1yABhx2ZWNvbm6XH0viIpkebDjHyDfkspcycISpuDd+0dUlgG5gNM0fQXwXwzbo6EcVFxwtXAcp/9n30lPYCY=", "From": "Koichiro Den <den@valinux.co.jp>", "To": "Frank.Li@nxp.com,\n\tdave.jiang@intel.com,\n\tntb@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdmaengine@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tnetdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Cc": "mani@kernel.org,\n\tkwilczynski@kernel.org,\n\tkishon@kernel.org,\n\tbhelgaas@google.com,\n\tcorbet@lwn.net,\n\tgeert+renesas@glider.be,\n\tmagnus.damm@gmail.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tvkoul@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tjdmason@kudzu.us,\n\tallenbh@gmail.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\tBasavaraj.Natikar@amd.com,\n\tShyam-sundar.S-k@amd.com,\n\tkurt.schwemmer@microsemi.com,\n\tlogang@deltatee.com,\n\tjingoohan1@gmail.com,\n\tlpieralisi@kernel.org,\n\tutkarsh02t@gmail.com,\n\tjbrunet@baylibre.com,\n\tdlemoal@kernel.org,\n\tarnd@arndb.de,\n\telfring@users.sourceforge.net,\n\tden@valinux.co.jp", "Subject": "[RFC PATCH v3 03/35] PCI: dwc: ep: Support BAR subrange inbound\n mapping via address match iATU", "Date": "Thu, 18 Dec 2025 00:15:37 +0900", "Message-ID": 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pi74Wjy4cO+fJjw8SZ8R+XjjQfmKdkYChZQ8u5xvqPREhP/hfoIBY+urDe1EYAr9eo/zFYS3lu4jc8o2nOv5Dg5DrFct8OJftPu6g/tkQH7vOovkAvAcxqCWtqwqamhqArvn1ub+VVnQhy+jSGcHlyQdSME3gRlsCT011/jCQhQcgH35b4won8LhnGU9SBFanuM/Wc8d33C3SJA3jqPCXody9rMUmjXCz7ZxqNPnlPUU+xtuPRbTgxXoesMky1kzIfhS0514qGRDfwRLK0DWTs4vHhoOC/x1fTnCZ7JG1ln1Qd1NBvYkBQz6q/pCyywn6J4genCNztCori+ujXMv8Xl3QMPsYppIgOAtOgg6OzOhJDs22XrbGKLYphzFol2kamkGKpXDhes5wiokd+DFybFY9yKPmhhOWgUzn3wYyKA9nFV5kQ+vZQrW/2LHrGkfZbwoeIEb3r4o0OH3AyTiCXgq90/318Xenqbp3xAgbsuE2FuziaDP2GwlqaWWg85k/S5obiLkNKqz2z+QZGxgE48rqRXwqCFHtiM4jG+rBbQXI1I55kEXSdLIP7ehX8jBQfAulEAzpFDLfhp6dxv/g8H15kJQVOUmWldqlIndBlcL9NEuO4ioF3d65PhpnSLqKKhUuwHrFZqbXpV9JUEmxLH6maqC75W+YAyWBAzC2L7QAvKrJLAGXW0YZvjvnsJoNu6wyjUiVZz4IRW1EGedBdvE5m+ZgmvFS2FZ+Jhv2scMKzeIgmDYXCB4k9KAaq1z8aeclsNpR0TP/Nszft8IupKAxWHgEOeSHur7jLvbMoOE6NuZhuzHNh6rBHdMADNTWS2hzK1PdFwfbItdhTRrTUUU5O7vw+uJvtoFJgOhB/po7HxdHMY1FO1kThQtouH2FD1/FliVMSfLZauVZCBrk/hr2nZBjGpxQq0OUmibvfMTDJAHuyuNOtyhebragAeDnidXKjSiuaKB6i4gPZXRFTdrXgApiwZK5nQ/5dY+ssS6ljpqrmqrAPRTNOqIW8QwG/oSQS38/+nnQKYtB0/10oOLgyHdGck3mup1sbs+T0OGLngcylorCNNZcCfUl+XSyfL53A+I62L9h+drE1AUeJUiJLY4UIc6/6Dfw3BcGnPCAig2GNmPWOll1OfXS87UCnEZ/SUbpJb9QGNF1SHloZciqL4oqYFh0uOveKcH52p/FI5JhO8ykRIOUZlVfToGEyiv1gyJi0KMRt8jjTL+0j0+tCpwLJIIypq8RC6piNm3LBj88OIosDVN5j481qWn2QsFoXRDjuaVaZQ8IFxZzX6Z9SXIZEIPi7zPsNfdI3qZOq1H1QMd9Rq/bUQalIzwmXHKjJx2esn7p6gNwxoH6OjEESAE9/mcYTqvBQe6yhhYV9EJupdn9xysBNlMpAQRpxQODsVCKuWBzd96Q3y3yG27ddKOwByRXlcIlpb5/AuSeqkATS89jbMsPiyJWiKTMVkGXeOSKW4aC9L0zdKsYbCxW/7fqS55/i4n2YqaGKmbHMq0a5TlCRroS4lyf8BruKSymO2i+9ZSXsjK0i3sz8QQ2o1knVdsCn8DSw0+RTnUIp1+Ls4CGBA7O6poS3RDkBjcdY6fjSBfBCtaUPMApkWEKshy0YcBfA7Q2KimGzk=", "X-OriginatorOrg": "valinux.co.jp", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 40879712-f8d8-4b53-ca2c-08de3d7f3907", "X-MS-Exchange-CrossTenant-AuthSource": "TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Dec 2025 15:16:16.0940\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "7a57bee8-f73d-4c5f-a4f7-d72c91c8c111", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n sA0RavGibqa+QmsKCLSy1hoRre9sVmc2jYsvG/SppcedTBcnH6GTRSg90lJ8zmvzDGS4qvwoPU/B8gbfnZjCPA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "OS9P286MB4633" }, "content": "Extend dw_pcie_ep_set_bar() to support Address Match Mode IB iATU\nwith the new 'submap' field in pci_epf_bar.\n\nThe existing dw_pcie_ep_inbound_atu(), which is for BAR match mode, is\nrenamed to dw_pcie_ep_ib_atu_bar() and the new dw_pcie_ep_ib_atu_addr()\nis introduced, which is for Address match mode.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\n .../pci/controller/dwc/pcie-designware-ep.c | 197 ++++++++++++++++--\n drivers/pci/controller/dwc/pcie-designware.h | 2 +\n drivers/pci/endpoint/pci-epc-core.c | 2 +-\n include/linux/pci-epf.h | 27 +++\n 4 files changed, 215 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex e94cde1a3506..9480aebaa32a 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -139,9 +139,10 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \treturn 0;\n }\n \n-static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,\n-\t\t\t\t dma_addr_t parent_bus_addr, enum pci_barno bar,\n-\t\t\t\t size_t size)\n+/* Bar match mode */\n+static int dw_pcie_ep_ib_atu_bar(struct dw_pcie_ep *ep, u8 func_no, int type,\n+\t\t\t\t dma_addr_t parent_bus_addr, enum pci_barno bar,\n+\t\t\t\t size_t size)\n {\n \tint ret;\n \tu32 free_win;\n@@ -174,6 +175,151 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,\n \treturn 0;\n }\n \n+struct dw_pcie_ib_map {\n+\tstruct list_head\tlist;\n+\tenum pci_barno\t\tbar;\n+\tu64\t\t\tpci_addr;\n+\tu64\t\t\tparent_bus_addr;\n+\tu64\t\t\tsize;\n+\tu32\t\t\tindex;\n+};\n+\n+static struct dw_pcie_ib_map *\n+dw_pcie_ep_find_ib_map(struct dw_pcie_ep *ep, enum pci_barno bar, u64 pci_addr)\n+{\n+\tstruct dw_pcie_ib_map *m;\n+\n+\tlist_for_each_entry(m, &ep->ib_map_list, list) {\n+\t\tif (m->bar == bar && m->pci_addr == pci_addr)\n+\t\t\treturn m;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static u64 dw_pcie_ep_read_bar_assigned(struct dw_pcie_ep *ep, u8 func_no,\n+\t\t\t\t\tenum pci_barno bar, int flags)\n+{\n+\tu32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);\n+\tu32 lo, hi;\n+\tu64 addr;\n+\n+\tlo = dw_pcie_ep_readl_dbi(ep, func_no, reg);\n+\n+\tif (flags & PCI_BASE_ADDRESS_SPACE)\n+\t\treturn lo & PCI_BASE_ADDRESS_IO_MASK;\n+\n+\taddr = lo & PCI_BASE_ADDRESS_MEM_MASK;\n+\tif (!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))\n+\t\treturn addr;\n+\n+\thi = dw_pcie_ep_readl_dbi(ep, func_no, reg + 4);\n+\treturn addr | ((u64)hi << 32);\n+}\n+\n+/* Address match mode */\n+static int dw_pcie_ep_ib_atu_addr(struct dw_pcie_ep *ep, u8 func_no, int type,\n+\t\t\t\t struct pci_epf_bar *epf_bar)\n+{\n+\tstruct pci_epf_bar_submap *submap = epf_bar->submap;\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tenum pci_barno bar = epf_bar->barno;\n+\tstruct dw_pcie_ib_map *m, *new;\n+\tstruct device *dev = pci->dev;\n+\tu64 pci_addr, parent_bus_addr;\n+\tu64 size, off, base;\n+\tunsigned long flags;\n+\tint free_win, ret;\n+\tu32 i;\n+\n+\tif (!epf_bar->num_submap)\n+\t\treturn 0;\n+\n+\tif (!submap)\n+\t\treturn -EINVAL;\n+\n+\tbase = dw_pcie_ep_read_bar_assigned(ep, func_no, bar, epf_bar->flags);\n+\tif (!base) {\n+\t\tdev_err(dev,\n+\t\t\t\"BAR%u not assigned, cannot set up sub-range mappings\\n\",\n+\t\t\tbar);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < epf_bar->num_submap; i++) {\n+\t\toff = submap[i].offset;\n+\t\tsize = submap[i].size;\n+\t\tparent_bus_addr = submap[i].phys_addr;\n+\n+\t\tif (!size)\n+\t\t\tcontinue;\n+\n+\t\tif (off > (~0ULL) - base)\n+\t\t\treturn -EINVAL;\n+\n+\t\tpci_addr = base + off;\n+\n+\t\tnew = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);\n+\t\tif (!new)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tspin_lock_irqsave(&ep->ib_map_lock, flags);\n+\t\tm = dw_pcie_ep_find_ib_map(ep, bar, pci_addr);\n+\t\tif (m) {\n+\t\t\tif (m->parent_bus_addr == parent_bus_addr &&\n+\t\t\t m->size == size) {\n+\t\t\t\tspin_unlock_irqrestore(&ep->ib_map_lock, flags);\n+\t\t\t\tdevm_kfree(dev, new);\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tret = dw_pcie_prog_inbound_atu(pci, m->index, type,\n+\t\t\t\t\t\t parent_bus_addr, pci_addr,\n+\t\t\t\t\t\t size);\n+\t\t\tif (!ret) {\n+\t\t\t\tm->parent_bus_addr = parent_bus_addr;\n+\t\t\t\tm->size = size;\n+\t\t\t}\n+\t\t\tspin_unlock_irqrestore(&ep->ib_map_lock, flags);\n+\t\t\tdevm_kfree(dev, new);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfree_win = find_first_zero_bit(ep->ib_window_map,\n+\t\t\t\t\t pci->num_ib_windows);\n+\t\tif (free_win >= pci->num_ib_windows) {\n+\t\t\tspin_unlock_irqrestore(&ep->ib_map_lock, flags);\n+\t\t\tdevm_kfree(dev, new);\n+\t\t\treturn -ENOSPC;\n+\t\t}\n+\t\tset_bit(free_win, ep->ib_window_map);\n+\n+\t\tnew->bar = bar;\n+\t\tnew->index = free_win;\n+\t\tnew->pci_addr = pci_addr;\n+\t\tnew->parent_bus_addr = parent_bus_addr;\n+\t\tnew->size = size;\n+\t\tlist_add_tail(&new->list, &ep->ib_map_list);\n+\n+\t\tspin_unlock_irqrestore(&ep->ib_map_lock, flags);\n+\n+\t\tret = dw_pcie_prog_inbound_atu(pci, free_win, type,\n+\t\t\t\t\t parent_bus_addr, pci_addr, size);\n+\t\tif (ret) {\n+\t\t\tspin_lock_irqsave(&ep->ib_map_lock, flags);\n+\t\t\tlist_del(&new->list);\n+\t\t\tclear_bit(free_win, ep->ib_window_map);\n+\t\t\tspin_unlock_irqrestore(&ep->ib_map_lock, flags);\n+\t\t\tdevm_kfree(dev, new);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,\n \t\t\t\t struct dw_pcie_ob_atu_cfg *atu)\n {\n@@ -204,17 +350,34 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n \tenum pci_barno bar = epf_bar->barno;\n-\tu32 atu_index = ep->bar_to_atu[bar] - 1;\n+\tstruct dw_pcie_ib_map *m, *tmp;\n+\tu32 atu_index;\n \n-\tif (!ep->bar_to_atu[bar])\n+\tif (!ep->epf_bar[bar])\n \t\treturn;\n \n \t__dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags);\n \n-\tdw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);\n-\tclear_bit(atu_index, ep->ib_window_map);\n+\t/* BAR match iATU */\n+\tif (ep->bar_to_atu[bar]) {\n+\t\tatu_index = ep->bar_to_atu[bar] - 1;\n+\t\tdw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);\n+\t\tclear_bit(atu_index, ep->ib_window_map);\n+\t\tep->bar_to_atu[bar] = 0;\n+\t}\n+\n+\t/* Address match iATU */\n+\tguard(spinlock_irqsave)(&ep->ib_map_lock);\n+\tlist_for_each_entry_safe(m, tmp, &ep->ib_map_list, list) {\n+\t\tif (m->bar != bar)\n+\t\t\tcontinue;\n+\t\tdw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, m->index);\n+\t\tclear_bit(m->index, ep->ib_window_map);\n+\t\tlist_del(&m->list);\n+\t\tkfree(m);\n+\t}\n+\n \tep->epf_bar[bar] = NULL;\n-\tep->bar_to_atu[bar] = 0;\n }\n \n static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci,\n@@ -364,10 +527,14 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \t\t/*\n \t\t * We can only dynamically change a BAR if the new BAR size and\n \t\t * BAR flags do not differ from the existing configuration.\n+\t\t * When 'use_submap' is true and the intention is to create\n+\t\t * sub-range mappings perhaps incrementally, epf_bar->size\n+\t\t * does not mean anything so no need to validate it.\n \t\t */\n \t\tif (ep->epf_bar[bar]->barno != bar ||\n-\t\t ep->epf_bar[bar]->size != size ||\n-\t\t ep->epf_bar[bar]->flags != flags)\n+\t\t ep->epf_bar[bar]->flags != flags ||\n+\t\t ep->epf_bar[bar]->use_submap != epf_bar->use_submap ||\n+\t\t (!epf_bar->use_submap && ep->epf_bar[bar]->size != size))\n \t\t\treturn -EINVAL;\n \n \t\t/*\n@@ -408,8 +575,12 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \telse\n \t\ttype = PCIE_ATU_TYPE_IO;\n \n-\tret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar,\n-\t\t\t\t size);\n+\tif (epf_bar->use_submap)\n+\t\tret = dw_pcie_ep_ib_atu_addr(ep, func_no, type, epf_bar);\n+\telse\n+\t\tret = dw_pcie_ep_ib_atu_bar(ep, func_no, type,\n+\t\t\t\t\t epf_bar->phys_addr, bar, size);\n+\n \tif (ret)\n \t\treturn ret;\n \n@@ -1120,6 +1291,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)\n \tstruct device *dev = pci->dev;\n \n \tINIT_LIST_HEAD(&ep->func_list);\n+\tINIT_LIST_HEAD(&ep->ib_map_list);\n+\tspin_lock_init(&ep->ib_map_lock);\n \tep->msi_iatu_mapped = false;\n \tep->msi_msg_addr = 0;\n \tep->msi_map_size = 0;\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex f555926a526e..1770a2318557 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -476,6 +476,8 @@ struct dw_pcie_ep {\n \tphys_addr_t\t\t*outbound_addr;\n \tunsigned long\t\t*ib_window_map;\n \tunsigned long\t\t*ob_window_map;\n+\tstruct list_head\tib_map_list;\n+\tspinlock_t\t\tib_map_lock;\n \tvoid __iomem\t\t*msi_mem;\n \tphys_addr_t\t\tmsi_mem_phys;\n \tstruct pci_epf_bar\t*epf_bar[PCI_STD_NUM_BARS];\ndiff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c\nindex ca7f19cc973a..2b95dbc7242a 100644\n--- a/drivers/pci/endpoint/pci-epc-core.c\n+++ b/drivers/pci/endpoint/pci-epc-core.c\n@@ -604,7 +604,7 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \t (epc_features->bar[bar].fixed_size != epf_bar->size))\n \t\treturn -EINVAL;\n \n-\tif (!is_power_of_2(epf_bar->size))\n+\tif (!epf_bar->num_submap && !is_power_of_2(epf_bar->size))\n \t\treturn -EINVAL;\n \n \tif ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||\ndiff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h\nindex 48f68c4dcfa5..126647b9f01e 100644\n--- a/include/linux/pci-epf.h\n+++ b/include/linux/pci-epf.h\n@@ -110,6 +110,25 @@ struct pci_epf_driver {\n \n #define to_pci_epf_driver(drv) container_of_const((drv), struct pci_epf_driver, driver)\n \n+/**\n+ * struct pci_epf_bar_submap - represents a BAR subrange for inbound mapping\n+ * @phys_addr: physical address that should be mapped to the BAR subrange\n+ * @size: the size of the subrange to be mapped\n+ * @offset: The byte offset from the BAR base\n+ * @mapped: Set to true if already mapped\n+ *\n+ * When @use_submap is set in struct pci_epf_bar, an EPF driver may describe\n+ * multiple independent mappings within a single BAR. An EPC driver can use\n+ * these descriptors to set up the required address translation (e.g. multiple\n+ * inbound iATU regions) without requiring the whole BAR to be mapped at once.\n+ */\n+struct pci_epf_bar_submap {\n+\tdma_addr_t\tphys_addr;\n+\tsize_t\t\tsize;\n+\tsize_t\t\toffset;\n+\tbool\t\tmapped;\n+};\n+\n /**\n * struct pci_epf_bar - represents the BAR of EPF device\n * @phys_addr: physical address that should be mapped to the BAR\n@@ -119,6 +138,9 @@ struct pci_epf_driver {\n * requirement\n * @barno: BAR number\n * @flags: flags that are set for the BAR\n+ * @use_submap: set true to request subrange mappings within this BAR\n+ * @num_submap: number of entries in @submap\n+ * @submap: array of subrange descriptors allocated by the caller\n */\n struct pci_epf_bar {\n \tdma_addr_t\tphys_addr;\n@@ -127,6 +149,11 @@ struct pci_epf_bar {\n \tsize_t\t\tmem_size;\n \tenum pci_barno\tbarno;\n \tint\t\tflags;\n+\n+\t/* Optional sub-range mapping */\n+\tbool\t\tuse_submap;\n+\tint\t\tnum_submap;\n+\tstruct pci_epf_bar_submap\t*submap;\n };\n \n /**\n", "prefixes": [ "RFC", "v3", "03/35" ] }