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GET /api/1.0/patches/2175186/?format=api
{ "id": 2175186, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175186/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217143150.94463-7-philmd@linaro.org>", "date": "2025-12-17T14:31:42", "name": "[06/14] system/physmem: Use explicit endianness in subpage_ops::read/write()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0fe6136abd2a7f41a529871cc432d1baef4454c8", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.0/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217143150.94463-7-philmd@linaro.org/mbox/", "series": [ { "id": 485701, "url": "http://patchwork.ozlabs.org/api/1.0/series/485701/?format=api", "date": "2025-12-17T14:31:37", "name": "system/memory: Clean ups around address_space_ldst() endian variants", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485701/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175186/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ElsVR5X1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" <mst@redhat.com>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n David Hildenbrand <david@kernel.org>, Peter Xu <peterx@redhat.com>", "Subject": "[PATCH 06/14] system/physmem: Use explicit endianness in\n subpage_ops::read/write()", "Date": "Wed, 17 Dec 2025 15:31:42 +0100", "Message-ID": "<20251217143150.94463-7-philmd@linaro.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20251217143150.94463-1-philmd@linaro.org>", "References": "<20251217143150.94463-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Replace the ldn_p/stn_p() calls by their explicit endianness\nvariants. Duplicate the MemoryRegionOps, replacing the single\nDEVICE_NATIVE_ENDIAN entry by a pair of LITTLE and BIG ones.\nSelect the proper MemoryRegionOps in subpage_init().\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n system/physmem.c | 81 ++++++++++++++++++++++++++++++++++++++----------\n 1 file changed, 64 insertions(+), 17 deletions(-)", "diff": "diff --git a/system/physmem.c b/system/physmem.c\nindex 1292f49095f..d8465f085bd 100644\n--- a/system/physmem.c\n+++ b/system/physmem.c\n@@ -2896,8 +2896,8 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,\n static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,\n bool is_write, MemTxAttrs attrs);\n \n-static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,\n- unsigned len, MemTxAttrs attrs)\n+static MemTxResult subpage_read_le(void *opaque, hwaddr addr, uint64_t *data,\n+ unsigned len, MemTxAttrs attrs)\n {\n subpage_t *subpage = opaque;\n uint8_t buf[8];\n@@ -2911,12 +2911,32 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,\n if (res) {\n return res;\n }\n- *data = ldn_p(buf, len);\n+ *data = ldn_le_p(buf, len);\n return MEMTX_OK;\n }\n \n-static MemTxResult subpage_write(void *opaque, hwaddr addr,\n- uint64_t value, unsigned len, MemTxAttrs attrs)\n+static MemTxResult subpage_read_be(void *opaque, hwaddr addr, uint64_t *data,\n+ unsigned len, MemTxAttrs attrs)\n+{\n+ subpage_t *subpage = opaque;\n+ uint8_t buf[8];\n+ MemTxResult res;\n+\n+#if defined(DEBUG_SUBPAGE)\n+ printf(\"%s: subpage %p len %u addr \" HWADDR_FMT_plx \"\\n\", __func__,\n+ subpage, len, addr);\n+#endif\n+ res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);\n+ if (res) {\n+ return res;\n+ }\n+ *data = ldn_be_p(buf, len);\n+ return MEMTX_OK;\n+}\n+\n+static MemTxResult subpage_write_le(void *opaque, hwaddr addr,\n+ uint64_t value, unsigned len,\n+ MemTxAttrs attrs)\n {\n subpage_t *subpage = opaque;\n uint8_t buf[8];\n@@ -2926,7 +2946,23 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,\n \" value %\"PRIx64\"\\n\",\n __func__, subpage, len, addr, value);\n #endif\n- stn_p(buf, len, value);\n+ stn_le_p(buf, len, value);\n+ return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);\n+}\n+\n+static MemTxResult subpage_write_be(void *opaque, hwaddr addr,\n+ uint64_t value, unsigned len,\n+ MemTxAttrs attrs)\n+{\n+ subpage_t *subpage = opaque;\n+ uint8_t buf[8];\n+\n+#if defined(DEBUG_SUBPAGE)\n+ printf(\"%s: subpage %p len %u addr \" HWADDR_FMT_plx\n+ \" value %\"PRIx64\"\\n\",\n+ __func__, subpage, len, addr, value);\n+#endif\n+ stn_be_p(buf, len, value);\n return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);\n }\n \n@@ -2944,15 +2980,26 @@ static bool subpage_accepts(void *opaque, hwaddr addr,\n len, is_write, attrs);\n }\n \n-static const MemoryRegionOps subpage_ops = {\n- .read_with_attrs = subpage_read,\n- .write_with_attrs = subpage_write,\n- .impl.min_access_size = 1,\n- .impl.max_access_size = 8,\n- .valid.min_access_size = 1,\n- .valid.max_access_size = 8,\n- .valid.accepts = subpage_accepts,\n- .endianness = DEVICE_NATIVE_ENDIAN,\n+static const MemoryRegionOps subpage_ops[2] = {\n+ [0 ... 1] = {\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 8,\n+ },\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 8,\n+ .accepts = subpage_accepts,\n+ },\n+ },\n+\n+ [0].endianness = DEVICE_LITTLE_ENDIAN,\n+ [0].read_with_attrs = subpage_read_le,\n+ [0].write_with_attrs = subpage_write_le,\n+\n+ [1].endianness = DEVICE_BIG_ENDIAN,\n+ [1].read_with_attrs = subpage_read_be,\n+ [1].write_with_attrs = subpage_write_be,\n };\n \n static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,\n@@ -2983,8 +3030,8 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base)\n mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));\n mmio->fv = fv;\n mmio->base = base;\n- memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,\n- NULL, TARGET_PAGE_SIZE);\n+ memory_region_init_io(&mmio->iomem, NULL, &subpage_ops[target_big_endian()],\n+ mmio, NULL, TARGET_PAGE_SIZE);\n mmio->iomem.subpage = true;\n #if defined(DEBUG_SUBPAGE)\n printf(\"%s: %p base \" HWADDR_FMT_plx \" len %08x\\n\", __func__,\n", "prefixes": [ "06/14" ] }